CN106653679A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN106653679A CN106653679A CN201510740015.6A CN201510740015A CN106653679A CN 106653679 A CN106653679 A CN 106653679A CN 201510740015 A CN201510740015 A CN 201510740015A CN 106653679 A CN106653679 A CN 106653679A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor device and a forming method thereof. The forming method of the semiconductor device includes providing a substrate, a gate structure being formed on the surface of the substrate, both sides of the gate structure each having an interconnection region, source regions and drain regions located at both sides of the gate structure being formed in the substrate of the interconnection region, and each interconnection region stretching across a plurality of source regions or a plurality of drain regions; forming first medium layers on the surface of the substrate and the surface of the gate structure; etching the first medium layers located on the interconnection regions till the source region surfaces or drain region surfaces are exposed, forming through holes being formed in the intersection regions, and each through hole stretching across all the source regions or all the drain regions in an interconnection region; forming interconnection layers filling the through holes; and forming zeroth conducting layers on top surfaces of the interconnection layers, each zeroth conducting layer being electrically connected with all the source regions or all the drain regions in an interconnection region. The forming method of the semiconductor device increases process flexibility, and improves electrical properties of the semiconductor device that is formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor devices and its formation side
Method.
Background technology
Metal interconnection structure is structure indispensable in semiconductor devices, for realize active area with it is active
Interconnection between interconnection between area, the interconnection between transistor and transistor or different layers metal wire,
Complete the transmission and control of signal.Therefore, in semiconductor fabrication, the formation of metal interconnection structure
Performance and semiconductor manufacturing cost to semiconductor devices has very big impact.In order to increase device
Density, the size of semiconductor devices in integrated circuits has been increasingly reduced within a few seconds, in order to realize each partly
The electrical connection of conductor device, it usually needs multilayer interconnection structure.
General, in the rear end interconnection process of fabrication of semiconductor device, first layer metal layer (M1)
Need to form electricity and the active device structures (comprising source and drain areas and grid structure region) of lower floor between
Connection.Therefore, before first layer metal layer is formed, it usually needs be pre-formed the office of semiconductor devices
Portion's interconnection structure (Local Interconnect).The local interlinkage structure is included：With the source-drain area of lower floor
The level 0 metal level (M0) of electrical connection and the level 0 grid electrically connected between grid structure region
Metal level (M0G).
However, the performance of the semiconductor devices formed in prior art needs further raising.
The content of the invention
The problem that the present invention is solved is to provide a kind of semiconductor devices and forming method thereof, improves half for being formed
The electric property of conductor device.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：There is provided
Substrate, the substrate surface is formed with grid structure, and the grid structure both sides are respectively with an interconnection
Area, is respectively formed with the source region positioned at grid structure both sides and drain region in the substrate of the interconnecting area, wherein,
Each interconnecting area is across several source regions or several drain regions；On the substrate surface and grid structure surface
Form first medium layer；First medium layer of the etching above interconnecting area, until exposing area surface
Or drain region surface, through hole is formed above the interconnecting area, and each through hole is complete in an interconnecting area
Portion's source region or whole drain regions；Form the interconnection layer of the full through hole of filling；In the interconnection layer top surface
Form level 0 conductive layer.
Optionally, the level 0 conductive layer is located at interconnection layer portions top surface.
Optionally, the level 0 conductive layer is also located at first medium layer segment top surface.
Optionally, the first medium layer top and grid structure top are flush or below grid structure top.
Optionally, forming the processing step of the through hole includes：Formed in the first medium layer surface and had
There is the first graph layer of the first opening, first opening is located at interconnecting area top, and across each interconnection
Whole source regions or whole drain regions in area；With first graph layer as mask, carve along the described first opening
First medium layer of the erosion above interconnecting area, forms the through hole；Remove first graph layer.
Optionally, forming the processing step of first graph layer includes：In the first medium layer surface
Form the first mask layer；The second mask layer, and first mask are formed in the first mask layer surface
Layer is different with the material of the second mask layer；The first photoresist layer, institute are formed in the second mask layer surface
State the first photoresist layer and be projected on the figure of grid structure top surface and at least cover between adjacent interconnection area
The whole top surface of grid structure, the region projection between adjacent first photoresist layer is in the figure of substrate surface
Shape is the first projecting figure, and first projecting figure covers interconnecting area and adjacent with the interconnecting area
Separation layer；With first photoresist layer as mask, second mask layer is etched until exposing first
Mask layer surface；Remove first photoresist layer；The second mask layer surface and expose after etching
The first mask layer surface form the second photoresist layer, second photoresist layer is projected on substrate surface
Figure is the second projecting figure, and the second projecting figure correspondence is located in the first projecting figure, and described second
Projecting figure covers separation layer；With second photoresist layer as mask, first exposed described in etching
Mask layer is until expose first medium layer surface, the formation first in first mask layer is open, institute
The first mask layer after etching is stated as the first graph layer；Remove second photoresist layer.
Optionally, forming the processing step of the level 0 conductive layer includes：The table at the top of the interconnection layer
Face and first medium layer top surface form conducting film；The graphical conducting film, forms described the
Zero layer conductive layer.
Optionally, forming the processing step of the level 0 conductive layer includes：The table at the top of the interconnection layer
Face and first medium layer top surface form second dielectric layer；In the second dielectric layer top surface shape
Into the second graph layer with the second opening, second open bottom exposes interconnection layer portions top table
Face；With the second graph layer as mask, along the second opening etching second dielectric layer, until exposure
Go out interconnection layer top surface, in the second dielectric layer groove is formed；Form the full groove of filling
Level 0 conductive layer；Remove the second graph layer.
Optionally, the material of the interconnection layer is one or more in copper, aluminium, tungsten, gold, silver or titanium；
The material of the level 0 conductive layer is one or more in copper, aluminium, tungsten, gold, silver or titanium.
Optionally, each grid structure both sides are respectively formed with multiple source regions or multiple drain regions, each interconnection
Area is across the plurality of source region or multiple drain regions.
Optionally, the substrate includes：Substrate；Positioned at some discrete fin of substrate surface；It is located at
The separation layer of the substrate surface, the separation layer covers the partial sidewall surface of fin, and the isolation
Layer top is less than fin top；Wherein, the grid structure is across the fin, and the grid structure
Positioned at part insulation surface and the side wall and top surface of fin, position is distinguished in the source region and drain region
In the fin of the grid structure both sides.
Optionally, the quantity of the fin is more than 1, and some fins are arranged in parallel, and the grid structure is horizontal
Across at least one fin；The quantity of the grid structure is more than 1, and some grid structures are arranged in parallel, often
One grid structure is across multiple fins.
Optionally, source region or drain region of each interconnecting area in the corresponding multiple fins of same grid structure.
Optionally, also including step：The level 0 grid that formation is electrically connected with the conductive grid in grid structure
Flush with level 0 conductive layer at the top of conductive layer, and the level 0 grid conductive layer.
The present invention also provides a kind of semiconductor devices, including：Substrate, the substrate surface is formed with grid
Structure, the grid structure both sides have respectively an interconnecting area, difference shape in the substrate of the interconnecting area
Into the source region and drain region that have positioned at grid structure both sides, wherein, each interconnecting area across several source regions or
Several drain regions；Positioned at the first medium layer on the substrate surface and grid structure surface；Positioned at described mutual
The even through hole in the first medium floor of area top, the through hole exposes area surface or drain region surface, and often
Whole source regions or whole drain region of one through hole in each interconnecting area；The interconnection layer of the full through hole of filling,
Whole source regions or whole drain region of the interconnection layer I in each interconnecting area I；Positioned at the interconnection layer top
The level 0 conductive layer on portion surface.
Optionally, the level 0 conductive layer is located at interconnection layer portions top surface.
Optionally, the level 0 conductive layer is also located at first medium layer segment top surface.
Optionally, the substrate includes：Substrate；Positioned at some discrete fin of substrate surface；It is located at
The separation layer of the substrate surface, the separation layer covers the partial sidewall surface of fin, and the isolation
Layer top is less than fin top；Wherein, the grid structure is across the fin, and the grid structure
Positioned at part insulation surface and the side wall and top surface of fin, position is distinguished in the source region and drain region
In the fin of the grid structure both sides.
Optionally, the quantity of the fin is more than 1, and some fins are arranged in parallel, and the grid structure is horizontal
Across at least one fin；The quantity of the grid structure is more than 1, and some grid structures are arranged in parallel, often
One grid structure across multiple fins, wherein, each interconnecting area is corresponding multiple across same grid structure
Source region or drain region in fin.
Optionally, also include：The level 0 grid conductive layer electrically connected with conductive grid in the grid structure,
And the level 0 grid conductive layer top flushes with level 0 conductive layer.
Compared with prior art, technical scheme has advantages below：
The present invention is provided in the technical scheme of method for forming semiconductor devices, substrate surface and grid structure table
Face forms first medium layer；First medium layer of the etching above interconnecting area, until exposing source region table
Face or drain region surface, form through hole, and whole of each through hole in an interconnecting area above interconnecting area
Source region or whole drain regions；Then, the interconnection layer of the full through hole of filling is formed so that the interconnection layer position
In area surface or drain region surface, and each interconnection layer is by the whole source regions in an interconnecting area or whole drain regions
It is electrically connected；Then, level 0 conductive layer, each level 0 are formed in the interconnection layer top surface
Conductive layer is electrically connected with the whole source regions in an interconnecting area or whole drain regions.In the present invention, due to being formed
Be initially formed interconnection layer before level 0 conductive layer, the interconnection layer by the whole source regions in interconnecting area or
Whole drain region electrical connections, therefore the level 0 conductive layer of formation only needs to be contacted with interconnection layer in the present invention,
The purpose that level 0 conductive layer is electrically connected with the whole source regions in interconnecting area or whole drain regions is can be realized as,
So that form the technological flexibility of semiconductor devices increasing, whole source regions in level 0 conductive layer and interconnecting area
Or the electrical connection properties between whole drain regions are good, it is to avoid some source regions in interconnecting area of the prior art
Or the poor problem of electrical connection properties between drain region and level 0 conductive layer, so as to improve the electricity of semiconductor devices
Learn performance.
Further, first medium layer top with grid structure top flush or below grid structure top,
So that the via depth that etching first medium layer is formed is shallower, the through hole has less vertical wide ratio, from
And the position precision for passing through and pattern accuracy for being formed is improved, and the ability of interconnection layer filling through hole is obtained
To raising, it is to avoid occur hole in the interconnection layer of formation, improve the interconnection layer for being formed position precision and
Pattern accuracy.
Further, forming the processing step of the through hole includes：Formed in the first medium layer surface
The first graph layer with the first opening, first opening is located at interconnecting area top, and across each mutual
Whole source regions even in area or whole drain regions；With first graph layer as mask, along the described first opening
First medium layer of the etching above interconnecting area, forms the through hole；Remove first graph layer.
Wherein, the method for forming first graph layer is Dual graphing method, by the first different mask of material
Layer and the second mask layer carry out secondary image, so as to form first graph layer, further increase
The position precision and pattern accuracy of the through hole of formation, and meet device miniaturization miniaturization development become
Gesture.
The present invention also provides a kind of structural behaviour superior semiconductor devices, including：Substrate, the substrate
Surface is formed with grid structure, and the grid structure both sides have respectively an interconnecting area, the interconnecting area
Substrate in be respectively formed with source region and drain region positioned at grid structure both sides, wherein, each interconnecting area is horizontal
Across several source regions or several drain regions；Positioned at the first medium on the substrate surface and grid structure surface
Layer；Positioned at the interconnecting area top first medium layer in through hole, the through hole expose area surface or
Drain region surface, and whole source regions or whole drain region of each through hole in each interconnecting area；The full institute of filling
State the interconnection layer of through hole, whole source regions or whole drain region of the interconnection layer I in each interconnecting area I；
Positioned at the level 0 conductive layer of the interconnection layer top surface.In the semiconductor devices that the present invention is provided, institute
Stating level 0 conductive layer only needs to be contacted with interconnection layer, therefore the level 0 in the semiconductor devices is conductive
The position of layer and morphology selection scope are wide, by the position and the pattern that rationally arrange level 0 conductive layer, energy
Enough semiconductor device layout designs for more being optimized, and cause semiconductor devices that there is higher electricity
Performance And Reliability.
Description of the drawings
Fig. 1 to Fig. 2 is the structural representation of prior art semiconductor devices；
The structural representation of the semiconductor devices forming process that Fig. 3 to Figure 19 is provided for one embodiment of the invention
Figure.
Specific embodiment
From background technology, the performance of the semiconductor devices that prior art is formed needs further raising.
Research finds, is prior art semiconductor devices top view with reference to Fig. 1 and Fig. 2, Fig. 1, and Fig. 2 is
Along the profile in XX1 directions, form the processing step of the semiconductor devices includes Fig. 1：Substrate is provided
101, positioned at the fin 102 on the surface of substrate 101, positioned at the surface of substrate 101 and the side wall table of fin 102
The separation layer 103 in face, the top of the separation layer 103 is less than the top of fin 102, across the fin 102
Grid structure 113, the grid structure 113 covers the atop part surface of fin 102 and sidewall surfaces,
Wherein, the grid structure both sides have respectively an interconnecting area, respectively positioned at the both sides of grid structure 113
Source region or drain region in fin 102, source region or drain region of the interconnecting area in several fins 102；
First medium layer 104 is formed on the surface of the separation layer 103 and the surface of grid structure 113, described first
The top of dielectric layer 104 flushes with the top of grid structure 113；Formed on the surface of first medium layer 104
Second dielectric layer 105；The through hole in the first medium layer 104 and second dielectric layer 105 is formed,
The through hole is located at interconnecting area top, and whole source regions or whole drain region of the through hole in interconnecting area；
Form the level 0 conductive layer 106 of the full through hole of filling；Form the ditch through the second dielectric layer 105
Groove, the groove is located at grid structure top, and the conductive grid at the groove exposure in grid structure
Surface；Form the level 0 grid conductive layer of the full groove of filling.
In prior art, it is contemplated that level 0 grid conductive layer top flushes or high with level 0 conductive layer top
Degree difference is less, and the top of grid structure 113 is should be higher than that at the top of the dielectric layer on the surface of separation layer 103,
Therefore prior art dielectric layer includes first medium layer 104 and positioned at the top surface of first medium layer 104
Second dielectric layer 105.Before level 0 conductive layer 106 is formed, etching is needed to be located at source region or drain region
The dielectric layer of top forms through hole, full level 0 conductive layer 106 is then filled in through hole, due to being given an account of
The thickness of matter layer is first medium layer 104 and the thickness sum of second dielectric layer 105, therefore prior art
The via depth of middle formation is deeper, and the vertical wide ratio of the through hole is big, the through hole formed using etching technics
The probability that deviation occur in position and pattern is big.Especially when the size of semiconductor devices is less and less, more
It is easily caused through hole and does not expose area surface or the drain region surface that some should be exposed, in turn results in
The electric property of semiconductor devices is deteriorated.
For this purpose, the present invention provides a kind of forming method of semiconductor devices, there is provided substrate, the substrate table
Face is formed with grid structure, and the grid structure both sides have respectively an interconnecting area, the interconnecting area
The source region positioned at grid structure both sides and drain region are respectively formed with substrate, wherein, each interconnecting area across
Several source regions or several drain regions；First medium layer is formed in the substrate surface and grid structure surface；
First medium layer of the etching above interconnecting area, until area surface or drain region surface are exposed, in institute
State interconnecting area top and form through hole, and whole source regions or all leakage of each through hole in each interconnecting area
Area；Form the interconnection layer of the full through hole of filling；It is conductive level 0 to be formed in the interconnection layer top surface
Layer.The present invention forms first interconnection layer in the first medium layer of thinner thickness, and the interconnection layer will be each
Whole source regions of interconnecting area or whole drain region electrical connections, and the interconnection layer has higher position precision
With pattern accuracy；Then, level 0 conductive layer is formed in interconnection layer top surface, the level 0 is led
Electric layer only needs to be contacted between interconnection layer, it becomes possible to make complete in level 0 conductive layer and each interconnecting area
Portion's source region or whole drain region electrical connections, the technological flexibility of the level 0 conductive layer of formation increases, and partly leads
The electric property of body device is improved.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
The structural representation of the semiconductor devices forming process that Fig. 3 to Figure 19 is provided for one embodiment of the invention
Figure.
With reference to Fig. 3 to Fig. 5, Fig. 3 is top view, and Fig. 4 shows for cross-section structures of the Fig. 3 along YY1 directions
It is intended to, Fig. 5 is cross-sectional views of the Fig. 3 along ZZ1 directions, there is provided substrate, the substrate surface
Grid structure is formed with, the grid structure both sides have respectively interconnecting area I, interconnecting area I
The source region (sign) positioned at grid structure both sides and drain region (sign) are respectively formed with substrate, its
In, each interconnecting area I is across several source regions or several drain regions.
In the present embodiment, the semiconductor devices of formation is fin field effect pipe, and the substrate includes：Substrate
201, positioned at some discrete fin 202 on the surface of substrate 201, positioned at the separation layer on the surface of substrate 201
203, the separation layer 203 covers the partial sidewall surface of fin 202, and the top of the separation layer 203
Less than the top of fin 202.The grid structure is across fin 202, and the grid structure covers fin
202 atop part and sidewall surfaces and the surface of part separation layer 203.
In another embodiment, the semiconductor devices is planar transistor, and the substrate is planar substrates,
The planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate
Or germanium substrate on insulator, glass substrate or III-V substrate (such as gallium nitride substrate or arsenic
Gallium substrate etc.), grid structure is formed at the plane.
The material of the substrate 201 be silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate or the germanium substrate on insulator on insulator to state substrate 201；The fin 202
Material include silicon, germanium, SiGe, carborundum, GaAs or gallium indium；The separation layer 203 is made
For the isolation structure of semiconductor devices, play a part of the adjacent fin 202 of electric isolution, the separation layer 203
Material be silica, silicon nitride or silicon oxynitride.In the present embodiment, the substrate 201 is silicon substrate,
The material of the fin 202 is silicon, and the material of the separation layer 203 is silica.
Each grid structure both sides are respectively formed with multiple source regions or multiple drain regions, and each interconnecting area I is across institute
State multiple source regions or multiple drain regions.In the present embodiment, the quantity of the fin 202 is more than 1, and the fin
Portion 202 is arranged in parallel, and the grid structure is across at least one fin 202；The quantity of the grid structure
Also greater than 1, and the grid structure is arranged in parallel, orientation and the fin 202 of the grid structure
Orientation is mutually perpendicular to, and each grid structure is across multiple fins 202；Each interconnecting area I is across same
Source region or drain region in the corresponding multiple fins 202 of one grid structure.
In a specific embodiment, each interconnecting area I is across corresponding 2 fins of same grid structure
Source region or drain region in 202；In other specific embodiments, each interconnecting area can also be across same grid
Source region or drain region in corresponding several fins of structure, described several are arbitrary natural number more than 2
It is individual.
The source region and drain region are also formed with stressor layers (sign), and the material of the stressor layers is carborundum
Or SiGe.When the material of the stressor layers is carborundum, doped with N-type ion in the stressor layers,
For example, P, As or Sb；When the material of the stressor layers is SiGe, doped with P in the stressor layers
Type ion, for example, B, Ga or In.The present embodiment has been correspondingly formed independence with each grid structure both sides
Source region or drain region as an example, in other embodiments, neighboring gate structures can also have doped region
As respective source region or drain region, i.e. have common source drain structure between neighboring gate structures.
The grid structure includes：Gate dielectric layer 211, positioned at the work-function layer on the surface of gate dielectric layer 211
212 and positioned at the conductive grid 213 on the surface of work-function layer 212.In the present embodiment, the grid knot
Structure also includes：Positioned at the sidewall surfaces of gate dielectric layer 211, the sidewall surfaces of work-function layer 212 and conductive gate
The side wall (not shown) of the sidewall surfaces of pole 213.
The material of the gate dielectric layer 211 is high-k gate dielectric material, and high-k gate dielectric material is HfO2、
HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3.The work-function layer 212
Material be N-type work function material or p-type work function material, wherein, N-type work function material be TiAl,
TaAlN, TiAlN, MoN, TaCN or AlN, p-type work function material is Ta, TiN, TaN, TaSiN
Or TiSiN.The material of the conductive grid 213 is Al, Cu, Ag, Au, Pt, Ni, Ti or W.
In the present embodiment, the grid structure also includes：Positioned at covering firmly for the top surface of conductive grid 213
Film layer 206, the hard mask layer 206 can play a part of to protect conductive grid 213.In the present embodiment,
The material of the hard mask layer 206 is silicon nitride.In other embodiments, the material of the hard mask layer
Can also be silicon oxynitride or carbon silicon oxynitride.
In other embodiments, the grid structure can also be pseudo- grid structure (dummy gate), wherein,
Grid structure is single layer structure or laminated construction.
With continued reference to Fig. 3 to Fig. 5, in the grid structure top surface and sidewall surfaces and substrate table
Face forms interlayer dielectric layer 204.
It should be noted that for the ease of illustrating and illustrating, fin 202 and grid are illustrate only in Fig. 3
The position relationship of pole structure, interlayer dielectric layer 204 not shown in Fig. 3, what is provided in subsequent process steps bows
The complete structure of view also not shown semiconductor devices.
In the present embodiment, the top of the interlayer dielectric layer 204 flushes with grid structure top.In other realities
In applying example, the interlayer dielectric layer top is less than grid structure top；Or, the interlayer dielectric layer top
Portion is higher than grid structure top.
The material of the interlayer dielectric layer 204 is the one kind or many in silica, silicon nitride, silicon oxynitride
Kind, formation process includes chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.
In the present embodiment, the material of the interlayer dielectric layer 204 is silica, and formation process includes plasma
Strengthen chemical vapor deposition (PECVD) technique.
It is the schematic diagram on the basis of Fig. 4 with reference to Fig. 6 and Fig. 7, Fig. 6, Fig. 7 is to illustrate on the basis of Fig. 5
Figure, first graph layer 207 with the first opening 208, institute are formed on the surface of first medium layer 204
State the first opening 208 and be located at interconnecting area I top, and the whole source regions or whole in each interconnecting area I
Drain region.
In the present embodiment, the projecting figure that first opening 208 is projected on substrate surface is paved with described mutual
Connect area I, so as to ensure that the interconnection layer being subsequently formed can be by the whole source regions or whole in each interconnecting area I
Drain region electrically connects.
The material of first graph layer 207 be silica, silicon nitride, silicon oxynitride, carbon silicon oxynitride,
Titanium nitride or tantalum nitride.The material of first graph layer 207 is different from the material of first medium layer 204,
In the present embodiment, the material of first graph layer 207 is silicon nitride, forms first graph layer 207
Processing step include：Graphic films are formed on the surface of first medium layer 204；In the graphic films table
Face forms patterned photoresist layer；With the patterned photoresist layer as mask, the figure is etched
Film forms first graph layer 207；Remove the patterned photoresist layer.
In other embodiments, additionally it is possible to formed using Dual graphing method and described have the of the first opening
One graph layer, forming the processing step of first graph layer includes：In the first medium layer surface shape
Into the first mask layer；The second mask layer, and first mask layer are formed in the first mask layer surface
It is different with the material of the second mask layer；The first photoresist layer is formed in the second mask layer surface, it is described
First photoresist layer is projected on the grid that the figure of grid structure top surface is at least covered between adjacent interconnection area
The whole top surface of pole structure, the region projection between adjacent first photoresist layer is in the figure of substrate surface
For the first projecting figure, first projecting figure cover interconnecting area and it is adjacent with the interconnecting area every
Absciss layer；With first photoresist layer as mask, etch second mask layer and cover until exposing first
Film surface；Remove first photoresist layer；The second mask layer surface and expose after etching
First mask layer surface forms the second photoresist layer, and second photoresist layer is projected on the figure of substrate surface
Shape is the second projecting figure, and per one second projecting figure, correspondence is located in one first projecting figure, and described
Second projecting figure covers separation layer；With second photoresist layer as mask, expose described in etching
First mask layer forms first in first mask layer and is open up to first medium layer surface is exposed,
The first mask layer after the etching is used as the first graph layer；Remove second photoresist layer.
In other embodiments, the material of first graph layer can also be Other substrate materials.
It is the schematic diagram on the basis of Fig. 6 with reference to Fig. 8 and Fig. 9, Fig. 8, Fig. 9 is on the basis of Fig. 7
Schematic diagram, first medium layer 204 of the etching above interconnecting area I, until exposing area surface or leakage
Area surface, forms through hole 218 above interconnecting area I.
Specifically, with first graph layer 207 (referring to Fig. 6 and Fig. 7) as mask, along described first
First medium layer 204 of the etching of opening 208 above interconnecting area I, forms the through hole 218.Using
Dry etch process etches the first medium layer 204, and the etching gas of dry etch process include CF4
Or CHF3。
The quantity of the through hole 218 is identical with the quantity of interconnecting area I, and each through hole 218 is across each mutual
Whole source regions even in area I or whole drain regions, so that the interconnection layer being subsequently formed is by each interconnecting area I
Interior whole source regions or whole drain regions are electrically connected.
In the present embodiment, the through hole 218 is only through the thickness of first medium layer 204.With prior art
Compare, the depth that the through hole 218 of formation is etched in the present embodiment is more shallow, so that shape in the present embodiment
Technology difficulty into through hole 218 reduces, and improves the pattern of the through hole 218 to be formed, and improves through hole 218
Position precision and pattern accuracy, and then cause the interconnection layer that is subsequently formed that there is higher position essence
Exactness and pattern accuracy, improve the reliability of electrical connection of the semiconductor devices for being formed.
And in prior art, source region or drain region surface are formed with level 0 conductive layer, and grid structure top
Surface is formed with level 0 grid conductive layer, it is contemplated that level 0 conductive layer top and level 0 grid conductive layer
Top flushes or differs less, needs to form second dielectric layer in first medium layer surface so that second is situated between
Matter layer top is higher than grid structure top, so as to form what is electrically connected with grid structure in second dielectric layer
Level 0 grid conductive layer, accordingly, forms the through hole needed for the level 0 conductive layer and runs through first medium
Thickness degree and second dielectric layer thickness, due to the depth of through hole it is deeper so that the position of the through hole of formation and
Easily there is deviation in pattern, especially when the size of semiconductor devices is less and less, it is also possible to cause through hole
The problem in some source regions or drain region in interconnecting area is not exposed.
With reference to figures 10 to Figure 12, Figure 10 is top view, and Figure 11 is profiles of the Figure 10 along YY1 directions,
Figure 12 is profiles of the Figure 10 along ZZ1 directions, formed the full through hole 218 of filling (with reference to Fig. 8 and
Interconnection layer 228 Fig. 9).
The material of the interconnection layer 228 is one or more in copper, aluminium, tungsten, gold, silver or titanium.This
In embodiment, the material of the interconnection layer 228 is tungsten.
Forming the processing step of the interconnection layer 228 includes：Form the interconnection of the full through hole 218 of filling
Film, the interconnection film top is higher than the top of first medium layer 204；Removal is pushed up higher than first medium layer 204
The interconnection film in portion, forms the interconnection layer 228.
The interconnection layer 228 is located at interconnecting area I top, and the interconnection layer 228 is located at area surface or drain region
Surface.The quantity of the interconnection layer 228 is identical with the quantity of interconnecting area I, and interconnection layer 228 is across each
Whole source regions or whole drain regions in interconnecting area I, so that the whole source regions or all leakages in interconnecting area I
Area electrical connection is realized by interconnection layer 228.
From Such analysis, the interconnection layer 228 formed in the present embodiment has higher position precision
With pattern accuracy so that the electrical connection properties reliability between whole source regions or whole drain regions in interconnecting area I
Property is improved.
It is the schematic diagram on the basis of Figure 11 with reference to Figure 13 and Figure 14, Figure 13, Figure 14 is basic in Figure 12
Upper schematic diagram, in the top surface of the interconnection layer 228 and the top surface of first medium layer 204 the is formed
Second medium layer 301.
In the present embodiment, the second dielectric layer 301 is to be subsequently formed level 0 conductive layer and level 0
Grid conductive layer provides Process ba- sis, and protects the level 0 conductive layer being subsequently formed and level 0 grid conductive
Layer.
The material of the second dielectric layer 301 is silica, silicon nitride, silicon oxynitride or carbon silicon oxynitride；
The second dielectric layer is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process
301.In the present embodiment, the material of the second dielectric layer 301 is silica.
It is the schematic diagram on the basis of Figure 13 with reference to Figure 15 and Figure 16, Figure 15, Figure 16 is basic in Figure 14
Upper schematic diagram, second figure with the second opening 303 is formed in the top surface of the second dielectric layer 301
Shape layer 302, second opening, 303 bottom-exposeds go out the top surface of interconnection layer 228.
The material of the second graph layer 302 be silica, silicon nitride, silicon oxynitride, carbon silicon oxynitride,
Titanium nitride or tantalum nitride.The material of the second graph layer 302 is different from the material of second dielectric layer 301,
In the present embodiment, the material of the second graph layer 302 is silicon nitride.
In the present embodiment, second opening, 303 bottom-exposeds go out the atop part surface of interconnection layer 228,
Just can pass through interconnection layer 228 make whole source regions in the level 0 conductive layer that is subsequently formed and interconnecting area I or
Whole drain region electrical connections, 303 bottoms of the second opening can also expose the part of first medium layer 204
Top surface.In other embodiments, second open bottom exposes interconnection layer whole top surface.
Second opening 303 is without the need for the whole source regions in each interconnecting area I or whole drain regions.Therefore,
In the present embodiment, the position of second opening 303 and the scope of design of pattern are wider, so that institute
The formation process flexibility for stating the second graph layer 302 with the second opening 303 is high, reduces semiconductor
The technology difficulty of device so that the layout of the second opening 303 is more flexible such that it is able to make semiconductor device
The layout design of part more optimizes.
In a specific embodiment, the second graph layer 302 with the second opening 303 is formed
Processing step includes：Initial graphics layer is formed on the surface of the second dielectric layer 301；In the initial graph
Shape layer surface forms patterned photoresist layer；With the patterned photoresist layer as mask, institute is etched
State initial graphics layer to be formed in the second graph layer 302, the second graph layer 302 with the second opening
303。
In other embodiments, the material of the second graph layer is Other substrate materials.
With reference to Figure 17, Figure 17 is the schematic diagram on the basis of Figure 16, with the second graph layer 302 (ginseng
Examine Figure 16) it is mask, along the second opening 303 (referring to Figure 16) etching second dielectric layer 301, until
The top surface of interconnection layer 228 is exposed, groove 313 is formed in the second dielectric layer 301.
The groove 313 exposes the top surface of interconnection layer 228.In the present embodiment, the groove 313
The atop part surface of interconnection layer 228 is exposed, the atop part surface of first medium layer 204 is also exposed.
In other embodiments, the groove only exposes interconnection layer portions top surface；Or, the groove
Expose interconnection layer whole top surface.
Using dry etch process, the second dielectric layer 301 is etched.After the groove 313 is formed,
Remove the second graph layer 302.
Referring to figs. 18 to Figure 19, Figure 18 is top view, and Figure 19 is profiles of the Figure 18 along ZZ1 directions,
Level 0 conductive layer 323 is formed in the top surface of the interconnection layer 228.
Specifically, in the present embodiment, the level 0 of the full groove 313 (referring to Figure 17) of filling is formed
Conductive layer 323.The material of the level 0 conductive layer 323 is in copper, aluminium, tungsten, gold, silver or titanium
Plant or various.In the present embodiment, the material of the level 0 conductive layer 323 is tungsten.
Each level 0 conductive layer 323 is electrically connected with the whole source regions in interconnecting area I or whole drain regions.Institute
State level 0 conductive layer 323 and there is contact surface with interconnection layer 228, i.e., can be caused by interconnection layer 228
Level 0 conductive layer 323 leads the whole source regions in interconnecting area I or whole drain region electrical connections, the level 0
The position of electric layer 323 and the scope of design width of pattern, so as to improve semiconductor device technology flexibility.
In the present embodiment, the level 0 conductive layer 323 is located at the atop part surface of interconnection layer 228, institute
State level 0 conductive layer 323 and be also located at the atop part surface of first medium layer 204.In other embodiments,
The level 0 conductive layer is located at interconnection layer whole top surface.
In other embodiments, can be so that before second dielectric layer is formed, the formation level 0 be conductive
Layer.Forming the processing step of the level 0 conductive layer includes：In the interconnection layer top surface and
First medium layer top surface forms conducting film；The graphical conducting film, forms the level 0 conductive
Layer, the level 0 conductive layer is located at interconnection layer portions top surface, or, the level 0 conductive layer
Positioned at interconnection layer whole top surface.
Also include step：The level 0 grid that formation is electrically connected with the conductive grid 213 in grid structure are conductive
Flush with level 0 conductive layer 323 at the top of layer, and the level 0 grid conductive layer.Wherein, the described 0th
The region that layer grid conductive layer is located is separate with interconnecting area I.Specifically, etching is located at grid structure top
Second dielectric layer 301, form groove in the second dielectric layer 301 above the grid structure, and also
Etching removes the hard mask layer 206 below the groove, wherein, the groove and level 0 conductive layer 323
It is separate；Form the level 0 grid conductive layer of the full groove of filling.
The embodiment of the present invention also provides a kind of semiconductor structure, with reference to Figure 13, Figure 18 and Figure 19, Figure 18
For top view, Figure 19 is profiles of the Figure 18 along ZZ1 directions, and Figure 13 is Figure 18 along YY1 directions
Profile, the semiconductor structure includes：
Substrate, the substrate surface is formed with grid structure, and the grid structure both sides have respectively one
Interconnecting area I, is respectively formed with the source region positioned at grid structure both sides and drain region in the substrate of interconnecting area I,
Wherein, each interconnecting area I is across several source regions or several drain regions；
Positioned at the first medium layer 204 on the substrate surface and grid structure surface；
Through hole in first medium layer 204 above interconnecting area I, the through hole exposes source region table
Face or drain region surface, and whole source regions or whole drain region of each through hole in each interconnecting area I；
The interconnection layer 228 of the full through hole of filling；
Positioned at the level 0 conductive layer 323 of the top surface of the interconnection layer 228.
The semiconductor structure that the present embodiment is provided will be described in detail below.
The substrate includes：Substrate 201；Positioned at some discrete fin 202 on the surface of substrate 201；Position
In the separation layer 203 on the surface of the substrate 201, the separation layer 203 covers the partial sidewall of fin 202
Surface, and the top of the separation layer 20 is less than the top of fin 202；Wherein, the grid structure is across institute
Fin 202 is stated, and the grid structure is located at the side wall of the surface of part separation layer 203 and fin 202
And top surface, the source region and drain region are respectively in the fin 202 of the grid structure both sides.
In the present embodiment, the quantity of the fin 202 is more than 1, and some fins are arranged in parallel, the grid
Pole structure is across at least one fin 202；The quantity of the grid structure is more than 1, and some grid structures
It is arranged in parallel, each grid structure across multiple fins 202, wherein, each interconnecting area I is across same grid
Source region or drain region in the corresponding multiple fins 202 of pole structure.
The grid structure includes：Gate dielectric layer 211, positioned at the work-function layer on the surface of gate dielectric layer 211
212 and positioned at the conductive grid 213 on the surface of work-function layer 212.The interconnection layer 228 is across each
Whole source regions or whole drain regions in interconnecting area I, so that the whole source regions or all leakages in interconnecting area I
Area is electrically connected by interconnection layer 228, the whole in interconnecting area I of each level 0 conductive layer 323 and
Source region or whole drain region electrical connections.In the present embodiment, the level 0 conductive layer 323 is located at interconnection layer 228
Atop part surface, the level 0 conductive layer 323 is also located at the atop part surface of first medium layer 204.
In other embodiments, the level 0 conductive layer can also be located at interconnection layer whole top surface.
Because the whole source regions in interconnecting area I or whole drain regions are electrically connected by interconnection layer 228, therefore
The level 0 conductive layer 323 only needs to be contacted with interconnection layer 228, it becomes possible to make level 0 conductive layer 323
Electrically connect with the whole source regions in interconnecting area I or whole drain regions, therefore the semiconductor device provided in the present embodiment
In part, the position of level 0 conductive layer 323 and pattern have wider range of choice, by rationally setting
The position of level 0 conductive layer 323 and pattern, can improve the layout design of semiconductor devices, and cause
Semiconductor devices has higher electric property and reliability.
The semiconductor devices also includes：Positioned at the second dielectric layer 301 of the top surface of first medium layer 204,
The second dielectric layer 301 covers the sidewall surfaces of level 0 conductive layer 323.Also include：With the grid
The level 0 grid conductive layer of the electrical connection of conductive grid 213 in structure, and level 0 grid conductive layer top
Flush with level 0 conductive layer, and the level 0 grid conductive layer region is separate with interconnecting area I.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of semiconductor devices, it is characterised in that include：
Substrate is provided, the substrate surface is formed with grid structure, and the grid structure both sides have respectively
One interconnecting area, is respectively formed with the source region positioned at grid structure both sides and leakage in the substrate of the interconnecting area
Area, wherein, each interconnecting area is across several source regions or several drain regions；
First medium layer is formed in the substrate surface and grid structure surface；
First medium layer of the etching above interconnecting area, until area surface or drain region surface are exposed,
Through hole, and whole source regions or whole of each through hole in an interconnecting area are formed above the interconnecting area
Drain region；
Form the interconnection layer of the full through hole of filling；
Level 0 conductive layer is formed in the interconnection layer top surface.
2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the level 0 is conductive
Layer is located at interconnection layer portions top surface.
3. the forming method of semiconductor devices as claimed in claim 1 or 2, it is characterised in that the level 0
Conductive layer is also located at first medium layer segment top surface.
4. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the first medium layer
Top is with grid structure top flush or below grid structure top.
5. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that form the through hole
Processing step includes：First graph layer with the first opening is formed in the first medium layer surface,
First opening is located at interconnecting area top, and the whole source regions in each interconnecting area or all leakages
Area；With first graph layer as mask, along the described first opening etching above the interconnecting area the
One dielectric layer, forms the through hole；Remove first graph layer.
6. the forming method of semiconductor devices as claimed in claim 5, it is characterised in that form first figure
The processing step of shape layer includes：The first mask layer is formed in the first medium layer surface；Described
One mask layer surface forms the second mask layer, and the material of first mask layer and the second mask layer is not
Together；The first photoresist layer is formed in the second mask layer surface, first photoresist layer is projected on
The figure of grid structure top surface at least covers the whole top table of grid structure between adjacent interconnection area
Face, the region projection between adjacent first photoresist layer is the first projecting figure in the figure of substrate surface,
First projecting figure covers interconnecting area and the separation layer adjacent with the interconnecting area；With described
One photoresist layer is mask, etches second mask layer until exposing the first mask layer surface；Go
Except first photoresist layer；Second mask layer surface and the first mask layer for exposing after etching
Surface forms the second photoresist layer, and it is second that second photoresist layer is projected on the figure of substrate surface
Projecting figure, the second projecting figure correspondence is located in the first projecting figure, and second projecting figure
Cover separation layer；With second photoresist layer as mask, the first mask layer exposed described in etching
Until exposing first medium layer surface, first is formed in first mask layer and is open, the quarter
The first mask layer after erosion is used as the first graph layer；Remove second photoresist layer.
7. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that form the level 0
The processing step of conductive layer includes：The table at the top of the interconnection layer top surface and first medium layer
Face forms conducting film；The graphical conducting film, forms the level 0 conductive layer.
8. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that form the level 0
The processing step of conductive layer includes：In the interconnection layer top surface and first medium layer top surface
Form second dielectric layer；Second figure with the second opening is formed in the second dielectric layer top surface
Shape layer, second open bottom exposes interconnection layer portions top surface；With the second graph layer
For mask, the second dielectric layer is etched along the second opening, until interconnection layer top surface is exposed,
Groove is formed in the second dielectric layer；Form the level 0 conductive layer of the full groove of filling；Go
Except the second graph layer.
9. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the material of the interconnection layer
Expect for one or more in copper, aluminium, tungsten, gold, silver or titanium；The material of the level 0 conductive layer
For one or more in copper, aluminium, tungsten, gold, silver or titanium.
10. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that each grid structure two
Side is respectively formed with multiple source regions or multiple drain regions, and each interconnecting area is across the plurality of source region or multiple
Drain region.
The forming method of 11. semiconductor devices as claimed in claim 1, it is characterised in that the substrate includes：
Substrate；Positioned at some discrete fin of substrate surface；Positioned at the separation layer of the substrate surface, institute
The partial sidewall surface that separation layer covers fin, and separation layer top are stated less than fin top；Its
In, the grid structure across the fin, and the grid structure be located at part insulation surface,
And the side wall and top surface of fin, the source region and drain region are located at respectively the grid structure both sides
Fin in.
The forming method of 12. semiconductor devices as claimed in claim 11, it is characterised in that the quantity of the fin
More than 1, and some fins are arranged in parallel, and the grid structure is across at least one fin；The grid
The quantity of pole structure is more than 1, and some grid structures are arranged in parallel, and each grid structure is across multiple
Fin.
The forming method of 13. semiconductor devices as claimed in claim 12, it is characterised in that each interconnecting area across
Source region or drain region in the corresponding multiple fins of same grid structure.
The forming method of 14. semiconductor devices as claimed in claim 1, it is characterised in that also including step：Shape
Lead into the level 0 grid conductive layer electrically connected with the conductive grid in grid structure, and the level 0 grid
Electric layer top flushes with level 0 conductive layer.
15. a kind of semiconductor devices, it is characterised in that include：
Substrate, the substrate surface is formed with grid structure, and the grid structure both sides have respectively one
Interconnecting area, is respectively formed with the source region positioned at grid structure both sides and drain region in the substrate of the interconnecting area,
Wherein, each interconnecting area is across several source regions or several drain regions；
Positioned at the first medium layer on the substrate surface and grid structure surface；
Positioned at the interconnecting area top first medium layer in through hole, the through hole expose area surface or
Drain region surface, and whole source regions or whole drain region of each through hole in each interconnecting area；
The interconnection layer of the full through hole of filling, whole source regions of the interconnection layer I in each interconnecting area I
Or whole drain regions；
Positioned at the level 0 conductive layer of the interconnection layer top surface.
16. semiconductor devices as claimed in claim 15, it is characterised in that the level 0 conductive layer is located at interconnection
Layer segment top surface.
17. as described in claim 15 or 16 semiconductor devices, it is characterised in that the level 0 conductive layer is also
Positioned at first medium layer segment top surface.
18. semiconductor devices as claimed in claim 15, it is characterised in that the substrate includes：Substrate；It is located at
The some discrete fin of substrate surface；Positioned at the separation layer of the substrate surface, the separation layer covers
The partial sidewall surface of lid fin, and separation layer top is less than fin top；Wherein, the grid
Pole structure is across the fin, and the grid structure is located at part insulation surface and fin
Side wall and top surface, the source region and drain region are respectively in the fin of the grid structure both sides.
19. semiconductor devices as claimed in claim 18, it is characterised in that the quantity of the fin be more than 1, and
Some fins are arranged in parallel, and the grid structure is across at least one fin；The number of the grid structure
Amount is more than 1, and some grid structures are arranged in parallel, each grid structure across multiple fins, wherein,
Source region or drain region of each interconnecting area in the corresponding multiple fins of same grid structure.
20. semiconductor devices as claimed in claim 15, it is characterised in that also include：In the grid structure
The level 0 grid conductive layer of conductive grid electrical connection, and level 0 grid conductive layer top and level 0
Conductive layer is flushed.
Priority Applications (1)
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| CN112992822A (en) * | 2019-12-17 | 2021-06-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113496993A (en) * | 2020-04-01 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and method for forming semiconductor structure |
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| CN102187453A (en) * | 2008-09-30 | 2011-09-14 | 先进微装置公司 | Contacts and vias of a semiconductor device formed by a hardmask and double exposure |
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