CN106611712B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN106611712B
CN106611712B CN201510706331.1A CN201510706331A CN106611712B CN 106611712 B CN106611712 B CN 106611712B CN 201510706331 A CN201510706331 A CN 201510706331A CN 106611712 B CN106611712 B CN 106611712B
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source
layer
drain
forming
groove
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CN106611712A (en
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余云初
沈忆华
潘见
傅丰华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method of the semiconductor structure comprises the following steps: forming dielectric layers on the top surface and the side wall surface of the grid structure and the surface of the substrate; etching the dielectric layer above the source-drain interconnection region to form a first groove above the source-drain interconnection region, and simultaneously etching the dielectric layer above the bridging region to form a second groove above the bridging region; forming a zero conducting layer which is filled in the first groove, and simultaneously forming a bridging conducting layer which is filled in the second groove, wherein the zero conducting layer is electrically connected with the source drain electrode in the source drain interconnection region; etching the dielectric layer above the grid interconnection region, and forming a third groove above the grid interconnection region in the dielectric layer, wherein the third groove exposes the surface of the grid structure of the grid interconnection region; and forming a zero gate conducting layer which is filled in the third groove, wherein the adjacent zero gate conducting layer is contacted with the side wall of the bridging conducting layer. The invention improves the electrical performance of the formed semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
The metal interconnection structure is an indispensable structure in a semiconductor device, and is used for realizing interconnection between an active region and an active region, interconnection between a transistor and a transistor, or interconnection between metal wires of different layers to complete signal transmission and control. Therefore, in a semiconductor manufacturing process, the formation of a metal interconnection structure has a great influence on the performance of a semiconductor device and the manufacturing cost of the semiconductor device. In order to increase the density of devices, the size of semiconductor devices in integrated circuits has been continuously reduced, and in order to achieve electrical connection of the respective semiconductor devices, a multi-layer interconnection structure is generally required.
Therefore, before the first metal layer is formed, a local interconnection structure (L cal Interconnect) of the semiconductor device is generally required to be formed in advance, wherein the local interconnection structure comprises a zeroth metal layer (M0) electrically connected with the lower source and drain regions and a zeroth gate metal layer (M0G) electrically connected with the gate structure.
However, the manufacturing process of the semiconductor structure having the local interconnect structure in the prior art is complicated, and the performance of the formed semiconductor structure is to be further improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can simplify the process steps and improve the electrical property of the formed semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein discrete gate structures are formed on the surface of the substrate, and source and drain electrodes are formed in the substrate on two sides of the gate structures, wherein the substrate is provided with gate interconnection regions and bridging regions positioned between adjacent gate interconnection regions, the gate interconnection regions and the bridging regions respectively correspond to different gate structures, the substrate is also provided with source and drain interconnection regions corresponding to the source and drain electrodes, the source and drain interconnection regions cross a plurality of source and drain electrodes, and the gate interconnection regions, the bridging regions and the source and drain interconnection regions are mutually independent; forming dielectric layers on the top surface and the side wall surface of the grid structure and the surface of the substrate; etching a dielectric layer positioned above a source-drain interconnection region, forming a first groove positioned above the source-drain interconnection region in the dielectric layer, simultaneously etching the dielectric layer positioned above a bridging region, and forming a second groove positioned above the bridging region in the dielectric layer, wherein a projection pattern of the second groove projected on the surface of a substrate at least fully covers the bridging region; forming a zero conducting layer which is filled in the first groove, and simultaneously forming a bridging conducting layer which is filled in the second groove, wherein the zero conducting layer is electrically connected with a source drain electrode in a source drain interconnection region; etching the dielectric layer above the grid interconnection region, and forming a third groove above the grid interconnection region in the dielectric layer, wherein the third groove exposes the surface of the grid structure of the grid interconnection region, and the surface of the side wall of the bridging conductive layer is also exposed by the third groove; and forming a zero gate conducting layer which is filled in the third groove, wherein the adjacent zero gate conducting layer is contacted with the side wall of the bridging conducting layer.
Optionally, the dielectric layer includes an interlayer dielectric layer and an upper dielectric layer located on the surface of the interlayer dielectric layer, wherein the interlayer dielectric layer covers the top surface and the sidewall surface of the gate structure and the surface of the substrate, the first groove penetrates through the upper dielectric layer, and the second groove penetrates through the upper dielectric layer.
Optionally, before the first groove and the second groove are formed, a source-drain conductive layer is formed in the interlayer dielectric layer above the source-drain interconnection region, the source-drain conductive layer is located on the surface of the source-drain electrode, and the source-drain conductive layer crosses the source-drain electrode in the source-drain interconnection region.
Optionally, before the first groove and the second groove are formed, a source-drain conductive layer is formed in the interlayer dielectric layer above the source-drain interconnection region, the source-drain conductive layer is located on the surface of the source-drain electrode, and the source-drain conductive layer crosses the source-drain electrode in the source-drain interconnection region.
Optionally, the process for forming the dielectric layer and the source-drain conductive layer includes: forming interlayer dielectric layers on the top surface and the side wall surface of the grid structure and the surface of the substrate; etching an interlayer dielectric layer positioned above a source-drain interconnection region, and forming a groove exposing the surface of a source-drain electrode in the interlayer dielectric layer, wherein the groove crosses the surface of the source-drain electrode in the source-drain interconnection region; forming a source drain conductive layer which is filled in the groove; and forming an upper dielectric layer on the surface of the source drain conductive layer and the surface of the interlayer dielectric layer.
Optionally, the process step of forming the trench includes: forming a third mask layer on the surface of the interlayer dielectric layer, wherein a fourth opening is formed in the third mask layer, and the fourth opening pattern crosses the source and drain electrodes in the source and drain interconnection region; and etching the interlayer dielectric layer along the fourth opening by taking the third mask layer as a mask until the surface of the source drain electrode is exposed, thereby forming the groove.
Optionally, the conductive layer of the zero layer and the bridging conductive layer are formed first, and then the conductive layer of the zero layer is formed, wherein the third groove exposes the sidewall surface of the adjacent bridging conductive layer.
Optionally, the process step of forming the first groove and the second groove includes: forming a first mask layer on the surface of the dielectric layer, wherein the first mask layer is internally provided with a first opening positioned above a source-drain interconnection region, the first mask layer is also internally provided with a second opening positioned above a bridging region, and a projection pattern of the second opening projected on the surface of the substrate at least fully covers the bridging region; taking the first mask layer as a mask, etching the dielectric layer along the first opening to form the first groove, and simultaneously etching the dielectric layer along the second opening to form the second groove; and removing the first mask layer.
Optionally, the process step of forming the third groove includes: forming a second mask layer with a third opening on the surface of the dielectric layer, wherein the third opening is positioned above the grid interconnection region, and the bottom of the third opening exposes partial surfaces of the adjacent bridging conductive layers; etching the dielectric layer along the third opening by taking the second mask layer as a mask to form a third groove; and removing the second mask layer.
Optionally, the zero gate conductive layer is formed first, and then the zero conductive layer and the bridging conductive layer are formed.
The present invention also provides a semiconductor structure comprising: the semiconductor device comprises a substrate, wherein discrete gate structures are formed on the surface of the substrate, and source and drain electrodes are formed in the substrate on two sides of the gate structures, wherein the substrate is provided with gate interconnection regions and bridging regions positioned between adjacent gate interconnection regions, the gate interconnection regions and the bridging regions respectively correspond to different gate structures, the substrate is also provided with source and drain interconnection regions corresponding to the source and drain electrodes, the source and drain interconnection regions cross a plurality of source and drain electrodes, and the gate interconnection regions, the bridging regions and the source and drain interconnection regions are mutually independent; the dielectric layers are positioned on the top surface and the side wall surface of the grid structure and the surface of the substrate; the first groove is positioned in the medium layer and is positioned above the source-drain interconnection region; the second groove is positioned above the bridging area, and the pattern of the second groove projected on the surface of the substrate at least fully covers the bridging area; the zero conducting layer is filled in the first groove; the bridging conductive layer is filled in the second groove; a third groove in the dielectric layer, the third groove being above the gate interconnection region, the third groove exposing the gate structure surface of the gate interconnection region, the third groove also exposing the bridging conductive layer sidewall surface; and the zero gate conducting layer of the third groove is filled, and the adjacent zero gate conducting layer is contacted with the side wall of the bridging conducting layer.
Optionally, the dielectric layer includes an interlayer dielectric layer and an upper dielectric layer located on the surface of the interlayer dielectric layer, wherein the interlayer dielectric layer covers the top surface and the sidewall surface of the gate structure and the surface of the substrate, the first groove penetrates through the upper dielectric layer, and the second groove penetrates through the upper dielectric layer.
Optionally, an active drain conductive layer is formed in the interlayer dielectric layer above the source-drain interconnection region, the source-drain conductive layer is located on the surface of the source-drain electrode, and the source-drain conductive layer crosses the source-drain electrode in the source-drain interconnection region.
Optionally, the first groove exposes a part of or all of the top surface of the source-drain conductive layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme of the forming method of the semiconductor structure, a first groove is formed in a dielectric layer above a source-drain interconnection region, and a second groove is formed in the dielectric layer above a bridging region, wherein the bridging region is located between adjacent grid interconnection regions, and a projection pattern of the second groove projected on the surface of a substrate is at least paved in the bridging region; forming a zero conducting layer which is filled in the first groove, and simultaneously forming a bridging conducting layer which is filled in the second groove, wherein the zero conducting layer is electrically connected with a source drain electrode in the source drain interconnection region; etching the dielectric layer above the grid interconnection region, and forming a third groove above the grid interconnection region in the dielectric layer, wherein the third groove exposes the surface of the grid structure of the grid interconnection region, and the surface of the side wall of the bridging conductive layer is also exposed by the third groove; and forming a zero gate conducting layer which is filled in the third groove, wherein the adjacent zero gate conducting layers are contacted with the side wall of the bridging conducting layer, so that the adjacent zero gate conducting layers are electrically connected through the bridging conducting layer, and no additional process step is required for realizing the electrical connection between the zero gate conducting layers, thereby simplifying the process steps. In addition, the electric signal transmission path between adjacent zero gate conductive layers is short, so that the time for transmitting the electric signal is short, the external interference of the electric signal is reduced, the reliability of electric signal transmission is improved, and the electric performance of the formed semiconductor structure is improved.
Furthermore, before the first groove and the second groove are formed, a source-drain conducting layer is formed in the interlayer dielectric layer above the source-drain interconnection region, the source-drain conducting layer is located on the surface of the source-drain electrode, and the source-drain conducting layer stretches across the source-drain electrode in the source-drain interconnection region, so that a subsequently formed zeroth conducting layer does not need to stretch across the source-drain electrode of the source-drain interconnection region, and the zeroth conducting layer is in contact with the source-drain conducting layer, so that the process difficulty of forming the zeroth conducting layer is reduced, the requirements on position accuracy and appearance accuracy of the zeroth conducting layer are lowered, and the process flexibility is improved.
The present invention also provides a semiconductor structure with superior structural performance, comprising: the dielectric layers are positioned on the top surface and the side wall surface of the grid structure and the surface of the substrate; the first groove is positioned in the medium layer and is positioned above the source-drain interconnection region; the second groove is positioned above the bridging area, and the pattern of the second groove projected on the surface of the substrate at least fully covers the bridging area; the zero conducting layer is filled in the first groove; the bridging conductive layer is filled in the second groove; a third groove in the dielectric layer, the third groove being above the gate interconnection region, the third groove exposing the gate structure surface of the gate interconnection region, the third groove also exposing the bridging conductive layer sidewall surface; the third groove is filled with the zero gate conducting layer, and the adjacent zero gate conducting layers are in contact with the side wall of the bridging conducting layer, so that the transmission path of the electric signals between the adjacent zero gate conducting layers is short, the interference of the external environment on the signals is reduced, the accuracy of the transmitted electric signals is high, the time required for transmitting the electric signals is short, and the semiconductor structure has excellent electrical performance.
Drawings
Fig. 1 to 2 are schematic views of semiconductor structures provided in the prior art.
Fig. 3 to 18 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
According to the background art, the manufacturing process of the semiconductor structure with the local interconnection structure in the prior art is complex, and the performance of the formed semiconductor structure needs to be further improved.
Referring to fig. 1 and 2, fig. 1 is a schematic perspective view of a semiconductor structure, and fig. 2 is a partial top view of the semiconductor structure, the semiconductor structure including: a substrate (not shown); a plurality of discrete fin portions 11 located on the surface of the substrate; the gate structure 12 crosses the fin 11, and the gate structure 12 covers part of the top surface and the sidewall surface of the fin 11; source and drain regions (not labeled) in the fin portion 11 located at two sides of the gate structure 12; a dielectric layer 13 covering the surface of the gate structure 12 and the surface of the source drain region; a zero Metal layer (M0, Metal 0)14 electrically connected to the source/drain region, where the zero Metal layer 14 includes a lower Metal layer located on the surface of the source/drain region and an upper Metal layer located on the top surface of the lower Metal layer, and the lower Metal layer is located in the dielectric layer 13, and a width dimension of the upper Metal layer is greater than a width dimension of the lower Metal layer in an extending direction along the fin portion 11; a zero Gate Metal layer (M0G, Metal 0Gate)15 electrically connected to the Gate structure 12; a plurality of discrete connection layers 17, wherein part of the connection layers 17 are positioned on the surface of the zero-level metal layer 14, and part of the connection layers 17 are positioned on the surface of the zero-level gate metal layer 15; and a plurality of discrete first-layer Metal layers (M1, Metal 1)16 located on the surface of the connecting layer 17, wherein part of the first-layer Metal layers 16 are electrically connected with the zero-layer Metal layer 14 through the connecting layer 17, and part of the first-layer Metal layers 16 are electrically connected with the zero-layer gate Metal layer 15 through the connecting layer 17.
Different zero gate metal layers 15 are electrically connected through the first metal layer 16, so that the zero gate metal layer 15 is electrically connected with other devices or structures, and the first metal layer 16 and the zero gate metal layer 15 are electrically connected through the connecting layer 17, so that the propagation path of an electric signal is long, and the reliability of the electrical performance of the semiconductor structure is poor. Further, since the first metal layer 16 is formed to electrically connect the different zero-level gate metal layers 15, the first metal layer 16 electrically connected to the zero-level metal layer 14 needs to be formed in order to electrically connect the zero-level metal layer 14 to another device or structure, which complicates the process of forming the semiconductor structure.
The invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, forming a discrete grid structure on the surface of the substrate, and forming a source drain in the substrate on two sides of the grid structure, wherein the substrate is provided with a grid interconnection region and a bridging region positioned between adjacent grid interconnection regions, the grid interconnection region and the bridging region respectively correspond to different grid structures, the substrate is also provided with a source drain interconnection region corresponding to a source drain, the source drain interconnection region spans a plurality of source drains, and the grid interconnection region, the bridging region and the source drain interconnection region are mutually independent; forming dielectric layers on the top surface and the side wall surface of the grid structure and the surface of the substrate; etching a dielectric layer positioned above a source-drain interconnection region, forming a first groove positioned above the source-drain interconnection region in the dielectric layer, simultaneously etching the dielectric layer positioned above a bridging region, and forming a second groove positioned above the bridging region in the dielectric layer, wherein a projection pattern of the second groove projected on the surface of a substrate at least fully covers the bridging region; forming a zero conducting layer which is filled in the first groove, and simultaneously forming a bridging conducting layer which is filled in the second groove, wherein the zero conducting layer is electrically connected with a source drain electrode in a source drain interconnection region; etching the dielectric layer above the grid interconnection region, and forming a third groove above the grid interconnection region in the dielectric layer, wherein the third groove exposes the surface of the grid structure of the grid interconnection region, and the surface of the side wall of the bridging conductive layer is also exposed by the third groove; and forming a zero gate conducting layer which is filled in the third groove, wherein the adjacent zero gate conducting layer is contacted with the side wall of the bridging conducting layer.
According to the invention, the first conductive layer electrically connecting the adjacent zero gate conductive layers is not required to be additionally formed, and the adjacent zero gate conductive layers are electrically connected through the bridging conductive layer positioned between the adjacent zero gate conductive layers, so that the process steps are simplified, the electric signal transmission path between the adjacent zero gate conductive layers is shortened, and the electrical property of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 18 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 3 to 5, fig. 3 is a top view, fig. 4 is a schematic cross-sectional view taken along a direction YY1 in fig. 3, fig. 5 is a schematic cross-sectional view taken along a direction ZZ1 in fig. 3, a substrate is provided, a discrete gate structure is formed on the surface of the substrate, and an active drain (not shown) is formed in the substrate on both sides of the gate structure.
The substrate is provided with a grid interconnection region I and a bridging region II positioned between adjacent grid interconnection regions I, the grid interconnection region I and the bridging region II correspond to different grid structures respectively, the substrate is further provided with a source-drain interconnection region III corresponding to a source-drain electrode, the source-drain interconnection region III spans a plurality of source-drain electrodes, and the grid interconnection region I, the bridging region II and the source-drain interconnection region III are independent of one another. In this embodiment, the YY1 direction is perpendicular to the gate structure arrangement direction, the ZZ1 direction is perpendicular to the gate structure arrangement direction, the source-drain interconnection region III is cut along the YY1 direction, and the gate interconnection region I and the bridging region II located between adjacent gate interconnection regions I are cut along the ZZ1 direction.
The source-drain interconnection regions III are located on two sides of the grid structure and cross the source-drain electrodes in the active regions. The size of the gate interconnection region I is larger than or equal to the size of the gate structure in the arrangement direction of the gate structure, so that a subsequently formed zero-th gate conductive layer is in contact with the whole top surface of the gate structure. The grid interconnection region I is provided with a grid structure, the bridging region II is provided with a grid structure, a zero-level grid conducting layer electrically connected with the corresponding grid structure is formed above the grid interconnection region I subsequently, and the zero-level grid conducting layer is electrically insulated from the grid structure of the bridging region II. In this embodiment, 2 gate interconnection regions I and 1 bridging region II are taken as an example, and in other embodiments, the number of the gate interconnection regions and the number of the bridging regions may be determined according to actual process requirements.
In this embodiment, the formed semiconductor device is a fin field effect transistor, and the substrate includes: the structure comprises a substrate 201, a plurality of discrete fins 202 located on the surface of the substrate 201, and an isolation layer 203 located on the surface of the substrate 201, wherein the isolation layer 203 covers part of the sidewall surface of the fins 202, and the top of the isolation layer 203 is lower than the top of the fins 202. The gate structure crosses over the fin 202 and covers part of the top and sidewall surfaces of the fin 202 and part of the surface of the isolation layer 203. In this embodiment, the number of the fin portions 202 is greater than 1, the fin portions 202 are arranged in parallel, and the gate structure crosses over at least one fin portion 202; the number of the gate structures is also greater than 1, the gate structures are arranged in parallel, the arrangement direction of the gate structures is perpendicular to the arrangement direction of the fin portions 202, and each gate structure spans at least one fin portion 202.
In another embodiment, the semiconductor device is a planar transistor, the base is a planar base, the planar base is a silicon substrate, a germanium substrate, a silicon germanium substrate or a silicon carbide substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, a glass substrate or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate, etc.), and the gate structure is formed on the surface of the planar base.
The substrate 201 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 201 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of the fin 202 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; the isolation layer 203 serves as an isolation structure of the semiconductor device and plays a role in electrically isolating the adjacent fins 202, and the isolation layer 203 is made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, in the present embodiment, the substrate 201 is a silicon substrate, the fin 202 is made of silicon, and the isolation layer 203 is made of silicon oxide.
The source and drain electrodes comprise source electrodes or drain electrodes which are respectively positioned in the active region substrates on the two opposite sides of the grid electrode structure. In this embodiment, the source-drain interconnection region III spans the source-drain electrodes in the plurality of fins 202. And a stress layer (not marked) is also formed in the source and drain electrodes, and the material of the stress layer is silicon carbide or silicon germanium. When the stress layer is made of silicon carbide, N-type ions, such as P, As or Sb, are doped in the stress layer; when the stress layer is made of silicon germanium, P-type ions, such as B, Ga or In, are doped In the stress layer.
The gate structure includes: a gate dielectric layer 211, a work function layer 212 on the surface of the gate dielectric layer 211, and a conductive gate 213 on the surface of the work function layer 212. In this embodiment, the gate structure further includes: and a sidewall spacer (not shown) on the sidewall surface of the gate dielectric layer 211, the sidewall surface of the work function layer 212, and the sidewall surface of the conductive gate 213.
The gate dielectric layer 211 is made of a high-k gate dielectric material, and the high-k gate dielectric material is HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3. The work function layer 212 is made of an N-type work function material or a P-type work function material, wherein the N-type work function material is TiAl, TaAlN, TiAlN, MoN, TaCN or AlN, and the P-type work function material is Ta, TiN, TaN, TaSiN or TiSiN. The conductive gate 213 is made of Al, Cu, Ag, Au, Pt, Ni, Ti or W.
In this embodiment, a hard mask layer 206 is further formed on the top surface of the gate structure, and the hard mask layer 206 can protect the conductive gate 213. In this embodiment, the hard mask layer 206 is made of silicon nitride. In other embodiments, the material of the hard mask layer can also be silicon oxynitride or silicon oxycarbonitride.
In other embodiments, the gate structure can also be a dummy gate structure (dummy gate), wherein the gate structure is a single-layer structure or a stacked structure.
With continued reference to fig. 3-5, an interlevel dielectric layer 204 is formed on the top and sidewall surfaces of the gate structure, as well as on the substrate surface.
For convenience of description, only the positional relationship between the fin 202 and the gate structure is shown in fig. 3, and the interlayer dielectric layer 204 is not shown in fig. 3.
In this embodiment, the top of the interlayer dielectric layer 204 is higher than the top of the gate structure. In other embodiments, the top of the interlayer dielectric layer is flush with the top of the gate structure.
The interlayer dielectric layer 204 is made of one or more of silicon oxide, silicon nitride and silicon oxynitride, and the forming process includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In this embodiment, the interlayer dielectric layer 204 is made of silicon oxide, and the forming process includes a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
Referring to fig. 6 to 7, fig. 6 is a top view, and fig. 7 is a schematic cross-sectional structure view of fig. 6 cut along the YY1 direction, and a source/drain conductive layer 207 is formed in the interlayer dielectric layer 204 above the source/drain interconnection region III.
For convenience of illustration, the interlayer dielectric layer 204 is not shown in fig. 6, and the dotted boxes shown in fig. 6 show the active region range spanned by the source-drain interconnection regions III, i.e., the source-drain electrode range spanned by each source-drain interconnection region. In this embodiment, a source-drain interconnection region III spanning the source-drain in the 4 fins is taken as an example.
The source-drain conducting layer 207 is positioned on the surface of the source-drain electrode, and the source-drain conducting layer 207 crosses the source-drain electrode in the source-drain interconnection region III, so that a plurality of source-drain electrodes in the source-drain interconnection region III are electrically connected with each other through the source-drain conducting layer 207, and therefore a subsequently formed zeroth conducting layer only needs to be electrically connected with the source-drain conducting layer 207, the zeroth conducting layer can be electrically connected with the source-drain electrodes in the source-drain interconnection region III, requirements on position accuracy and appearance accuracy of the zeroth conducting layer are reduced, process flexibility is improved, and reliability of a semiconductor structure is improved.
The source-drain conductive layer 207 is made of copper, aluminum, tungsten, silver or gold. In this embodiment, the source-drain conductive layer 207 is made of tungsten.
In one embodiment, the process for forming the source/drain conductive layer 207 includes: etching the interlayer dielectric layer 204 positioned above the source-drain interconnection region III, and forming a groove exposing the surface of the source-drain electrode in the interlayer dielectric layer 204, wherein the groove crosses the surface of the source-drain electrode in the source-drain interconnection region III; and forming a source drain conductive layer 207 which is filled in the groove. The process steps for forming the trench include: forming a third mask layer on the surface of the interlayer dielectric layer 204, wherein a fourth opening is formed in the third mask layer, and the fourth opening pattern crosses the source and drain electrodes in the source and drain interconnection region III; etching the interlayer dielectric layer 204 along the fourth opening by taking the third mask layer as a mask until the surface of the source drain is exposed to form the groove; and removing the third mask layer.
In another embodiment, the source/drain conductive layer 207 is formed by a double patterning method, so that the position accuracy and the topography accuracy of the formed source/drain conductive layer 207 are further improved.
Referring to fig. 8 to 9, fig. 8 is a schematic diagram based on fig. 7, and fig. 9 is a schematic diagram based on fig. 5, and an upper dielectric layer 208 is formed on the surfaces of the source/drain conductive layers 207 and the surface of the interlayer dielectric layer 204.
The upper dielectric layer 208 is made of silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbonitride. In this embodiment, the upper dielectric layer 208 is made of silicon oxide.
In this embodiment, the interlayer dielectric layer 204 and the upper dielectric layer 208 on the surface of the interlayer dielectric layer 204 form a stacked structure, the stacked structure is a dielectric layer on the top surface and the side wall surface of the gate structure and on the surface of the substrate, the dielectric layer subsequently etched above the source-drain interconnection region III is actually an upper dielectric layer 208 etched above the source-drain interconnection region III, the dielectric layer etched above the bridging region II is actually an upper dielectric layer 208 etched above the bridging region II, the interlayer dielectric layer 204 plays a role in protecting the top of the gate structure, and prevents the bridge conductive layer formed subsequently from being undesirably electrically connected with the gate structure of the bridging region II. In addition, the source-drain conducting layer 207 positioned in the interlayer dielectric layer 204 is formed, so that a subsequently formed zero-layer conducting layer enables a plurality of source-drain electrodes of the source-drain interconnection region III to be electrically connected, the process difficulty of subsequently forming the zero-layer conducting layer can be reduced, and the pattern of the zero-layer conducting layer does not need to stretch across the plurality of source-drain electrodes to be electrically connected of the source-drain interconnection region III.
With continuing reference to fig. 8 to 9, a first mask layer 209 is formed on the surface of the upper dielectric layer 208, the first mask layer 209 has a first opening 301 therein over the source-drain interconnection region III, and the first mask layer 209 also has a second opening 302 therein over the bridging region II.
The projection pattern of the first opening 301 projected on the substrate surface is paved on part or all of the source-drain interconnection region III. In this embodiment, the source-drain conductive layer 207 crossing the source-drain interconnection region III source-drain is formed, so that even if the first opening 301 projects on the source-drain interconnection region III at a portion of the projection pattern profile on the substrate surface, the source-drain in the same source-drain interconnection region III can be electrically connected by the subsequently formed zeroth conductive layer. Therefore, in this embodiment, the requirements on the position accuracy and the profile accuracy of the first opening 301 are low, so that the process flexibility is increased, and the process difficulty is reduced.
In this embodiment, in order to further reduce the difficulty of the process for forming the first opening 301, the width of the first opening 301 is greater than the width of the source-drain interconnection region III.
In this embodiment, a projection pattern of the second opening 302 projected on the substrate surface at least covers the bridging region II, so that the subsequently formed adjacent zeroth gate conductive layer can be electrically connected through the bridging conductive layer.
In this embodiment, the second opening 302 is located above the bridging region II, and is also located above the gate interconnection region I adjacent to the bridging region II, and a projection pattern area of the second opening 302 projected on the adjacent gate interconnection region I is smaller than an area of the gate interconnection region I, so as to reserve a space position for forming a zero-th gate conductive layer subsequently. In order to make the subsequently formed zero-th gate conductive layer contact with the whole top surface of the gate structure, the projection pattern of the second opening 302 projected on the gate interconnection region I does not overlap with the gate structure in the gate interconnection region I. In other embodiments, the second opening is only located above the bridging region.
The first mask layer 209 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium nitride, or tantalum nitride. The material of the first mask layer 209 is different from the material of the upper dielectric layer 208 and the material of the interlayer dielectric layer 204, and in this embodiment, the material of the first mask layer 209 is silicon nitride.
The process steps for forming the first mask layer 209 include: forming an initial mask layer on the surface of the upper dielectric layer 208; forming a graphical photoresist layer on the surface of the initial mask layer; etching the initial mask layer by taking the patterned photoresist layer as a mask to form a first mask layer 209 with a first opening 301 and a second opening 302; and removing the patterned photoresist layer.
In other embodiments, the material of the first mask layer can also be photoresist, and the first mask layer is removed after the first groove and the second groove are formed subsequently; and before the third groove is formed in the subsequent step, forming a second mask layer on the surface of the dielectric layer again.
Referring to fig. 10 and 11, fig. 10 is a schematic view based on fig. 8, fig. 11 is a schematic view based on fig. 9, and the first mask layer 209 (refer to fig. 8 to 9) is used as a mask to etch the upper dielectric layer 208 along the first opening 301 (refer to fig. 8) to form a first groove 311, and simultaneously etch the upper dielectric layer 208 along the second opening 302 (refer to fig. 9) to form a second groove 312.
And etching the upper dielectric layer 208 by adopting a dry etching process to form the first groove 311 and the second groove 312, wherein the first groove 311 penetrates through the upper dielectric layer 208, and the second groove 312 penetrates through the upper dielectric layer 208.
The first groove 311 is located above the source-drain interconnection region III, and the first groove 311 exposes a part or all of the top surface of the source-drain conductive layer 207. In this embodiment, the first groove 311 exposes a portion of the top surface of the source/drain conductive layer 207.
In this embodiment, the bottom of the second groove 312 exposes the top surface of the interlayer dielectric layer 204, and the interlayer dielectric layer 204 plays a role in protecting the top of the gate structure of the bridging region II, so as to prevent the top surface of the gate structure of the bridging region II from being exposed.
The second groove 312 is located above the bridging section II, and a projection pattern of the second groove 312 projected on the substrate surface at least fills the bridging section II. In this embodiment, the second groove 312 is only located above the bridging section II. In other embodiments, the second groove is located above the bridging region and above the gate interconnection region adjacent to the bridging region, and a projected pattern area of the second groove projected on the substrate surface is smaller than an area of the gate interconnection region, so as to reserve a space position for forming a zero gate conductive layer subsequently.
Next, the first mask layer 209 is removed. In other embodiments, the first mask layer can be removed after the zero conductive layer and the bridging conductive layer are formed subsequently; or the first mask layer is not required to be removed before the zero gate conducting layer is formed subsequently, the first mask layer is used as a second mask layer adopted when a second groove is formed subsequently, and the second mask layer is not required to be formed again, so that the production cost can be saved.
Referring to fig. 12 and fig. 14, a zero-layer conductive layer 217 filling the first groove 311 (refer to fig. 10) is formed, and a bridging conductive layer 322 filling the second groove 312 (refer to fig. 11) is formed at the same time, where the zero-layer conductive layer 217 is electrically connected to the source and drain electrodes in the source and drain interconnection region III.
For ease of illustration, the upper dielectric layer 208 and the interlevel dielectric layer 204 are not shown in FIG. 12.
The process steps for forming the zeroth conductive layer 217 and the bridging conductive layer 322 include: forming a conductive film which fills the first groove 311 and the second groove 312, wherein the top of the conductive film is higher than the top of the upper dielectric layer 208; the conductive film above the top of the upper dielectric layer 208 is removed to form the zero layer conductive layer 217 and the bridging conductive layer 322.
The material of the zero conducting layer 217 is one or more of copper, aluminum, tungsten, gold, silver or titanium; the material of the bridging conductive layer 322 is one or more of copper, aluminum, tungsten, gold, silver, or titanium.
In this embodiment, the zero layer conductive layer 217 is electrically connected to the source/drain conductive layer 207, and the source/drain conductive layer 207 is electrically connected to a plurality of source/drain electrodes of the source/drain interconnection region III, so that the zero layer conductive layer 217 is electrically connected to the plurality of source/drain electrodes of the source/drain interconnection region III, and the plurality of source/drain electrodes are electrically connected to other devices or other structures.
In this embodiment, the bridging conductive layer 322 is located above the bridging region II, the bridging conductive layer 322 is also located above the gate interconnection region I adjacent to the bridging region II, and a projection pattern of the bridging conductive layer 322 on the gate interconnection region I does not overlap with the gate structure in the gate interconnection region I, so that a subsequently formed zeroth gate conductive layer is in contact with the entire top surface of the gate structure. In other embodiments, the bridging conductive layer can also be located only over the bridging region; or the projection pattern of the bridging conductive layer projected on the gate interconnection region and the gate structure in the gate interconnection region have an overlapped part.
Referring to fig. 15, fig. 15 is a schematic view based on fig. 14, a second mask layer 231 having a third opening 233 is formed on the surface of the dielectric layer, the third opening 233 is located above the gate interconnection region I, and a part of the surface of the adjacent bridging conductive layer 322 is exposed at the bottom of the third opening 233.
The second mask layer 231 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium nitride, or tantalum nitride. In this embodiment, the second mask layer 231 is made of silicon nitride.
The bottom of the third opening 233 exposes a portion of the surface of the adjacent bridging conductive layer 322, so that the subsequently formed third groove exposes the sidewall surface of the bridging conductive layer 322.
Referring to fig. 16, fig. 16 is a schematic diagram based on fig. 15, a dielectric layer located above the gate interconnection region I is etched, a third groove 243 located above the gate interconnection region I is formed in the dielectric layer, the third groove 243 exposes a surface of the gate structure of the gate interconnection region I, and the third groove 243 also exposes a surface of a sidewall of the bridging conductive layer 322.
Specifically, with the second mask layer 231 (refer to fig. 15) as a mask, the third groove 243 is formed by etching the dielectric layer along the third opening 233 (refer to fig. 15); the second mask layer 231 is removed. In this embodiment, the second mask layer 231 is used as a mask to etch the upper dielectric layer 208 and the interlayer dielectric layer 204 with a partial thickness, and the hard mask layer 206 on the top surface of the gate structure in the gate interconnection region I is further etched and removed until the top surface of the conductive gate 213 is exposed.
In this embodiment, the third recess 243 exposes the entire top surface of the conductive gate 213.
Referring to fig. 13, 17 and 18, fig. 17 is a top view, fig. 13 is a cross-sectional view cut along YY1 in fig. 17, fig. 18 is a cross-sectional view cut along ZZ1 in fig. 17, a zero-th gate conductive layer 253 is formed to fill the third groove 243 (refer to fig. 16), and the adjacent zero-th gate conductive layer 253 contacts with the sidewall of the bridging conductive layer 322.
The material of the zero gate conductive layer 253 is one or more of copper, aluminum, tungsten, gold, silver, or titanium. The process steps for forming the zero gate conductive layer 253 include: forming a conductive film which is filled in the third groove 243, wherein the top of the conductive film is higher than that of the dielectric layer; and removing the conductive film higher than the top of the dielectric layer to form the zero gate conductive layer 253.
In this embodiment, the adjacent zero-th gate conductive layers 253 are electrically connected through the bridging conductive layer 322, so that additional process steps are not required to be performed subsequently, and a first conductive layer electrically connecting the adjacent zero-th gate conductive layers 252 is not required to be formed, thereby saving process steps. Meanwhile, the electrical signal transmission path between adjacent zero gate conductive layers 252 is short, so that the accuracy of the transmitted electrical signal is high, and the electrical performance of the formed semiconductor structure is improved.
In addition, the bridging conductive layer is formed by utilizing the process of forming the conductive layer of the zeroth layer, so that the process steps are not increased, the number of used photomasks is not increased, the electrical performance of the formed semiconductor structure is improved, the process steps are further simplified, and the production cost of the semiconductor is saved.
In other embodiments, when the dielectric layer is a single-layer structure, the first groove is formed to penetrate through the dielectric layer, the second groove is formed to penetrate through the dielectric layer, and the third groove is formed to penetrate through the dielectric layer located above the gate structure of the gate interconnection region. In order to ensure that the bridging conductive layer is electrically insulated from the gate structure of the bridging region, a hard mask layer is formed on the top surface of the gate structure, so that the bottom of the second groove is exposed out of the surface of the hard mask layer, and the hard mask layer enables the subsequently formed bridging conductive layer to be electrically insulated from the gate structure of the bridging region; the first groove exposes the source and drain electrode surface of the source and drain interconnection region, so that the formed zero layer conducting layer is positioned on the source and drain electrode surface, and the zero layer conducting layer stretches across the source and drain electrode surface of the source and drain interconnection region.
In this embodiment, for example, the zero conductive layer and the bridging conductive layer are formed first, and then the zero gate conductive layer is formed, wherein the third groove exposes the sidewall surface of the adjacent bridging conductive layer. In other embodiments, the zeroth gate conductive layer can be formed first, and then the zeroth conductive layer and the bridging conductive layer can be formed.
An embodiment of the present invention further provides a semiconductor structure, with reference to fig. 13, 17, and 18, where the semiconductor structure includes:
the semiconductor device comprises a substrate, wherein discrete gate structures are formed on the surface of the substrate, and source and drain electrodes are formed in the substrate on two sides of the gate structures, wherein the substrate is provided with a gate interconnection region I and a bridging region II positioned between adjacent gate interconnection regions I, the gate interconnection regions I and the bridging region II respectively correspond to different gate structures, the substrate is also provided with a source and drain interconnection region III corresponding to the source and drain electrodes, the source and drain interconnection region III spans a plurality of source and drain electrodes, and the gate interconnection region I, the bridging region II and the source and drain interconnection region III are mutually independent;
the dielectric layers are positioned on the top surface and the side wall surface of the grid structure and the surface of the substrate;
the first groove is positioned in the medium layer and is positioned above the source-drain interconnection region III;
the second groove is positioned in the medium layer and positioned above the bridging area II, and the pattern of the second groove projected on the surface of the substrate at least fully covers the bridging area II;
the zero conducting layer 217 is filled in the first groove;
a bridging conductive layer 322 filling the second recess;
a third groove in the dielectric layer, the third groove being located above the gate interconnection region I, the third groove exposing the surface of the gate structure of the gate interconnection region I, the third groove also exposing the surface of the sidewall of the bridging conductive layer 322;
and the zeroth gate conductive layer 253 is filled in the third groove, and the adjacent zeroth gate conductive layer 253 is in contact with the side wall of the bridging conductive layer 322.
The semiconductor structure provided in the present embodiment will be described in detail below.
The source-drain interconnection regions III are located on two sides of the grid structure and cross the source-drain electrodes in the active regions. The size of the gate interconnection region I is greater than or equal to the size of the gate structure in the arrangement direction of the gate structures, so that the zero-th gate conductive layer 253 is in contact with the entire top surface of the gate structure. The grid interconnection region I is provided with a grid structure, the bridging region II is provided with a grid structure, a zero-level grid conducting layer 253 electrically connected with the corresponding grid structure is formed above the grid interconnection region I, and the zero-level grid conducting layer 253 is electrically insulated from the grid structure of the bridging region II.
The substrate includes: a substrate 201; a plurality of discrete fins 202 on the surface of the substrate 201; an isolation layer 203 located on the surface of the substrate 201, wherein the isolation layer 203 covers part of the sidewall surface of the fin 202, and the top of the isolation layer 203 is lower than the top of the fin 202; the gate structure crosses over the fin 202, the gate structure is located on the surface of the partial isolation layer 203, the side wall and the top surface of the fin, and the source and drain electrodes are located in the fin 202 on two sides of the gate structure. In this embodiment, the source-drain interconnection region III spans the source-drain electrodes in the plurality of fins 202.
The gate structure includes: a gate dielectric layer 211, a work function layer 212 on the surface of the gate dielectric layer 211, and a conductive gate 213 on the surface of the work function layer 212.
The dielectric layers comprise an interlayer dielectric layer 204 and an upper dielectric layer 208 positioned on the surface of the interlayer dielectric layer 204, wherein the interlayer dielectric layer 204 covers the top surface, the side wall surface and the substrate surface of the gate structure, the first groove penetrates through the upper dielectric layer 208, and the second groove penetrates through the upper dielectric layer 208.
An active drain conductive layer 207 is formed in the interlayer dielectric layer 204 above the source-drain interconnection region III, the source-drain conductive layer 207 is positioned on the surface of the source-drain electrode, and the source-drain conductive layer 207 crosses the source-drain electrode in the source-drain interconnection region III. The first groove exposes a part of or all of the top surface of the source drain conductive layer 207. In this embodiment, the first groove exposes a portion of the top surface of the source/drain conductive layer 207, the zero conductive layer 217 is located on a portion of the top surface of the source/drain conductive layer 217, and the width of the zero conductive layer 217 is greater than the width of the source/drain conductive layer 217.
In this embodiment, besides the bridging conductive layer 322 is located above the bridging region II, the bridging conductive layer 322 is also located above the adjacent gate interconnection region I. In other embodiments, the bridging conductive layer is only over the bridging region.
In this embodiment, the zero gate conductive layer 253 covers the entire top surface of the gate structure in the gate interconnection region igold. The sidewall of the zero gate conductive layer 253 contacts the bridge conductive layer 322, so that the adjacent zero gate conductive layer 253 is electrically connected through the bridge conductive layer 322. Compared with the prior art, the electric signal transmission path between the zeroth conductive layer 253 is shorter in the embodiment, so that the external environment interference effect is reduced, the accuracy of the transmitted electric signal is improved, and the processing speed of the semiconductor structure during operation is also improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein discrete gate structures are formed on the surface of the substrate, and source and drain electrodes are formed in the substrate on two sides of the gate structures, wherein the substrate is provided with gate interconnection regions and bridging regions positioned between adjacent gate interconnection regions, the gate interconnection regions and the bridging regions respectively correspond to different gate structures, the substrate is also provided with source and drain interconnection regions corresponding to the source and drain electrodes, the source and drain interconnection regions cross a plurality of source and drain electrodes, and the gate interconnection regions, the bridging regions and the source and drain interconnection regions are mutually independent;
forming dielectric layers on the top surface and the side wall surface of the grid structure and the surface of the substrate;
etching a dielectric layer positioned above a source-drain interconnection region, forming a first groove positioned above the source-drain interconnection region in the dielectric layer, simultaneously etching the dielectric layer positioned above a bridging region, and forming a second groove positioned above the bridging region in the dielectric layer, wherein a projection pattern of the second groove projected on the surface of a substrate at least fully covers the bridging region;
forming a zero conducting layer which is filled in the first groove, and simultaneously forming a bridging conducting layer which is filled in the second groove, wherein the zero conducting layer is electrically connected with a source drain electrode in a source drain interconnection region;
etching the dielectric layer above the grid interconnection region, and forming a third groove above the grid interconnection region in the dielectric layer, wherein the third groove exposes the surface of the grid structure of the grid interconnection region, and the surface of the side wall of the bridging conductive layer is also exposed by the third groove;
and forming a zero gate conducting layer which is filled in the third groove, wherein the adjacent zero gate conducting layer is contacted with the side wall of the bridging conducting layer.
2. The method for forming a semiconductor structure according to claim 1, wherein the dielectric layer comprises an interlayer dielectric layer and an upper dielectric layer located on a surface of the interlayer dielectric layer, wherein the interlayer dielectric layer covers a top surface, a sidewall surface, and a substrate surface of the gate structure, the first recess penetrates through the upper dielectric layer, and the second recess penetrates through the upper dielectric layer.
3. The method for forming the semiconductor structure according to claim 2, wherein a source-drain conductive layer is formed in the interlayer dielectric layer above the source-drain interconnection region before the first groove and the second groove are formed, the source-drain conductive layer is located on a surface of the source-drain electrode, and the source-drain conductive layer crosses the source-drain electrode in the source-drain interconnection region.
4. The method for forming the semiconductor structure according to claim 3, wherein the first groove exposes a part or all of the top surface of the source drain conductive layer.
5. The method for forming a semiconductor structure according to claim 3, wherein the step of forming the dielectric layer and the source-drain conductive layer comprises: forming interlayer dielectric layers on the top surface and the side wall surface of the grid structure and the surface of the substrate; etching an interlayer dielectric layer positioned above a source-drain interconnection region, and forming a groove exposing the surface of a source-drain electrode in the interlayer dielectric layer, wherein the groove crosses the surface of the source-drain electrode in the source-drain interconnection region; forming a source drain conductive layer which is filled in the groove; and forming an upper dielectric layer on the surface of the source drain conductive layer and the surface of the interlayer dielectric layer.
6. The method of forming a semiconductor structure of claim 5, wherein the process step of forming the trench comprises: forming a third mask layer on the surface of the interlayer dielectric layer, wherein a fourth opening is formed in the third mask layer, and the fourth opening pattern crosses the source and drain electrodes in the source and drain interconnection region; and etching the interlayer dielectric layer along the fourth opening by taking the third mask layer as a mask until the surface of the source drain electrode is exposed, thereby forming the groove.
7. The method of forming a semiconductor structure of claim 1, wherein the process steps of forming the zeroth conductive layer and the bridging conductive layer comprise: forming a conductive film which is filled in the first groove and the second groove, wherein the top of the conductive film is higher than that of the dielectric layer; and removing the conductive film higher than the top of the dielectric layer to form the zero conductive layer and the bridging conductive layer.
8. The method of forming a semiconductor structure of claim 1, wherein the process step of forming the first recess and the second recess comprises: forming a first mask layer on the surface of the dielectric layer, wherein the first mask layer is internally provided with a first opening positioned above a source-drain interconnection region, the first mask layer is also internally provided with a second opening positioned above a bridging region, and a projection pattern of the second opening projected on the surface of the substrate at least fully covers the bridging region; taking the first mask layer as a mask, etching the dielectric layer along the first opening to form the first groove, and simultaneously etching the dielectric layer along the second opening to form the second groove; and removing the first mask layer.
9. The method of claim 8, wherein the first mask layer is made of silicon nitride, silicon oxynitride, silicon oxycarbonitride, titanium nitride, or tantalum nitride.
10. The method of forming a semiconductor structure of claim 1, wherein the process step of forming the third recess comprises: forming a second mask layer with a third opening on the surface of the dielectric layer, wherein the third opening is positioned above the grid interconnection region, and the bottom of the third opening exposes partial surfaces of the adjacent bridging conductive layers; etching the dielectric layer along the third opening by taking the second mask layer as a mask to form a third groove; and removing the second mask layer.
11. The method of forming a semiconductor structure of claim 1, wherein the zero gate conductive layer is formed first, and then the zero conductive layer and the bridging conductive layer are formed.
12. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: a substrate; a plurality of discrete fin portions on the surface of the substrate; the isolation layer is positioned on the surface of the substrate, covers part of the side wall surface of the fin part, and the top of the isolation layer is lower than that of the fin part; the grid electrode structure stretches across the fin portion, the grid electrode structure is located on the surface of a part of the isolation layer, the side wall of the fin portion and the surface of the top of the fin portion, and the source electrode and the drain electrode are located in the fin portion on two sides of the grid electrode structure.
13. The method for forming the semiconductor structure according to claim 1, wherein the dielectric layer is a single-layer structure, the first groove penetrates through the dielectric layer, the second groove penetrates through the dielectric layer, and a hard mask layer is formed on the top of the gate structure, wherein the first groove exposes a source/drain surface of the source/drain interconnection region, and the bottom of the second groove exposes a hard mask layer surface.
14. The method for forming the semiconductor structure according to claim 13, wherein the zero conducting layer is located on a source-drain electrode surface, and the zero conducting layer crosses the source-drain electrode surface of the source-drain interconnection region.
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