CN106611712A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN106611712A CN106611712A CN201510706331.1A CN201510706331A CN106611712A CN 106611712 A CN106611712 A CN 106611712A CN 201510706331 A CN201510706331 A CN 201510706331A CN 106611712 A CN106611712 A CN 106611712A
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- 238000000034 method Methods 0.000 title claims abstract description 37
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- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 517
- 239000011229 interlayer Substances 0.000 claims description 45
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- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
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- 238000009413 insulation Methods 0.000 claims description 3
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention relates to a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the steps of forming a dielectric layer at the top surface, the side wall surface and the substrate surface of a grid structure; etching the dielectric layer located above a source-drain interconnecting region, forming a first groove located above the source-drain interconnecting region, etching the dielectric layer located above a bridging region at the same time, and forming a second groove located above the bridging region; forming a zeroth conductive layer which fully fills the first groove, and forming a bridging conductive layer which fully fills the second groove, wherein the zeroth conductive layer is electrically connected with source-drain electrodes in the source-drain interconnection region; etching the dielectric layer located above a grid interconnecting region, and forming third grooves located above the grid interconnecting region in the dielectric layer, wherein the third grooves expose the grid structure surface of the grid interconnecting region; and forming zeroth gate conductive layers which fully fill the third grooves, wherein the adjacent zeroth gate conductive layers are contacted with the side wall of the bridging conductive layer. The electrical performance of the formed semiconductor structure is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and its formation side
Method.
Background technology
Metal interconnection structure is structure indispensable in semiconductor device, for realize active area with it is active
Interconnection between interconnection between area, the interconnection between transistor and transistor or different layers metal wire,
Complete the transmission and control of signal.Therefore, in semiconductor fabrication, the formation of metal interconnection structure
Performance and semiconductor manufacturing cost to semiconductor device has very big impact.In order to increase device
Density, the size of semiconductor device in integrated circuits has been increasingly reduced within a few seconds, in order to realize each partly
The electrical connection of conductor device, it usually needs multilayer interconnection structure.
General, in the rear end interconnection process of fabrication of semiconductor device, first layer metal layer (M1)
Need to form electricity and the active device structures (comprising source and drain areas and grid structure region) of lower floor between
Connection.Therefore, before first layer metal layer is formed, it usually needs be pre-formed the office of semiconductor device
Portion's interconnection structure (Local Interconnect).The local interlinkage structure is included：With the source-drain area of lower floor
Between the level 0 metal level (M0) that electrically connects and the level 0 grid that electrically connect between grid structure
Metal level (M0G).
However, the manufacturing process of the semiconductor structure with local interlinkage structure is complicated in prior art, and
The performance of the semiconductor structure of formation needs further raising.
The content of the invention
The problem that the present invention is solved is to provide a kind of semiconductor structure and forming method thereof, Simplified flowsheet step,
Improve the electric property of the semiconductor structure for being formed.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：There is provided
Substrate, the substrate surface is formed with discrete grid structure, is formed with the substrate of grid structure both sides
Source-drain electrode, wherein, the substrate has gate interconnection area and between neighboring gates interconnecting area
Bridging area, the gate interconnection area and bridging area it is corresponding from different grid structures respectively, the base
Bottom also have the source and drain interconnecting area corresponding with source-drain electrode, the source and drain interconnecting area across several source-drain electrodes,
And the gate interconnection area, bridging area and source and drain interconnecting area are separate；At the top of the grid structure
Surface and sidewall surfaces and substrate surface form dielectric layer；Jie of the etching above source and drain interconnecting area
Matter layer, forms the first groove above source and drain interconnecting area in the dielectric layer, while etching is located at
Dielectric layer above bridging area, forms the second groove above bridging area in the dielectric layer, its
In, second groove is projected on the projecting figure of substrate surface and is at least paved with bridging area；Form filling full
The level 0 conductive layer of first groove, while the bridging conductive layer of full second groove of filling is formed,
The level 0 conductive layer is electrically connected with the source-drain electrode in source and drain interconnecting area；Etching is located in gate interconnection area
The dielectric layer of side, forms the 3rd groove above gate interconnection area in the dielectric layer, and described the
Three grooves expose the grid structure surface in gate interconnection area, and it is conductive that the 3rd groove also exposes bridging
Layer sidewall surfaces；Form the level 0 grid conductive layer of full 3rd groove of filling, and adjacent level 0 grid
Conductive layer contacts with the bridging conductive layer side wall.
Optionally, the dielectric layer includes interlayer dielectric layer and is situated between positioned at the upper strata of inter-level dielectric layer surface
Matter layer, wherein, the interlayer dielectric layer covers grid structural top surface and sidewall surfaces and substrate
Surface, first groove runs through the top dielectric layer, and second groove runs through the top dielectric
Layer.
Optionally, before first groove and the second groove is formed, above the source and drain interconnecting area
Interlayer dielectric layer in form source and drain conductive layer, the source and drain conductive layer is located at source-drain electrode surface, and described
Source-drain electrode of the source and drain conductive layer in source and drain interconnecting area.
Optionally, before first groove and the second groove is formed, above the source and drain interconnecting area
Interlayer dielectric layer in form source and drain conductive layer, the source and drain conductive layer is located at source-drain electrode surface, and described
Source-drain electrode of the source and drain conductive layer in source and drain interconnecting area.
Optionally, forming the dielectric layer and the processing step of source and drain conductive layer includes：In the grid
Structural top surface and sidewall surfaces and substrate surface form interlayer dielectric layer；It is mutual that etching is located at source and drain
Even the interlayer dielectric layer above area, forms the groove for exposing source-drain electrode surface in the interlayer dielectric layer,
Source-drain electrode surface of the groove in source and drain interconnecting area；The source and drain for forming the full groove of filling is conductive
Layer；Top dielectric layer is formed in the source and drain conductive layer surface and inter-level dielectric layer surface.
Optionally, forming the processing step of the groove includes：The is formed in the inter-level dielectric layer surface
With the 4th opening in three mask layers, the 3rd mask layer, the 4th opening figure is across the source
Source-drain electrode in leakage interconnecting area；With the 3rd mask layer as mask, along the 4th opening etching inter-level dielectric
Layer forms the groove up to source-drain electrode surface is exposed.
Optionally, the level 0 conductive layer and bridging conductive layer are initially formed, the level 0 grid is formed afterwards
Conductive layer, wherein, the 3rd groove exposes adjacent bridging conductive layer sidewall surfaces.
Optionally, forming first groove and the processing step of the second groove includes：In the dielectric layer
Surface is formed has above source and drain interconnecting area first to open in the first mask layer, first mask layer
Mouthful, also there is the second opening above bridging area in first mask layer, second opening is thrown
Shadow is at least paved with bridging area in the projecting figure of substrate surface；With first mask layer as mask, along
One opening etch media layer forms first groove, while forming described along the second opening etch media layer
Second groove；Remove first mask layer.
Optionally, forming the processing step of the 3rd groove includes：Formed in the dielectric layer surface and had
There is the second mask layer of the 3rd opening, the 3rd opening is located at gate interconnection area top, and the described 3rd
Open bottom exposes adjacent bridging Conductive layer portions surface；With second mask layer as mask, edge
The 3rd opening etch media layer forms the 3rd groove；Remove second mask layer.
Optionally, the level 0 grid conductive layer is initially formed, the level 0 conductive layer and bridging is formed afterwards
Conductive layer.
The present invention also provides a kind of semiconductor structure, including：Substrate, the substrate surface is formed with discrete
Grid structure, be formed with source-drain electrode in the substrate of grid structure both sides, wherein, the substrate has grid
Pole interconnecting area and the bridging area between neighboring gates interconnecting area, the gate interconnection area and bridge
Even area is corresponding from different grid structures respectively, and the substrate also has the source and drain corresponding with source-drain electrode
Interconnecting area, the source and drain interconnecting area across several source-drain electrodes, and the gate interconnection area, bridging area with
And source and drain interconnecting area is separate；Positioned at the grid structure top surface and sidewall surfaces and substrate
The dielectric layer on surface；The first groove in the dielectric layer, first groove is interconnected positioned at source and drain
Area top；The second groove in the dielectric layer, second groove is located at bridging area top, and
Second groove is projected on the figure of substrate surface and is at least paved with bridging area；Full first groove of filling
Level 0 conductive layer；The bridging conductive layer of full second groove of filling；In the dielectric layer
3rd groove, the 3rd groove is located at gate interconnection area top, and it is mutual that the 3rd groove exposes grid
Connect the grid structure surface in area, the 3rd groove also exposes bridging conductive layer sidewall surfaces；Filling is full
The level 0 grid conductive layer of the 3rd groove, and adjacent level 0 grid conductive layer and the bridging conductive layer
Side wall contacts.
Optionally, the dielectric layer includes interlayer dielectric layer and is situated between positioned at the upper strata of inter-level dielectric layer surface
Matter layer, wherein, the interlayer dielectric layer covers grid structural top surface and sidewall surfaces and substrate
Surface, first groove runs through the top dielectric layer, and second groove runs through the top dielectric
Layer.
Optionally, source and drain conductive layer is formed with the interlayer dielectric layer above the source and drain interconnecting area, it is described
Source and drain conductive layer is located at source-drain electrode surface, and source-drain electrode of the source and drain conductive layer in source and drain interconnecting area.
Optionally, first groove exposes the part or all of top surface of source and drain conductive layer.
Compared with prior art, technical scheme has advantages below：
In the technical scheme of the forming method of the semiconductor structure that the present invention is provided, above source and drain interconnecting area
Dielectric layer in form the first groove, while form the second groove in the dielectric layer above bridging area, its
In, bridging area is located between neighboring gates interconnecting area, and second groove is projected on the projection of substrate surface
Figure is at least paved with the bridging area；The level 0 conductive layer of full first groove of filling is formed, while being formed
The bridging conductive layer of full second groove of filling, the zero layer conductive layer is electric with the source-drain electrode in source and drain interconnecting area
Connection；Dielectric layer of the etching above gate interconnection area, forms mutual positioned at grid in the dielectric layer
Connect the 3rd groove above area, the 3rd groove exposes the grid structure surface in gate interconnection area, institute
State the 3rd groove and also expose bridging conductive layer sidewall surfaces；Form the 0th of full 3rd groove of filling the
Layer grid conductive layer, and adjacent level 0 grid conductive layer contacts with the bridging conductive layer side wall, therefore this
Adjacent level 0 grid conductive layer realizes electrical connection by bridging conductive layer in invention, without the need in order to realize the 0th
Layer grid conductive layer between electrical connection and carry out extra processing step, so as to simplify processing step.And
And, the signal of telecommunication bang path in the present invention between adjacent level 0 grid conductive layer is short, so that transmission
Time needed for the signal of telecommunication is few, and reduces the signal of telecommunication and disturbed by the external world, improves signal of telecommunication transmission
Reliability, so that the electric property of the semiconductor structure for being formed is improved.
Further, before the first groove and the second groove is formed, the layer above the source and drain interconnecting area
Between source and drain conductive layer is formed in dielectric layer, the source and drain conductive layer is located at source-drain electrode surface, and the source and drain
Source-drain electrode of the conductive layer in source and drain interconnecting area, therefore, the level 0 conductive layer being subsequently formed is without the need for horizontal
Across the source-drain electrode of source and drain interconnecting area, the level 0 conductive layer contacts with source and drain conductive layer, so as to
Reduce the technology difficulty to form level 0 conductive layer, reduce to level 0 conductive layer position precision and
The requirement of pattern degree of accuracy, improves technological flexibility.
The present invention also provides a kind of structural behaviour superior semiconductor structure, including：Positioned at grid knot
The dielectric layer of structure top surface and sidewall surfaces and substrate surface；In the dielectric layer first
Groove, first groove is located at source and drain interconnecting area top；The second groove in the dielectric layer,
Second groove is located at bridging area top, and second groove is projected on the figure of substrate surface at least
It is paved with bridging area；The level 0 conductive layer of full first groove of filling；Full second groove of filling
Bridging conductive layer；The 3rd groove in the dielectric layer, the 3rd groove is located at gate interconnection area
Top, the 3rd groove exposes the grid structure surface in gate interconnection area, and the 3rd groove is also sudden and violent
Expose bridging conductive layer sidewall surfaces；The level 0 grid conductive layer of full 3rd groove of filling, and it is adjacent
Level 0 grid conductive layer contacts with the bridging conductive layer side wall, thus adjacent level 0 grid conductive layer it
Between signal of telecommunication bang path it is short, so as to reduce interference of the external environment to signal so that the telecommunications of transmission
Number accuracy rate height, and it is short the time required to transmitting the signal of telecommunication, therefore semiconductor structure has excellent electrical property
Energy.
Description of the drawings
The semiconductor structure schematic diagram that Fig. 1 to Fig. 2 is provided for prior art.
Fig. 3 to Figure 18 forms the structural representation of process for the semiconductor structure that one embodiment of the invention is provided
Figure.
Specific embodiment
According to background technology, the manufacture of the semiconductor structure with local interlinkage structure in prior art
Complex process, and the performance of the semiconductor structure for being formed needs further raising.
It is semiconductor structure dimensional structure diagram with reference to Fig. 1 and Fig. 2, Fig. 1, Fig. 2 is semiconductor structure
Partial top view, semiconductor structure includes：Substrate (not shown)；Positioned at some discrete of substrate surface
Fin 11；Across the grid structure 12 of the fin 11, and the grid structure 12 covers fin 11
Atop part surface and sidewall surfaces；Source and drain in the fin 11 of the both sides of the grid structure 12
Area (does not indicate)；Cover the dielectric layer 13 on the surface of the grid structure 12 and source-drain area surface；With it is described
The level 0 metal level (M0, Metal 0) 14 of source-drain area electrical connection, the level 0 metal level 14 is wrapped
Include the lower metal layer positioned at source-drain area surface and the upper metal level positioned at lower metal layer top surface, it is described under
Layer metal level is located in dielectric layer 13, wherein, along the bearing of trend of fin 11, the upper metal level
Width dimensions more than lower metal layer width dimensions；The level 0 grid electrically connected with the grid structure 12
Metal level (M0G, Metal 0Gate) 15；Some discrete articulamentums 17, part articulamentum 17
In the surface of level 0 metal level 14, part articulamentum 17 is located at the table of level 0 barrier metal layer 15
Face；Positioned at some discrete first layer metal layer (M1, Metal 1) 16 on the surface of articulamentum 17, portion
First layer metal layer 16 is divided to electrically connect with the level 0 metal level 14 by articulamentum 17, part first
Layer metal level 16 is electrically connected by articulamentum 17 with level 0 barrier metal layer 15.
Different level 0 barrier metal layers 15 are electrically connected by first layer metal layer 16, so that the 0th
Layer barrier metal layer 15 is electrically connected with other devices or structure, and the first layer metal layer 16 and level 0
Electrically connected by articulamentum 17 between barrier metal layer 15 so that propagation of electrical signals path length so that partly lead
The electric property less reliable of body structure.Also, due to defining different level 0 barrier metal layers 15
The first layer metal layer 16 of electrical connection, in order that level 0 metal level 14 is electrically connected with other devices or structure,
Also need to be formed the first layer metal layer 16 electrically connected with level 0 metal level 14, the formation of semiconductor structure
Complex process.
For this purpose, the present invention provides a kind of forming method of semiconductor structure, there is provided substrate, the substrate table
Face is formed with discrete grid structure, and in the substrate of grid structure both sides source-drain electrode is formed with, wherein, institute
State substrate and there is gate interconnection area and the bridging area between neighboring gates interconnecting area, the grid
Interconnecting area and bridging area are corresponding from different grid structures respectively, and the substrate also has and source-drain electrode
Corresponding source and drain interconnecting area, the source and drain interconnecting area is across several source-drain electrodes, and the gate interconnection
Area, bridging area and source and drain interconnecting area are separate；The grid structure top surface and sidewall surfaces,
And substrate surface forms dielectric layer；Dielectric layer of the etching above source and drain interconnecting area, in the medium
The first groove above source and drain interconnecting area is formed in layer, while medium of the etching above bridging area
Layer, forms the second groove above bridging area in the dielectric layer, wherein, second groove
The projecting figure for being projected on substrate surface is at least paved with bridging area；Form the of full first groove of filling
Zero layer conductive layer, while forming the bridging conductive layer of full second groove of filling, the level 0 is conductive
Layer is electrically connected with the source-drain electrode in source and drain interconnecting area；Dielectric layer of the etching above gate interconnection area,
The 3rd groove above gate interconnection area is formed in the dielectric layer, the 3rd groove exposes grid
The grid structure surface of pole interconnecting area, the 3rd groove also exposes bridging conductive layer sidewall surfaces；Shape
Expire the level 0 grid conductive layer of the 3rd groove, and adjacent level 0 grid conductive layer and the bridge into filling
Even conductive layer side wall contacts.
The present invention need not be additionally formed the ground floor conductive layer for electrically connecting adjacent level 0 grid conductive layer, lead to
The bridging conductive layer crossed between adjacent level 0 grid conductive layer, makes adjacent level 0 grid conductive layer be electrically connected
Connect, simplify processing step, shorten the signal of telecommunication bang path between adjacent level 0 grid conductive layer,
So as to improve the electric property of the semiconductor structure to be formed.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 3 to Figure 18 shows for the cross-section structure that the semiconductor structure that one embodiment of the invention is provided forms process
It is intended to.
With reference to Fig. 3 to Fig. 5, Fig. 3 is top view, and Fig. 4 is that Fig. 3 is tied along the section that YY1 directions are cut
Structure schematic diagram, Fig. 5 is the cross-sectional view that Fig. 3 cuts along ZZ1 directions, there is provided substrate, described
Substrate surface is formed with discrete grid structure, and source-drain electrode is formed with the substrate of grid structure both sides (not
Sign).
The substrate has the gate interconnection area I and bridging area II between neighboring gates interconnecting area I,
The gate interconnection area I and bridging area II are corresponding from different grid structures respectively, and the substrate is also
With source and drain interconnecting area III corresponding with source-drain electrode, source and drain interconnecting area III across several source-drain electrodes,
And the gate interconnection area I, bridging area II and source and drain interconnecting area III are separate.In the present embodiment,
YY1 directions are mutually perpendicular to grid structure orientation, and ZZ1 directions are mutual with grid structure orientation
Vertically, and along YY1 directions source and drain interconnecting area III is cut, along ZZ1 directions to gate interconnection area
I and the bridging area II between neighboring gates interconnecting area I are cut.
Source and drain interconnecting area III is located at grid structure both sides, and source and drain interconnecting area III is across some
Source-drain electrode in individual active area.In grid structure orientation, the size of the gate interconnection area I is big
In or equal to grid structure size so that the level 0 grid conductive layer being subsequently formed is whole with grid structure
Individual top surface contacts.The gate interconnection area I is formed with grid structure, and the bridging area II is formed
There are grid structure, and the follow-up level 0 formed above gate interconnection area I with the electrical connection of corresponding grid structure
It is electrically insulated between the grid structure of grid conductive layer, the level 0 grid conductive layer and bridging area II.This enforcement
Example with 2 gate interconnection area I and 1 bridging area II as an example, it is in other embodiments, described
The quantity in gate interconnection area and the quantity in bridging area can be determined according to actual process demand.
In the present embodiment, the semiconductor device of formation is fin field effect pipe, and the substrate includes：Substrate
201, positioned at some discrete fin 202 on the surface of substrate 201, positioned at the sealing coat on the surface of substrate 201
203, the sealing coat 203 covers the partial sidewall surface of fin 202, and the top of the sealing coat 203
Less than the top of fin 202.The grid structure is across fin 202, and the grid structure covers fin
202 atop part and sidewall surfaces and the surface of part sealing coat 203.In the present embodiment, the fin
The quantity in portion 202 is more than 1, and the fin 202 is arranged in parallel, and the grid structure is across at least one
Fin 202；The quantity of the grid structure is also greater than 1, and the grid structure is arranged in parallel, the grid
The orientation of pole structure is mutually perpendicular to the orientation of fin 202, and each grid structure is across extremely
A few fin 202.
In another embodiment, the semiconductor device is planar transistor, and the substrate is planar substrates,
The planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate
Or germanium substrate on insulator, glass substrate or III-V substrate (such as gallium nitride substrate or arsenic
Gallium substrate etc.), grid structure is formed at the plane.
The material of the substrate 201 be silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate or the germanium substrate on insulator on insulator to state substrate 201；The fin 202
Material include silicon, germanium, SiGe, carborundum, GaAs or gallium indium；The sealing coat 203 is made
For the isolation structure of semiconductor device, play a part of the adjacent fin 202 of electric isolution, the sealing coat 203
Material be silicon oxide, silicon nitride or silicon oxynitride.In the present embodiment, in the present embodiment, the substrate
201 is silicon substrate, and the material of the fin 202 is silicon, and the material of the sealing coat 203 is silicon oxide.
The source-drain electrode includes the intrabasement source electrode of active area positioned at grid structure opposite sides or leakage respectively
Pole.In the present embodiment, source-drain electrode of source and drain interconnecting area III in several fins 202.It is described
Stressor layers (sign) are also formed with source-drain electrode, the material of the stressor layers is carborundum or SiGe.
When the material of the stressor layers is carborundum, doped with N-type ion in the stressor layers, for example, P,
As or Sb；When the material of the stressor layers is SiGe, doped with p-type ion, example in the stressor layers
Such as it is B, Ga or In.
The grid structure includes：Gate dielectric layer 211, positioned at the work-function layer on the surface of gate dielectric layer 211
212 and positioned at the conductive grid 213 on the surface of work-function layer 212.In the present embodiment, the grid knot
Structure also includes：Positioned at the sidewall surfaces of gate dielectric layer 211, the sidewall surfaces of work-function layer 212 and conductive gate
The side wall (not shown) of the sidewall surfaces of pole 213.
The material of the gate dielectric layer 211 is high-k gate dielectric material, and high-k gate dielectric material is HfO2、
HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3.The work-function layer 212
Material be N-type work function material or p-type work function material, wherein, N-type work function material be TiAl,
TaAlN, TiAlN, MoN, TaCN or AlN, p-type work function material is Ta, TiN, TaN, TaSiN
Or TiSiN.The material of the conductive grid 213 is Al, Cu, Ag, Au, Pt, Ni, Ti or W.
In the present embodiment, the grid structure top surface is also formed with hard mask layer 206, the hard mask
Layer 206 can play a part of to protect conductive grid 213.In the present embodiment, the hard mask layer 206
Material be silicon nitride.In other embodiments, the material of the hard mask layer can also be silicon oxynitride
Or carbon silicon oxynitride.
In other embodiments, the grid structure can also be pseudo- grid structure (dummy gate), wherein,
Grid structure is single layer structure or laminated construction.
With continued reference to Fig. 3 to Fig. 5, in the grid structure top surface and sidewall surfaces and substrate table
Face forms interlayer dielectric layer 204.
It should be noted that for convenience of description, fin 202 and grid structure are illustrate only in Fig. 3
Position relationship, interlayer dielectric layer 204 not shown in Fig. 3.
In the present embodiment, the top of the interlayer dielectric layer 204 is higher than grid structure top.In other enforcements
In example, the interlayer dielectric layer top flushes with grid structure top.
The material of the interlayer dielectric layer 204 is the one kind or many in silicon oxide, silicon nitride, silicon oxynitride
Kind, formation process includes chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process.
In the present embodiment, the material of the interlayer dielectric layer 204 is silicon oxide, and formation process includes plasma
Strengthen chemical vapor deposition (PECVD) technique.
With reference to Fig. 6 to Fig. 7, Fig. 6 is top view, and Fig. 7 is that Fig. 6 is tied along the section that YY1 directions are cut
Source and drain conductive layer is formed in structure schematic diagram, the interlayer dielectric layer 204 above source and drain interconnecting area III
207。
For convenience of description, interlayer dielectric layer 204 not shown in Fig. 6, the dotted line frame illustrated in Fig. 6 is illustrated
Source and drain interconnecting area III across active area regions, i.e., each source and drain interconnecting area across source-drain electrode scope.
In the present embodiment, so that source and drain interconnecting area III is across the source-drain electrode in 4 fins as an example.
The source and drain conductive layer 207 is located at source-drain electrode surface, and the source and drain conductive layer 207 is across described
Source-drain electrode in source and drain interconnecting area III so that several source-drain electrodes in source and drain interconnecting area III are by described
Source and drain conductive layer 207 realizes the purpose being electrically connected to each other, therefore the level 0 conductive layer being subsequently formed only is needed
Electrically connect with source and drain conductive layer 207, it becomes possible to make some in level 0 conductive layer and source and drain interconnecting area III
Individual source-drain electrode electrical connection so that the requirement drop of position precision and pattern degree of accuracy to level 0 conductive layer
It is low, so as to increase technological flexibility, improve the reliability of semiconductor structure.
The material of the source and drain conductive layer 207 is copper, aluminum, tungsten, silver or gold.It is described in the present embodiment
The material of source and drain conductive layer 207 is tungsten.
In one embodiment, forming the processing step of the source and drain conductive layer 207 includes：Etching is located at
Interlayer dielectric layer 204 above source and drain interconnecting area III, forms in the interlayer dielectric layer 204 and exposes
The groove on source-drain electrode surface, source-drain electrode surface of the groove in source and drain interconnecting area III；Form filling
The source and drain conductive layer 207 of the full groove.Forming the processing step of the groove includes：It is situated between in the interlayer
The surface of matter layer 204 forms in the 3rd mask layer, the 3rd mask layer and is open with the 4th, and the described 4th
Source-drain electrode of the opening figure in source and drain interconnecting area III；With the 3rd mask layer as mask, edge
4th opening etching interlayer dielectric layer 204 forms the groove up to source-drain electrode surface is exposed；Remove
3rd mask layer.
In another embodiment, the source and drain conductive layer 207 is formed by Dual graphing method, is further carried
The position precision and pattern degree of accuracy of the source and drain conductive layer 207 that height is formed.
With reference to Fig. 8 to Fig. 9, Fig. 8 is the schematic diagram on the basis of Fig. 7, and Fig. 9 is on the basis of Fig. 5
Schematic diagram, on the surface of source and drain conductive layer 207 and the surface of interlayer dielectric layer 204 top dielectric is formed
Layer 208.
The material of the top dielectric layer 208 is silicon oxide, silicon nitride, silicon oxynitride or carbon silicon oxynitride.
In the present embodiment, the material of the top dielectric layer 208 is silicon oxide.
In the present embodiment, the interlayer dielectric layer 204 and the upper strata positioned at the surface of interlayer dielectric layer 204
Dielectric layer 208 forms laminated construction, and the laminated construction is positioned at grid structure top surface and side wall table
Face and the dielectric layer of substrate surface, subsequent etching is located at the dielectric layer reality above source and drain interconnecting area III
To etch the top dielectric layer 208 above source and drain interconnecting area III, medium of the etching above bridging area II
The actual top dielectric floor 208 for above etching bridging area II of floor, the interlayer dielectric layer 204 plays guarantor
The effect of grille pole structural top, prevents the grid structure of the bridging conductive layer and bridging area II being subsequently formed
The undesirable electrical connection of generation.Also, the shape of the source and drain conductive layer 207 in interlayer dielectric layer 204
Into not only so that the level 0 conductive layer being subsequently formed makes several source-drain electrodes of source and drain interconnecting area III be electrically connected
Connect, additionally it is possible to which reduction is subsequently formed the technology difficulty of level 0 conductive layer so that the figure of level 0 conductive layer
Shape is without the need for several source-drain electrodes to be electrically connected across source and drain interconnecting area III.
With continued reference to Fig. 8 to Fig. 9, the first mask layer 209 is formed on the surface of top dielectric layer 208,
There is in first mask layer 209 the first opening 301 above source and drain interconnecting area III, described the
Also there is the second opening 302 above bridging area II in one mask layer 209.
The projecting figure that first opening 301 is projected on substrate surface is paved with part or all of source and drain interconnection
Area III.In the present embodiment, the source and drain conductive layer 207 across source and drain interconnecting area III source-drain electrode is previously formed,
Therefore, even if the first opening 301 is projected on projecting figure cross sectional portion source and drain interconnecting area III of substrate surface,
Source-drain electrode in same source and drain interconnecting area III can be also electrically connected and be picked up by the level 0 conductive layer being subsequently formed
Come.For this purpose, in the present embodiment, the position precision and pattern degree of accuracy to the described first opening 301
Requirement is relatively low, so as to increased technological flexibility, reduces technology difficulty.
In the present embodiment, in order to further reduce being formed the technology difficulty of the first opening 301, described first
Width dimensions of the width dimensions of opening 301 more than source and drain interconnecting area III.
In the present embodiment, the projecting figure that second opening 302 is projected on substrate surface is at least paved with bridge
Connect area II, so that the adjacent level 0 grid conductive layer being subsequently formed can be realized by bridging conductive layer
Electrical connection.
In the present embodiment, it is described second opening 302 except positioned at bridging area II top in addition to, be also located at it is described
The top of bridging area II adjacent gate interconnection area I, and second opening 302 is projected on neighboring gates
Projecting figure area in interconnecting area I is less than gate interconnection area I areas, so as to be subsequently formed level 0 grid
Conductive layer headspace position.In order that the level 0 grid conductive layer being subsequently formed is whole with grid structure
Top surface contacts, and second opening 302 is projected on projecting figure and grid on gate interconnection area I
Grid structure in interconnecting area I does not have intersection.In other embodiments, second opening is only located at
Bridging area top.
The material of first mask layer 209 be silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxynitride,
Titanium nitride or tantalum nitride.The material of first mask layer 209 is situated between with top dielectric layer 208 and interlayer
The material of matter layer 204 is different, and in the present embodiment, the material of first mask layer 209 is silicon nitride.
Forming the processing step of first mask layer 209 includes：On the surface of top dielectric layer 208
Form original mask layer；Patterned photoresist layer is formed in the original mask layer surface；With the figure
The photoresist layer of shape is mask, etches the original mask layer, is formed and has the first opening 301 and the
First mask layer 209 of two openings 302；Remove the patterned photoresist layer.
In other embodiments, it can also be photoresist that the material of first mask layer is, then follow-up
After forming the first groove and the second groove, first mask layer is removed；It is being subsequently formed the 3rd groove
Before, again in dielectric layer surface the second mask layer of formation.
It is the schematic diagram on the basis of Fig. 8 with reference to Figure 10 and Figure 11, Figure 10, Figure 11 is basic in Fig. 9
On schematic diagram, with first mask layer 209 (refer to Fig. 8 to Fig. 9) as mask, be open along first
301 (referring to Fig. 8) etching top dielectric layer 208 forms the first groove 311, while along the second opening 302
(referring to Fig. 9) etching top dielectric layer 208 forms the second groove 312.
Using dry etch process, etch the top dielectric layer 208 and form the He of the first groove 311
Second groove 312, first groove 311 runs through the top dielectric layer 208, second groove 312
Through the top dielectric layer 208.
First groove 311 is located at source and drain interconnecting area III top, and first groove 311 exposes source
The part or all of top surface of leakage conductive layer 207.In the present embodiment, first groove 311 exposes
Go out the atop part surface of source and drain conductive layer 207.
In the present embodiment, the bottom-exposed of the second groove 312 goes out the top surface of interlayer dielectric layer 204,
The interlayer dielectric layer 204 plays a part of to protect at the top of bridging area II grid structures, it is to avoid bridging area II
Grid structure top surface is exposed.
Second groove 312 is located at bridging area II tops, and second groove 312 is projected on substrate table
The projecting figure in face is at least paved with bridging area II.In the present embodiment, second groove 312 is only located at bridge
Even above area II.In other embodiments, second groove is also located in addition to positioned at bridging area top
The gate interconnection area top adjacent with the bridging area, and the second groove is projected on the projection of substrate surface
Shape area is less than gate interconnection area area, so as to be subsequently formed level 0 grid conductive layer headspace position.
Then, first mask layer 209 is removed.In other embodiments, additionally it is possible to be subsequently formed
After zero layer conductive layer and bridging conductive layer, first mask layer is removed；Or, it is being subsequently formed
First mask layer need not be removed before zero layer grid conductive layer, by the use of first mask layer as follow-up
The second mask layer adopted during the second groove is formed, without the need for forming the second mask layer again such that it is able to save
About production cost.
With reference to Figure 12 and Figure 14, the level 0 of full first groove 311 (referring to Figure 10) of filling is formed
Conductive layer 217, while forming the bridging conductive layer of full second groove 312 (referring to Figure 11) of filling
322, the level 0 conductive layer 217 is electrically connected with the source-drain electrode in source and drain interconnecting area III.
For convenience of description, top dielectric layer 208 and interlayer dielectric layer 204 not shown in Figure 12.
Forming the processing step of the level 0 conductive layer 217 and bridging conductive layer 322 includes：Formed
The conducting film of the full groove 312 of first groove 311 and second of filling, the conducting film top is higher than upper
The top of layer dielectric layer 208；The conducting film higher than the top of top dielectric layer 208 is removed, the described 0th is formed
Layer conductive layer 217 and bridging conductive layer 322.
The material of the level 0 conductive layer 217 is the one kind or many in copper, aluminum, tungsten, gold, silver or titanium
Kind；The material of the bridging conductive layer 322 is one or more in copper, aluminum, tungsten, gold, silver or titanium.
In the present embodiment, the level 0 conductive layer 217 is electrically connected with source and drain conductive layer 207, the source
Leakage conductive layer 207 is electrically connected with several source-drain electrodes of source and drain interconnecting area III, therefore the level 0 is conductive
Layer 217 is electrically connected with several source-drain electrodes of source and drain interconnecting area III, so that described several source-drain electrodes
Electrically connect with other devices or other structures.
In the present embodiment, the bridging conductive layer 322 is located at bridging area II tops, the bridging conductive layer
322 are also located at the gate interconnection area I top adjacent with the bridging area II, and the bridging conductive layer 322
The projecting figure being projected on gate interconnection area I does not have coincidence part with the grid structure in gate interconnection area I
Point, so that the level 0 grid conductive layer being subsequently formed contacts with the whole top surface of grid structure.
In other embodiments, the bridging conductive layer can also be only located at bridging area top；Or, the bridge
Even conductive layer is projected on the projecting figure in gate interconnection area and the grid structure in gate interconnection area has weight
Close part.
With reference to Figure 15, Figure 15 is the schematic diagram on the basis of Figure 14, is formed in the dielectric layer surface and is had
There is the second mask layer 231 of the 3rd opening 233, the 3rd opening 233 is located at gate interconnection area I tops,
And 233 bottoms of the 3rd opening also expose the adjacent part surface of bridging conductive layer 322.
The material of second mask layer 231 be silicon oxide, silicon nitride, silicon oxynitride, carbonitride of silicium,
Titanium nitride or tantalum nitride.In the present embodiment, the material of second mask layer 231 is silicon nitride.
3rd opening, 233 bottom-exposeds go out the adjacent part surface of bridging conductive layer 322, so that
The 3rd groove that must be subsequently formed exposes the sidewall surfaces of bridging conductive layer 322.
With reference to Figure 16, Figure 16 is the schematic diagram on the basis of Figure 15, and etching is located on gate interconnection area I
The dielectric layer of side, forms the 3rd groove 243 above gate interconnection area I, institute in the dielectric layer
The grid structure surface that the 3rd groove 243 exposes gate interconnection area I is stated, the 3rd groove 243 is also sudden and violent
Expose the sidewall surfaces of bridging conductive layer 322.
Specifically, with second mask layer 231 (referring to Figure 15) as mask, along the described 3rd opening
233 (referring to Figure 15) etch media layers form the 3rd groove 243；Remove second mask layer 231.
In the present embodiment, with second mask layer 231 as mask, top dielectric layer 208 and part are etched
The interlayer dielectric layer 204 of thickness, also etching are removed positioned at the hard of gate interconnection area I grid structure top surfaces
Mask layer 206, until exposing the top surface of conductive grid 213.
In the present embodiment, the 3rd groove 243 exposes the whole top surface of conductive grid 213.
With reference to Figure 13, Figure 17 and Figure 18, Figure 17 is top view, and Figure 13 is Figure 17 along YY1 directions
The cross-sectional view of cutting, Figure 18 is the cross-sectional view that Figure 17 cuts along ZZ1 directions,
Form the level 0 grid conductive layer 253 of full 3rd groove 243 (referring to Figure 16) of filling, and adjacent the
Zero layer grid conductive layer 253 contacts with the side wall of the bridging conductive layer 322.
The material of the level 0 grid conductive layer 253 be copper, aluminum, tungsten, gold, silver or titanium in one kind or
It is various.Forming the processing step of the level 0 grid conductive layer 253 includes：Form filling the full described 3rd
The conducting film of groove 243, the conducting film top is higher than dielectric layer top；Remove higher than dielectric layer top
Conducting film, form the level 0 grid conductive layer 253.
In the present embodiment, adjacent level 0 grid conductive layer 253 realizes electrical connection by bridging conductive layer 322,
Therefore, subsequently without the need for carrying out extra processing step again, without the need for re-forming adjacent level 0 grid conductive layer
The 252 ground floor conductive layers being electrically connected, so as to save processing step.Meanwhile, adjacent level 0 grid
Signal of telecommunication bang path between conductive layer 252 is short so that the signal of telecommunication accuracy rate of transmission is high, so that
The electric property of the semiconductor structure that must be formed is improved.
Also, form the bridging conductive layer, therefore this enforcement using the technique for forming level 0 conductive layer
Do not increase processing step in example, do not increase the light shield quantity for using, not only increase the quasiconductor to be formed
The electric property of structure, has further simplified processing step, has saved semiconductor production cost.
In other embodiments, when the dielectric layer is single layer structure, then the first groove for being formed runs through institute
Dielectric layer is stated, the second groove of formation runs through the dielectric layer, and the 3rd groove of formation is through positioned at grid
Dielectric layer above the grid structure of interconnecting area.In order to ensure the grid structure of bridging conductive layer and bridging area
Electric insulation, the grid structure top surface is formed with hard mask layer, so that the second bottom portion of groove is sudden and violent
Expose hard mask layer surface, the hard mask layer causes the bridging conductive layer being subsequently formed and bridging area grid
Structure is electrically insulated；First groove exposes the source-drain electrode surface of source and drain interconnecting area, so that being formed
Level 0 conductive layer be located at source-drain electrode surface, and the level 0 conductive layer is across the source and drain interconnecting area
Source-drain electrode surface.
In the present embodiment, to be initially formed the level 0 conductive layer and bridging conductive layer, described is formed afterwards
As a example by zero layer grid conductive layer, wherein, the 3rd groove exposes adjacent bridging conductive layer sidewall surfaces.
In other embodiments, additionally it is possible to be initially formed level 0 grid conductive layer, the level 0 conductive layer is formed afterwards
With bridging conductive layer.
The embodiment of the present invention also provides a kind of semiconductor structure, with reference to reference to Figure 13, Figure 17 and Figure 18,
The semiconductor structure includes：
Substrate, the substrate surface is formed with discrete grid structure, shape in the substrate of grid structure both sides
Into there is source-drain electrode, wherein, the substrate has gate interconnection area I and positioned at neighboring gates interconnecting area I
Between bridging area II, the gate interconnection area I and bridging area II respectively from different grid structure phases
Correspondence, the substrate also has source and drain interconnecting area III corresponding with source-drain electrode, source and drain interconnecting area III
Across several source-drain electrodes, and the gate interconnection area I, bridging area II and source and drain interconnecting area III are mutual
It is independent；
Positioned at the grid structure top surface and the dielectric layer of sidewall surfaces and substrate surface；
The first groove in the dielectric layer, first groove is located at source and drain interconnecting area III top；
The second groove in the dielectric layer, second groove is located at bridging area II tops, and institute
State the second groove and be projected on the figure of substrate surface and be at least paved with bridging area II；
The level 0 conductive layer 217 of full first groove of filling；
The bridging conductive layer 322 of full second groove of filling；
The 3rd groove in the dielectric layer, the 3rd groove is located at gate interconnection area I tops, institute
The grid structure surface that the 3rd groove exposes gate interconnection area I is stated, the 3rd groove also exposes bridging
The sidewall surfaces of conductive layer 322；
The level 0 grid conductive layer 253 of full 3rd groove of filling, and adjacent level 0 grid conductive layer 253
Contact with the side wall of the bridging conductive layer 322.
The semiconductor structure that the present embodiment is provided will be described in detail below.
Source and drain interconnecting area III is located at grid structure both sides, and source and drain interconnecting area III is across some
Source-drain electrode in individual active area.In grid structure orientation, the size of the gate interconnection area I is big
In or equal to grid structure size so that level 0 grid conductive layer 253 and the whole top of grid structure
Surface contacts.The gate interconnection area I is formed with grid structure, and the bridging area II is formed with grid
Structure, and the level 0 grid conductive layer with the electrical connection of corresponding grid structure is formed with above gate interconnection area I
253, it is electrically insulated between the level 0 grid conductive layer 253 and the grid structure of bridging area II.
The substrate includes：Substrate 201；Positioned at some discrete fin 202 on the surface of substrate 201；Position
In the sealing coat 203 on the surface of the substrate 201, the sealing coat 203 covers the partial sidewall of fin 202
Surface, and the top of the sealing coat 203 is less than the top of fin 202；Wherein, the grid structure across
The fin 202, and the grid structure be located at the surface of part sealing coat 203 and fin side wall and
Top surface, the source-drain electrode is located in the fin 202 of grid structure both sides.It is described in the present embodiment
Source-drain electrode of source and drain interconnecting area III in several fins 202.
The grid structure includes：Gate dielectric layer 211, positioned at the work-function layer on the surface of gate dielectric layer 211
212 and positioned at the conductive grid 213 on the surface of work-function layer 212.
The dielectric layer includes interlayer dielectric layer 204 and is situated between positioned at the upper strata on the surface of interlayer dielectric layer 204
Matter layer 208, wherein, the interlayer dielectric layer 204 cover grid structural top surface and sidewall surfaces, with
And substrate surface, through the top dielectric layer 208, second groove is through described for first groove
Top dielectric layer 208.
Source and drain conductive layer 207, institute are formed with interlayer dielectric layer 204 above source and drain interconnecting area III
Source and drain conductive layer 207 is stated positioned at source-drain electrode surface, and the source and drain conductive layer 207 is across source and drain interconnecting area
Source-drain electrode in III.First groove exposes the part or all of top surface of source and drain conductive layer 207.
In the present embodiment, first groove exposes the atop part surface of source and drain conductive layer 207, and the described 0th
Layer conductive layer 217 is located at the atop part surface of source and drain conductive layer 217, and the width of level 0 conductive layer 217
Size is more than the width dimensions of source and drain conductive layer 217.
In the present embodiment, the bridging conductive layer 322 in addition to positioned at bridging area II tops, lead by the bridging
Electric layer 322 is also located at neighboring gates interconnecting area I top.In other embodiments, the bridging conductive layer is only
Positioned at bridging area top.
In the present embodiment, the level 0 grid conductive layer 253 covers grid interconnecting area I grid structure and entirely pushes up
Portion surface.The side wall of the level 0 grid conductive layer 253 contacts with bridging conductive layer 322, so that
Adjacent level 0 grid conductive layer 253 realizes electrical connection by bridging conductive layer 322.Compared with prior art,
Signal of telecommunication bang path in the present embodiment between level 0 conductive layer 253 is shorter, so as to reduce the external world
Environmental disturbances are acted on so that the signal of telecommunication accuracy rate of transmission gets a promotion, and semiconductor structure is operationally
Processing speed also get a promotion.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of forming method of semiconductor structure, it is characterised in that include：
Substrate is provided, the substrate surface is formed with discrete grid structure, the substrate of grid structure both sides
Source-drain electrode is inside formed with, wherein, the substrate has gate interconnection area and positioned at neighboring gates interconnection
Bridging area between area, the gate interconnection area and bridging area it is corresponding from different grid structures respectively,
The substrate also has the source and drain interconnecting area corresponding with source-drain electrode, and the source and drain interconnecting area is across several
Source-drain electrode, and the gate interconnection area, bridging area and source and drain interconnecting area are separate；
Dielectric layer is formed in the grid structure top surface and sidewall surfaces and substrate surface；
Dielectric layer of the etching above source and drain interconnecting area, forms positioned at source and drain interconnection in the dielectric layer
The first groove above area, while dielectric layer of the etching above bridging area, the shape in the dielectric layer
Into the second groove above bridging area, wherein, second groove is projected on the projection of substrate surface
Figure is at least paved with bridging area；
The level 0 conductive layer of full first groove of formation filling, while it is recessed to form filling completely described second
The bridging conductive layer of groove, the level 0 conductive layer is electrically connected with the source-drain electrode in source and drain interconnecting area；
Dielectric layer of the etching above gate interconnection area, forms in the dielectric layer and is located at gate interconnection
The 3rd groove above area, the 3rd groove exposes the grid structure surface in gate interconnection area, described
3rd groove also exposes bridging conductive layer sidewall surfaces；
Form the level 0 grid conductive layer of full 3rd groove of filling, and adjacent level 0 grid conductive layer with
The bridging conductive layer side wall contacts.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the dielectric layer includes
Interlayer dielectric layer and the top dielectric layer positioned at inter-level dielectric layer surface, wherein, the inter-level dielectric
Layer covers grid structural top surface and sidewall surfaces and substrate surface, and first groove runs through
The top dielectric layer, second groove runs through the top dielectric layer.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that forming described first
Before groove and the second groove, source and drain is formed in the interlayer dielectric layer above the source and drain interconnecting area and is led
Electric layer, the source and drain conductive layer is located at source-drain electrode surface, and the source and drain conductive layer is interconnected across source and drain
Source-drain electrode in area.
4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that first groove is sudden and violent
Expose the part or all of top surface of source and drain conductive layer.
5. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that form the dielectric layer
And the processing step of source and drain conductive layer includes：The grid structure top surface and sidewall surfaces,
And substrate surface forms interlayer dielectric layer；Interlayer dielectric layer of the etching above source and drain interconnecting area,
The groove for exposing source-drain electrode surface is formed in the interlayer dielectric layer, the groove is mutual across source and drain
Connect the source-drain electrode surface in area；Form the source and drain conductive layer of the full groove of filling；Lead in the source and drain
Electric layer surface and inter-level dielectric layer surface form top dielectric layer.
6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that form the groove
Processing step includes：The 3rd mask layer, the 3rd mask layer are formed in the inter-level dielectric layer surface
Inside there is the 4th opening, source-drain electrode of the 4th opening figure in the source and drain interconnecting area；With
3rd mask layer is mask, along the 4th opening etching interlayer dielectric layer until exposing source-drain electrode table
Face, forms the groove.
7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form the level 0
The processing step of conductive layer and bridging conductive layer includes：Form full first groove and second of filling
The conducting film of groove, the conducting film top is higher than dielectric layer top；Remove higher than at the top of dielectric layer
Conducting film, forms the level 0 conductive layer and bridging conductive layer.
8. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that be initially formed the described 0th
Layer conductive layer and bridging conductive layer, form afterwards the level 0 grid conductive layer, wherein, the described 3rd is recessed
Groove exposes adjacent bridging conductive layer sidewall surfaces.
9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that form described first recessed
The processing step of groove and the second groove includes：The first mask layer is formed in the dielectric layer surface, it is described
There is the first opening above source and drain interconnecting area, in first mask layer in first mask layer also
With the second opening above bridging area, second opening is projected on the projection of substrate surface
Shape is at least paved with bridging area；With first mask layer as mask, along the first opening etch media layer shape
Into first groove, while forming second groove along the second opening etch media layer；Remove institute
State the first mask layer.
10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that first mask layer
Material be silicon nitride, silicon oxynitride, carbon silicon oxynitride, titanium nitride or tantalum nitride.
The forming method of 11. semiconductor structures as claimed in claim 8, it is characterised in that form the described 3rd recessed
The processing step of groove includes：Second mask layer with the 3rd opening is formed in the dielectric layer surface,
3rd opening is located at gate interconnection area top, and the 3rd open bottom exposes adjacent bridge
Connect Conductive layer portions surface；With second mask layer as mask, along the described 3rd opening etch media
Layer forms the 3rd groove；Remove second mask layer.
The forming method of 12. semiconductor structures as claimed in claim 1, it is characterised in that be initially formed the described 0th
Layer grid conductive layer, forms afterwards the level 0 conductive layer and bridging conductive layer.
The forming method of 13. semiconductor structures as claimed in claim 1, it is characterised in that the substrate includes：
Substrate；Positioned at some discrete fin of substrate surface；Positioned at the sealing coat of the substrate surface, institute
The partial sidewall surface that sealing coat covers fin, and sealing coat top are stated less than fin top；Its
In, the grid structure across the fin, and the grid structure be located at part insulation surface,
And the side wall and top surface of fin, the source-drain electrode is in the fin of the grid structure both sides.
The forming method of 14. semiconductor structures as claimed in claim 1, it is characterised in that the dielectric layer is single
Rotating fields, first groove runs through the dielectric layer, and second groove runs through the dielectric layer,
And the grid structure top is formed with hard mask layer, wherein, it is mutual that first groove exposes source and drain
Connect the source-drain electrode surface in area, second bottom portion of groove exposes hard mask layer surface.
The forming method of 15. semiconductor structures as claimed in claim 14, it is characterised in that the level 0 is conductive
Layer is located at source-drain electrode surface, and the level 0 conductive layer is across the source-drain electrode table of the source and drain interconnecting area
Face.
16. a kind of semiconductor structures, it is characterised in that include：
Substrate, the substrate surface is formed with discrete grid structure, shape in the substrate of grid structure both sides
Into there is source-drain electrode, wherein, the substrate have gate interconnection area and positioned at neighboring gates interconnecting area it
Between bridging area, the gate interconnection area and bridging area it is corresponding from different grid structures respectively, institute
State substrate and also there is the source and drain interconnecting area corresponding with source-drain electrode, the source and drain interconnecting area is across several sources
Drain electrode, and the gate interconnection area, bridging area and source and drain interconnecting area are separate；
Positioned at the grid structure top surface and the dielectric layer of sidewall surfaces and substrate surface；
The first groove in the dielectric layer, first groove is located at source and drain interconnecting area top；
The second groove in the dielectric layer, second groove is located at bridging area top, and described
Second groove is projected on the figure of substrate surface and is at least paved with bridging area；
The level 0 conductive layer of full first groove of filling；
The bridging conductive layer of full second groove of filling；
The 3rd groove in the dielectric layer, the 3rd groove is located at gate interconnection area top, institute
The grid structure surface that the 3rd groove exposes gate interconnection area is stated, the 3rd groove also exposes bridging
Conductive layer sidewall surfaces；
The level 0 grid conductive layer of full 3rd groove of filling, and adjacent level 0 grid conductive layer with it is described
Bridging conductive layer side wall contacts.
17. semiconductor structures as claimed in claim 16, it is characterised in that the dielectric layer includes interlayer dielectric layer
And positioned at the top dielectric layer of inter-level dielectric layer surface, wherein, the interlayer dielectric layer covers grid
Structural top surface and sidewall surfaces and substrate surface, first groove is situated between through the upper strata
Matter layer, second groove runs through the top dielectric layer.
18. semiconductor structures as claimed in claim 17, it is characterised in that the interlayer above the source and drain interconnecting area
Source and drain conductive layer is formed with dielectric layer, the source and drain conductive layer is located at source-drain electrode surface, and the source
Source-drain electrode of the leakage conductive layer in source and drain interconnecting area.
19. semiconductor structures as claimed in claim 18, it is characterised in that first groove exposes source and drain leads
The part or all of top surface of electric layer.
20. semiconductor structures as claimed in claim 16, it is characterised in that the substrate includes：Substrate；It is located at
The some discrete fin of substrate surface；Positioned at the sealing coat of the substrate surface, the sealing coat covers
The partial sidewall surface of lid fin, and sealing coat top is less than fin top；Wherein, the grid
Pole structure is across the fin, and the grid structure is located at part insulation surface and fin
Side wall and top surface, the source-drain electrode is located in the fin of grid structure both sides.
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| US20210358817A1 (en) * | 2018-06-29 | 2021-11-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of Forming Contact Features in Field-Effect Transistors |
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| CN103247602A (en) * | 2012-02-08 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| US20150129961A1 (en) * | 2013-11-11 | 2015-05-14 | Stmicroelectronics | Bridging local semiconductor interconnects |
| US20150194427A1 (en) * | 2014-01-03 | 2015-07-09 | Samsung Electronics Co., Ltd. | Semiconductor devices including finfets and local interconnect layers and methods of fabricating the same |
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| CN103247602A (en) * | 2012-02-08 | 2013-08-14 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| US20150129961A1 (en) * | 2013-11-11 | 2015-05-14 | Stmicroelectronics | Bridging local semiconductor interconnects |
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