CN106653614B - The production method of retarder in a kind of digital isolator - Google Patents
The production method of retarder in a kind of digital isolator Download PDFInfo
- Publication number
- CN106653614B CN106653614B CN201610903420.XA CN201610903420A CN106653614B CN 106653614 B CN106653614 B CN 106653614B CN 201610903420 A CN201610903420 A CN 201610903420A CN 106653614 B CN106653614 B CN 106653614B
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- Prior art keywords
- retarder
- layer
- digital isolator
- insulating layer
- production method
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- Expired - Fee Related
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 230000008021 deposition Effects 0.000 claims abstract description 3
- 239000010931 gold Substances 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 238000011031 large-scale manufacturing process Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 17
- 238000002955 isolation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
- Manufacturing Cores, Coils, And Magnets (AREA)
Abstract
The invention discloses a kind of production methods of retarder in digital isolator characterized by comprising step 1 provides the wafer substrate comprising inner coil；Step 2, in one insulating layer of wafer deposition on substrate；Step 3, one seed layer of local deposits on the insulating layer；Step 4, on the seed layer, one pattern of lithographic definition, the pattern is Chong Die with the inner coil；Step 5 deposits a metal layer in the photoetching position of the step 4；Step 6 removes the insulating layer of step 2, retains the metal layer；Step 7 removes the seed layer of step 3, retains the metal layer；The metal layer of step 8, the reservation constitutes upper coil, and the upper and lower layer line circle overlaps to form the retarder.The present invention realizes the production of wafer level, is conducive to large-scale production, reduces cost, improves efficiency.And technological parameter is easier to control.
Description
Technical field
The present invention relates to the digital isolators in semicon industry, especially the wherein production method of retarder.
Background technique
In current electronic system, often there are many digital signals and analog signal to be transmitted, while requiring to have
Very high resistive isolation characteristic realizes being isolated between electronic system and user, and optocoupler, Magnetic isolation and Capacitor apart is mostly used
It realizes, but its power consumption, speed, isolation voltage etc. tend not to be optimal.A kind of commonplace mode is, with wireless
Transmission is greatly improved to realize the isolation and transmitting of signal in aspect of performance.Specifically, digital isolator
Side as the input of signal, after converting the signal into radio frequency signal, the other side carries out RF reception and processing, and
Received signal is exported by Output.
Because using the transmitting that wireless signal carries out signal, the conversion of signal and transmission speed are fast, message data rate
It can reach 150Mbps, size can also be made small, and power consumption is very low, and the propagation time is short, and isolation voltage is very high.
Retarder in this digital isolator is carried out by the way of metal wound wire.
As shown in Figure 1, traditional way is using in attachment after the inner coil 10 of digital isolator is completed
Layer conductor 13 simultaneously fixes total with upper cover 11, and export lead 12 is drawn from 11 surface of upper cover.This production method due to
Topping wire 13 is placed directly in centre using whole, and it is more difficult to be aligned, and not only causes performance unstable, moreover, complex process, raw
It produces low efficiency and process parameter control is more difficult.
Summary of the invention
It should be appreciated that the general description and the following detailed description more than disclosure be all it is exemplary and illustrative,
And it is intended that the disclosure as claimed in claim provides further explanation.
The present invention makes the production of lower metal coil fab and upper layer gold by providing a kind of completely new technological process of production
Category coil encapsulation factory can be routed (RDL) by remapping and combine, and realize the production of entire retarder wafer level, no
Production efficiency is only substantially increased, the cost of one single chip is reduced.Technological parameter is easier to control.
In order to achieve the above-mentioned object of the invention, the present invention provides a kind of production method of retarder in digital isolator,
It is characterised by comprising:
Step 1 provides the wafer substrate comprising inner coil；
Step 2, in one insulating layer of wafer deposition on substrate；
Step 3, one seed layer of local deposits on the insulating layer；
Step 4, on the seed layer, one pattern of lithographic definition, the pattern is Chong Die with the inner coil；
Step 5 deposits a metal layer in the photoetching position of the step 4；
Step 6 removes the insulating layer of step 2, retains the metal layer；
Step 7 removes the seed layer of step 3, retains the metal layer；
The metal layer of step 8, the reservation constitutes upper coil, and the upper and lower layer line circle overlaps to form the shielding wire
Circle.
It is preferable to, the present invention also to further disclose a kind of production method of retarder in digital isolator,
It is characterized in that,
Insulating layer is polymolecular polymer in the step 2.
It is preferable to, the present invention also to further disclose a kind of production method of retarder in digital isolator,
It is characterized in that,
The polymolecular polymer includes polyimides.
It is preferable to, the present invention also to further disclose a kind of production method of retarder in digital isolator,
It is characterized in that,
The wafer includes 6 cun, 8 cun or 12 cun.
It is preferable to, the present invention also to further disclose a kind of production method of retarder in digital isolator,
It is characterized in that,
10~the 20um of thickness of insulating layer.
It is preferable to, the present invention also to further disclose a kind of production method of retarder in digital isolator,
It is characterized in that,
The upper coil includes gold, copper, nickel, palladium.
The present invention realizes the production of wafer level, is conducive to large-scale production, reduces cost, improves efficiency.And technique
Parameter is easier to control.
Detailed description of the invention
In the following, referring to attached drawing, for those skilled in the art, from the detailed description to the method for the present invention
In, above and other objects, features and advantages of the invention will be evident.
Fig. 1 is the schematic diagram of the digital isolator of the prior art；
Fig. 2 is the schematic diagram for removing the digital isolator after upper cover 11 in Fig. 1；
Fig. 3 illustrates flow sheet of the invention；
Fig. 4 illustrates the schematic diagram that retarder is made in the method for the present invention.
Appended drawing reference
10-- inner coils
11-- upper covers
12-- leads
13-- topping wires
20-- upper coils
Specific embodiment
Example is described implementation of the disclosure with detailed reference to attached drawing now.Now with detailed reference to the preferred implementation of the disclosure
Example, its example is shown in the drawings.In the case of any possible, phase will be indicated using identical label in all the appended drawings
Same or similar part.In addition, although term used in the disclosure is selected from public term, this
Some terms mentioned in prospectus may be that applicant is judged to carry out selection as his or her, and detailed meanings are at this
Illustrate in the relevant portion of the description of text.Furthermore, it is desirable that not only by used actual terms, and be also to by each
Meaning that term is contained understands the disclosure.
Fig. 3 is referred to, production technological process of the invention is shown, illustrates each step in conjunction with the figure:
Step 1, a wafer substrate comprising inner coil 10 is provided；
Step 2, an insulating layer is deposited over the substrate, which generallys use polymolecular polymer P I, i.e. polyamides is sub-
Amine (Polimide)；
Step 3, pass through UBM technique local deposits seed layer；Here can remark additionally lower UBM technique
Step 4, using the pattern of lithographic definition upper coil 20, the pattern is Chong Die with inner coil 10；
Step 5, a metal layer, usually Au, to form upper coil 20 are deposited in the photoetching position of step 4；
Step 6, remove the insulating layer in step 2, the insulating layer in addition to metal layer is removed；
Step 7, seed layer, the upper coil 20 of reservation being made of metal Au are etched away；
Step 8, completely overlapped upper and lower layer line circle 20 and 10, as retarder are formed.
Finally add upper cover 11, and lead 12 drawn from upper cover 11, become digital isolator as shown in Figure 1 at
Product.
It can see from above-mentioned process, Fig. 4 is the retarder schematic diagram being finally made by the process flow of Fig. 3, on
Inner coil 10 and 20 is completely overlapped.
When retarder work of the invention, inner coil 10, which is powered, generates electric pulse, and the electric field of variation can generate magnetic
, magnetic field is through the insulating layer between upper coil 20, so that upper coil 20 senses magnetic field.Changing magnetic field simultaneously
Electric pulse is generated in upper coil 20 again, thus through the electric impulse signal between insulating layer transmitting different voltages domain.
Wafer employed in technique of the invention can be 6 cun, 8 cun or 12 cun.
The PI thickness of insulating layer employed in technique of the invention can be 10~20um, and the voltage completely cut off as needed comes
It determines, according to following relationship to determine thickness of insulating layer.
Completely cut off voltage=thickness of insulating layer × insulating materials dielectric strength
In the present invention, the material of upper coil 20 is metal AU, this technique of thickness is 2um, if technique can be made
It is thinner, be conducive to cost reduction.The material of upper coil 20 is not limited to gold simultaneously, can be copper, the powereds such as NiPdAu
It can good metal.
The present invention realizes the production of wafer level, is conducive to large-scale production, reduces cost, improves efficiency.And technique
Parameter is easier to control.
The description to preferred embodiment provided above, so that any technical staff in the art can be used or utilize this
Invention.The various modifications of these embodiments are evident for personnel skilled in the art, it can be described here total
Principle be applied to other embodiments without the use of creativeness.Thus, the present invention is not limited to embodiment depicted herein, and answers
According to the widest range for meeting teachings disclosed herein and new feature.
Claims (6)
1. the production method of retarder in a kind of digital isolator characterized by comprising
Step 1 provides the wafer substrate comprising inner coil；
Step 2, in one insulating layer of wafer deposition on substrate；
Step 3, one seed layer of local deposits on the insulating layer；
Step 4, on the seed layer, one pattern of lithographic definition, the pattern is Chong Die with the inner coil；
Step 5 deposits a metal layer in the photoetching position of the step 4；
Step 6 removes the insulating layer of step 2, retains the metal layer；
Step 7 removes the seed layer of step 3, retains the metal layer；
The metal layer of step 8, the reservation constitutes upper coil, and the upper and lower layer line circle overlaps to form the retarder.
2. the production method of retarder in digital isolator according to claim 1, which is characterized in that
Insulating layer includes polymolecular polymer in the step 2.
3. the production method of retarder in digital isolator according to claim 2, which is characterized in that
The polymolecular polymer includes polyimides.
4. the production method of retarder in digital isolator according to claim 1 or 2 or 3, which is characterized in that
The wafer includes 6 cun, 8 cun or 12 cun.
5. the production method of retarder in digital isolator according to claim 4, which is characterized in that
10~the 20um of thickness of insulating layer.
6. the production method of retarder in digital isolator according to claim 5, which is characterized in that
The upper coil includes gold or copper or nickel or palladium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610903420.XA CN106653614B (en) | 2016-10-17 | 2016-10-17 | The production method of retarder in a kind of digital isolator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610903420.XA CN106653614B (en) | 2016-10-17 | 2016-10-17 | The production method of retarder in a kind of digital isolator |
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| Publication Number | Publication Date |
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| CN106653614A CN106653614A (en) | 2017-05-10 |
| CN106653614B true CN106653614B (en) | 2019-03-29 |
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| CN201610903420.XA Expired - Fee Related CN106653614B (en) | 2016-10-17 | 2016-10-17 | The production method of retarder in a kind of digital isolator |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202772678U (en) * | 2012-08-23 | 2013-03-06 | 华南理工大学 | On-line monitoring equipment power supply system based on wireless power transmission technology |
| CN104022113A (en) * | 2014-06-16 | 2014-09-03 | 中国科学院自动化研究所 | Stackable digital isolator based on miniature transformer |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002057032A (en) * | 2000-08-10 | 2002-02-22 | Nippon Shokubai Co Ltd | Thin film magnetic device |
| KR101979025B1 (en) * | 2012-08-01 | 2019-05-16 | 매그나칩 반도체 유한회사 | Metal wiring of semiconductor device and method for manufacturing thereof |
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2016
- 2016-10-17 CN CN201610903420.XA patent/CN106653614B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202772678U (en) * | 2012-08-23 | 2013-03-06 | 华南理工大学 | On-line monitoring equipment power supply system based on wireless power transmission technology |
| CN104022113A (en) * | 2014-06-16 | 2014-09-03 | 中国科学院自动化研究所 | Stackable digital isolator based on miniature transformer |
Non-Patent Citations (1)
| Title |
|---|
| A 2.5kV Isolation 35kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique;Shunichi Kaeriyama，et al.;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;20120229;第47卷(第2期);全文 |
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| CN106653614A (en) | 2017-05-10 |
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Granted publication date: 20190329 Termination date: 20211017 |