CN106653614A - Production method of isolation coil in digital isolator - Google Patents

Production method of isolation coil in digital isolator Download PDF

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Publication number
CN106653614A
CN106653614A CN201610903420.XA CN201610903420A CN106653614A CN 106653614 A CN106653614 A CN 106653614A CN 201610903420 A CN201610903420 A CN 201610903420A CN 106653614 A CN106653614 A CN 106653614A
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CN
China
Prior art keywords
coil
production
layer
digital isolator
retarder
Prior art date
Application number
CN201610903420.XA
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Chinese (zh)
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CN106653614B (en
Inventor
葛晓欢
卢家福
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中颖电子股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

The present invention discloses a production method of an isolation coil in a digital isolator. The production method is characterized by including the following steps that: step 1, a wafer substrate comprising a lower-layer coil is provided; step 2, an insulating layer is deposited on the wafer substrate; step 3, a seed crystal layer is partially deposited on the insulating layer; step 4, a pattern is defined on the seed crystal layer through photo-etching, wherein the pattern is overlapped with the lower-layer coil; step 5, a metal layer is deposited on a photo-etching position in the step 4; step 6, the insulating layer in the step 2 is removed, and the metal layer is reserved; step 7, the seed crystal layer in the step 3 is removed, the metal layer is reserved; and step 8, the reserved metal layer forma an upper-layer coil, and the lower-layer coil and the upper-layer coil are overlapped to form the isolation coil. With the production method of the isolation coil in the digital isolator of the invention adopted, wafer-level production can be realized, large-scale production can be facilitated, costs can be reduced, efficiency can be improved, and process parameters are easier to control.

Description

The production method of retarder in a kind of digital isolator
Technical field
The present invention relates to the digital isolator in semicon industry, the especially wherein production method of retarder.
Background technology
In current electronic system, often there are many data signals and analog signal to need to be transmitted, while requiring have Very high resistive isolation characteristic, realizes isolating between electronic system and user, more using optocoupler, Magnetic isolation and Capacitor apart come Realize, but the aspect such as its power consumption, speed, isolation voltage tends not to be optimal.A kind of commonplace mode is, with wireless Transmit to realize the isolation and transmission of signal, while being greatly improved in aspect of performance.Specifically, digital isolator Side as signal input, after converting the signal into radio frequency signal, opposite side carries out RF receptions and process, and The signal of reception is exported by Output.
Because employing wireless signal carries out the transmission of signal, the conversion of signal and transmission speed are fast, message data rate 150Mbps is can reach, size can also be made thin little, and power consumption is very low, and the propagation time is short, and isolation voltage is very high.
Retarder in this digital isolator is carried out by the way of metal wound wire.
As shown in figure 1, after the inner coil 10 of digital isolator is completed, traditional way is using in attachment Layer conductor 13 and the fixation total of above lid 11, derive lead 12 and draw from the surface of upper lid 11.This production method due to Topping wire 13 is placed directly in centre using overall, and it is more difficult to be aligned, and not only causes unstable properties, and, complex process is raw Product efficiency is low and process parameter control is more difficult.
The content of the invention
It should be appreciated that the general description and the following detailed description more than disclosure is all exemplary and explanat, And it is intended that the disclosure as claimed in claim provides further explanation.
The present invention makes the production of lower metal coil fab and upper strata gold by providing a kind of brand-new technological process of production Category coil encapsulation factory can be combined by remapping wiring (RDL), realize the production of whole retarder wafer level, no Production efficiency is only substantially increased, the cost of one single chip is reduced.Technological parameter is easily controlled.
In order to realize foregoing invention purpose, the invention provides in a kind of digital isolator retarder production method, Characterized in that, including:
Step one, there is provided the wafer substrate comprising inner coil;
Step 2, in the insulating barrier of wafer deposition on substrate one;
Step 3, the inculating crystal layer of local deposits one on the insulating barrier;
Step 4, on the inculating crystal layer, the pattern of lithographic definition one, the pattern is Chong Die with the inner coil;
Step 5, in the photoetching position of the step 4 metal level is deposited;
Step 6, removes the insulating barrier of step 2, retains the metal level;
Step 7, removes the inculating crystal layer of step 3, retains the metal level;
Step 8, the metal level of the reservation constitutes upper coil, and the upper and lower layer line circle overlaps to form the shielding wire Circle.
Reasonable to be, the present invention also further discloses a kind of production method of retarder in digital isolator, its It is characterised by,
Insulating barrier is polymolecular polymer in the step 2.
Reasonable to be, the present invention also further discloses a kind of production method of retarder in digital isolator, its It is characterised by,
The polymolecular polymer includes polyimides.
Reasonable to be, the present invention also further discloses a kind of production method of retarder in digital isolator, its It is characterised by,
The wafer includes 6 cun, 8 cun or 12 cun.
Reasonable to be, the present invention also further discloses a kind of production method of retarder in digital isolator, its It is characterised by,
10~the 20um of thickness of insulating layer.
Reasonable to be, the present invention also further discloses a kind of production method of retarder in digital isolator, its It is characterised by,
The upper coil includes gold, copper, Nie, Palladium.
The present invention realizes the production of wafer level, is conducive to large-scale production, reduces cost to improve efficiency.And technique Parameter is easily controlled.
Description of the drawings
Below, referring to the drawings, for those skilled in the art, from the detailed description to the inventive method In, the above and other objects, features and advantages of the present invention will be evident that.
Fig. 1 is the schematic diagram of the digital isolator of prior art;
Fig. 2 is the schematic diagram for removing the digital isolator after upper lid 11 in Fig. 1;
Fig. 3 illustrates the flow sheet of the present invention;
Fig. 4 illustrates the schematic diagram that the inventive method makes retarder.
Reference
10-- inner coil
11-- upper lid
12-- lead
13-- topping wire
20-- upper coil
Specific embodiment
Now with detailed reference to Description of Drawings embodiment of the disclosure.Present being preferable to carry out with detailed reference to the disclosure Example, its example is shown in the drawings.In the case of any possible, will mark to represent phase using identical in all of the figs Same or similar part.Although additionally, the term used in the disclosure be from public term select, this Some terms mentioned in prospectus are probably that applicant carrys out selection by his or her judgement, and its detailed meanings is at this Explanation in the relevant portion of the description of text.In addition, it is desirable to not only by the actual terms for being used, and be also to by each The meaning that term is contained is understanding the disclosure.
Fig. 3 is referred to, the production technological process of the present invention is shown, with reference to the figure each step is illustrated:
Step 1, there is provided a wafer substrate comprising inner coil 10;
Step 2, deposits over the substrate an insulating barrier, and the insulating barrier generally adopts polymolecular polymer P I, i.e. polyamides sub- Amine (Polimide);
Step 3, by UBM technique local deposits inculating crystal layers;Here can remark additionally lower UBM techniques
Step 4, using the pattern of lithographic definition upper coil 20, the pattern is overlap with inner coil 10;
Step 5, in the photoetching position of step 4 metal level, typically Au, to form upper coil 20 are deposited;
Step 6, removes the insulating barrier in step 2, and the insulating barrier in addition to metal level is removed;
Step 7, etches away inculating crystal layer, the upper coil 20 being made up of metal Au of reservation;
Step 8, forms completely overlapped upper and lower layer line circle 20 and 10, as retarder.
Finally add upper lid 11, and lead 12 drawn from upper lid 11, become digital isolator as shown in Figure 1 into Product.
Can see from above-mentioned flow process, Fig. 4 is the retarder schematic diagram being finally made by the technological process of Fig. 3, on Inner coil 10 and 20 is completely overlapped.
When the retarder of the present invention works, inner coil 10 is powered and produces electric pulse, and the electric field of change can produce magnetic , magnetic field passes through and the insulating barrier between upper coil 20 so that upper coil 20 senses magnetic field.The magnetic field for changing simultaneously Again electric pulse is produced in upper coil 20, thus transmit the electric impulse signal between different voltage domains through insulating barrier.
Wafer can be 6 cun, 8 cun or 12 cun employed in the technique of the present invention.
The PI thickness of insulating barrier can be 10~20um employed in the technique of the present invention, and the voltage for completely cutting off as needed comes Determine, according to relationship below determining thickness of insulating layer.
The dielectric strength of isolation voltage=thickness of insulating layer × insulating materials
In the present invention, the material of upper coil 20 is metal AU, and its thickness this technique is 2um, if technique can be made It is thinner, be conducive to cost to reduce.Simultaneously the material of upper coil 20 is not limited to gold, can be the powereds such as copper , Nie Palladium gold The good metal of energy.
The present invention realizes the production of wafer level, is conducive to large-scale production, reduces cost to improve efficiency.And technique Parameter is easily controlled.
The description to preferred embodiment provided above, so that any technical staff in the art can use or using this Invention.Various modifications to these embodiments are evident for personnel skilled in the art, can be described here total Principle be applied to other embodiment and do not use creativeness.Thus, the present invention is not limited to embodiment depicted herein, and answers According to the widest range for meeting teachings disclosed herein and new feature.

Claims (6)

1. in a kind of digital isolator retarder production method, it is characterised in that include:
Step one, there is provided the wafer substrate comprising inner coil;
Step 2, in the insulating barrier of wafer deposition on substrate one;
Step 3, the inculating crystal layer of local deposits one on the insulating barrier;
Step 4, on the inculating crystal layer, the pattern of lithographic definition one, the pattern is Chong Die with the inner coil;
Step 5, in the photoetching position of the step 4 metal level is deposited;
Step 6, removes the insulating barrier of step 2, retains the metal level;
Step 7, removes the inculating crystal layer of step 3, retains the metal level;
Step 8, the metal level of the reservation constitutes upper coil, and the upper and lower layer line circle overlaps to form the retarder.
2. in digital isolator according to claim 1 retarder production method, it is characterised in that
Insulating barrier includes polymolecular polymer in the step 2.
3. in digital isolator according to claim 2 retarder production method, it is characterised in that
The polymolecular polymer includes polyimides.
4. in the digital isolator according to claim 1 or 2 or 3 retarder production method, it is characterised in that
The wafer includes 6 cun, 8 cun or 12 cun.
5. in digital isolator according to claim 4 retarder production method, it is characterised in that
10~the 20um of thickness of insulating layer.
6. in digital isolator according to claim 5 retarder production method, it is characterised in that
The upper coil includes gold, copper, Nie, Palladium.
CN201610903420.XA 2016-10-17 2016-10-17 The production method of retarder in a kind of digital isolator Active CN106653614B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057032A (en) * 2000-08-10 2002-02-22 Nippon Shokubai Co Ltd Thin film magnetic device
CN202772678U (en) * 2012-08-23 2013-03-06 华南理工大学 On-line monitoring equipment power supply system based on wireless power transmission technology
US20140035146A1 (en) * 2012-08-01 2014-02-06 Kwan-Soo Kim Metal wiring of semiconductor device and method for manufacturing the same
CN104022113A (en) * 2014-06-16 2014-09-03 中国科学院自动化研究所 Stackable digital isolator based on miniature transformer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002057032A (en) * 2000-08-10 2002-02-22 Nippon Shokubai Co Ltd Thin film magnetic device
US20140035146A1 (en) * 2012-08-01 2014-02-06 Kwan-Soo Kim Metal wiring of semiconductor device and method for manufacturing the same
CN202772678U (en) * 2012-08-23 2013-03-06 华南理工大学 On-line monitoring equipment power supply system based on wireless power transmission technology
CN104022113A (en) * 2014-06-16 2014-09-03 中国科学院自动化研究所 Stackable digital isolator based on miniature transformer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHUNICHI KAERIYAMA,ET AL.: "A 2.5kV Isolation 35kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 *

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