CN106652959A - Silicon-based microdisplay column selection drive method and circuit suitable for high-frequency applications - Google Patents
Silicon-based microdisplay column selection drive method and circuit suitable for high-frequency applications Download PDFInfo
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- CN106652959A CN106652959A CN201710045984.9A CN201710045984A CN106652959A CN 106652959 A CN106652959 A CN 106652959A CN 201710045984 A CN201710045984 A CN 201710045984A CN 106652959 A CN106652959 A CN 106652959A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a silicon-based microdisplay column selection drive method and a silicon-based microdisplay column selection drive circuit suitable for high-frequency applications. The column selection drive circuit comprises an SR latch, a phase inverter, and a D-flip flop group with a setting function, wherein the output end VP1 of the SR latch is connected with the input of the phase inverter, the output VP2 of the phase inverter is connected with the input end of the D-flip flop group, and the setting end SET of the first D-flip flop DFF1 in the D-flip flop group is connected with one input end of a NAND gate NAND1 in the SR latch. For the circuit, by utilizing the D-flip flops with the setting function, the low level of the input horizontal synchronizing signal HS is used for realizing setting, and meanwhile, by combining with the SR latch 1 and the D-flip flop group, the generation of column selection signals is realized. For the column selection drive circuit, the occurrence of narrow pulse in a chip can be avoided, and the purpose that the stable column selections are generated at high frequency can be realized.
Description
Technical field
The present invention relates to a kind of microelectronics and Display Technique, especially a kind of column selection driving method of silicon substrate micro display chip
And drive circuit, specifically a kind of silicon substrate micro display column selection driving method and drive circuit suitable for frequency applications.
Background technology
Micro display technology is a branch of display technology field, and it has huge excellent in portable display application aspect
Gesture.And low-power consumption is the very strong driving force of its rapid growth, so the application in its future can be more market-oriented.Micro display technology master
To include liquid crystal on silicon（LCoS）Micro display and silicon-based organic light-emitting diode (OLED) micro display.LCoS micro displays belong to reflection
Formula Display Technique, is realized and achieved with major progress in various projections and nearly eye show.With LCoS technologies
Compare, OLED is actively luminous, it is no longer necessary to which backlight can greatly reduce the power consumption of system；And it can realize flexible showing
Show.No matter any micro display, is all, using silicon chip as backboard is driven, wherein can to collect on silicon substrate display driver chip and embark on journey
Row control circuit, image element circuit, band-gap reference and other functional modules.Wherein column selection drive circuit, produces array selecting signal,
Such that it is able to gate each row pixel, the corresponding switch of each row pixel is opened, corresponding pixel drive voltage is transferred to
Each row pixel.Fig. 1 is a kind of existing silicon substrate micro display column selection drive circuit figure, and Fig. 2 is existing silicon substrate micro display column selection
The sequential chart of drive circuit.The annexation of circuit shown in Fig. 1 is as follows：It is synchronous that the signal input part D of d type flip flop DFF1_1 connects row
The input end of clock of signal HS, d type flip flop DFF1_1 meets pixel clock PCLK, and set end SET of d type flip flop DFF1_1 connects set
The reset terminal CLR of signal SET1, d type flip flop DFF1_1 connects reset signal CLR1；The signal input part D of d type flip flop DFF2_1 connects
D type flip flop DFF1_1 output ends Q0_1, the input end of clock of d type flip flop DFF2_1 meets pixel clock PCLK, d type flip flop DFF2_1
Set end SET meet set signal SET1, the reset terminal CLR of d type flip flop DFF2_1 connects reset signal CLR1；D type flip flop DFFn_
1 signal input part D connects d type flip flop DFFn-1_1 output ends Qn-1, and the input end of clock of d type flip flop DFFn_1 connects pixel clock
Set end SET of PCLK, d type flip flop DFFn_1 meets set signal SET1, and the reset terminal CLR of d type flip flop DFFn_1 connects reset letter
Number CLR1；The course of work of circuit shown in Fig. 1 is as follows：Set signal SET1 is always high level, T<T1Stage reset signal
CLR1 is low level, and circuit enters reseting stage, T>T1Stage, CLR1 is high level, and circuit starts normal work.In PCLK
Before one rising edge in the t2 times, HS is high level, and DFF1_1 produces first row column selection in first rising edge triggering of PCLK
Signal Q0_1, HS is necessary for low level during next PCLK rising edges, so as to next PCLK triggerings make Q0_1 be changed into low level,
Q0_1 connects the input of next trigger DFF2_1, and in PCLK rising edges generation secondary series column selection signal Q1_1 is triggered successively,
Again successively triggering produces the (n-1)th row column selection signal Qn signal.This circuit requirement ensures that HS is high electricity in first CLK rising edge
It is flat, need line synchronising signal HS and pixel clock signal PCLK to have phase difference T2.Simultaneously the pulsewidth of HS needs to meet.In high frequency, the time is very short, such as during 100M, 1TPCLK=10ns, T2=1ns, THS<11ns, if
Chip internal parasitism is excessive, and HS signal high pulse widths may be less likely to not increase, and DFF1_1 cannot complete triggering, causes whole row
Select circuit operational failure.In this regard, the solution that there is no at present.
The content of the invention
The purpose of the present invention is there is a problem of burst pulse easily occur for existing drive circuit and signal stabilization is poor,
A kind of silicon substrate micro display column selection driving method suitable for frequency applications of invention, while providing a kind of corresponding drive circuit.With
Avoid the appearance of burst pulse, realization that stable column selection signal is produced in high frequency.
One of technical scheme is：
A kind of silicon substrate micro display column selection driving method suitable for frequency applications, is characterized in that using the triggerings of the D with set function
Device, using the low level set of input line synchronising signal HS, arranges with reference to S/R latch with the realization of the d type flip flop group with set function
Select the generation of signal.
The S/R latch can be set to " 1 " and " 0 " state according to input signal, S/R latch include NAND gate NAND1 and
NAND gate NAND2, input termination line synchronising signal HS of NAND gate NAND1, another input termination of NAND gate NAND1
The output end of NAND gate NAND2；The output end of the d type flip flop DFF1 of one input terminal strip set function of NAND gate NAND2
Q0, the output of another input termination NAND gate NAND1 of NAND gate NAND2；The phase inverter realizes S/R latch output end
VP1 signals it is anti-phase；The d type flip flop group with set function realizes pulse-triggered VP2 signal；D with set function triggerings
Device group includes d type flip flop DFF1 and d type flip flop DFF2 until DFFn, d type flip flop DFF1 and d type flip flop DFF2, d type flip flop
DFFn includes set end SEL, reset terminal CLR, signal input part D, input end of clock CK；The signal input part D of d type flip flop DFF1
The output VP2 of phase inverter 2 is met, the input end of clock of d type flip flop DFF1 connects pixel clock PCLK, the set end of d type flip flop DFF1
SET connects input termination line synchronising signal HS of NAND gate NAND1, and the reset terminal CLR of d type flip flop DFF1 connects reset signal
CLR1；The signal input part D of d type flip flop DFF2 connects d type flip flop DFF1 output ends Q0, and the input end of clock of d type flip flop DFF2 connects
Set end SET of pixel clock PCLK, d type flip flop DFF2 meets set signal SET1, and the reset terminal CLR of d type flip flop DFF2 connects multiple
Position signal CLR1；The signal input part D of d type flip flop DFFn connects d type flip flop DFFn-1 output ends Qn-1, d type flip flop DFFn when
Clock input termination pixel clock PCLK, set end SET of d type flip flop DFFn connects set signal SET1, the reset of d type flip flop DFFn
End CLR connects reset signal CLR1.
The two of technical scheme are：
A kind of silicon substrate micro display column selection drive circuit suitable for frequency applications, is characterized in that it includes S/R latch（1）, it is anti-phase
Device（2）With the d type flip flop group with set function（3）；The S/R latch（1）Output end VP1 connect phase inverter（2）Input
End, phase inverter（2）Output VP2 tape splicing set functions d type flip flop group（3）Input, the d type flip flop group with set function
（3）First d type flip flop DFF1 set end SET connect S/R latch（1）In NAND gate NAND1 an input.
The described d type flip flop group with set function includes d type flip flop DFF1 and d type flip flop DFF2 until DFFn, D are touched
Sending out device DFF1 and d type flip flop DFF2, d type flip flop DFFn includes set end SEL, reset terminal CLR, signal input part D, clock input
End CK；The signal input part D of d type flip flop DFF1 meets the output VP2 of phase inverter 2, and the input end of clock of d type flip flop DFF1 connects pixel
Set end SET of clock PCLK, d type flip flop DFF1 connects input termination line synchronising signal HS of NAND gate NAND1, D triggerings
The reset terminal CLR of device DFF1 connects reset signal CLR1；The signal input part D of d type flip flop DFF2 connects d type flip flop DFF1 output ends
The input end of clock of Q0, d type flip flop DFF2 meets pixel clock PCLK, and set end SET of d type flip flop DFF2 connects set signal
The reset terminal CLR of SET1, d type flip flop DFF2 connects reset signal CLR1；The signal input part D of d type flip flop DFFn connects d type flip flop
DFFn-1 output ends Qn-1, the input end of clock of d type flip flop DFFn connects pixel clock PCLK, set end SET of d type flip flop DFFn
Set signal SET1 is met, the reset terminal CLR of d type flip flop DFFn connects reset signal CLR1.
The invention has the beneficial effects as follows：
（1）The column selection drive circuit scheme of the present invention avoids the generation of burst pulse of the circuit in frequency applications, enhances electricity
The reliability on road.
（2）The type of drive of the present invention is avoided has phase difference to being input into line synchronising signal HS and pixel clock signal PCLK
Requirement, it is to avoid requirement to HS signal pulse widths.
Description of the drawings
Fig. 1 is existing silicon substrate micro display column selection drive circuit figure.
Fig. 2 is existing silicon substrate micro display column selection drive circuit control sequential figure.
Fig. 3 is the silicon substrate micro display column selection drive circuit figure suitable for frequency applications of the present invention.
Fig. 4 is the control sequential figure of the column selection drive circuit of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawings the present invention is described in detail with specific embodiment.
As shown in Figure 3-4.
A kind of silicon substrate micro display column selection drive circuit suitable for frequency applications, it includes S/R latch 1, phase inverter 2, band
The d type flip flop group 3 of set function.Output end VP1 of the S/R latch 1 meets the input of phase inverter 2, the output VP2 of phase inverter 2
Connect the input of d type flip flop group 3, first d type flip flop DFF1 set end SET of d type flip flop group 3 connect in S/R latch 1 with
One input of not gate NAND1.Circuit utilizes the d type flip flop with set function, using the low electricity of input line synchronising signal HS
Horizontal position, with reference to S/R latch 1 and d type flip flop group 3 generation of column selection signal is realized.The S/R latch 1 can be according to input
Signal is set to " 1 " and " 0 " state, and S/R latch 1 includes NAND gate NAND1 and NAND gate NAND2, one of NAND gate NAND1
Input termination line synchronising signal HS, the output of another input termination NAND gate NAND2 of NAND gate NAND1；NAND gate NAND2
An input termination d type flip flop DFF1 output end Q0, another input termination NAND gate NAND1 of NAND gate NAND2
Output.The phase inverter 2 realizes the anti-phase of the output end VP1 signal of S/R latch 1.Phase inverter 2 includes phase inverter INV1.The band
The d type flip flop group 3 of set function realizes pulse-triggered VP2 signal.D type flip flop group 3 includes d type flip flop DFF1 and d type flip flop
DFF2 until DFFn, d type flip flop DFF1 and d type flip flop DFF2, d type flip flop DFFn include set end SEL, reset terminal CLR,
Signal input part D, input end of clock CK.The signal input part D of d type flip flop DFF1 connects the output VP2 of phase inverter 2, d type flip flop
The input end of clock of DFF1 meets pixel clock PCLK, and set end SET of d type flip flop DFF1 connects an input of NAND gate NAND1
Termination line synchronising signal HS, the reset terminal CLR of d type flip flop DFF1 connects reset signal CLR1；The signal input of d type flip flop DFF2
End D connects d type flip flop DFF1 output ends Q0, and the input end of clock of d type flip flop DFF2 meets pixel clock PCLK, d type flip flop DFF2's
Set end SET meets set signal SET1, and the reset terminal CLR of d type flip flop DFF2 connects reset signal CLR1；The letter of d type flip flop DFFn
Number input D connects d type flip flop DFFn-1 output ends Qn-1, and the input end of clock of d type flip flop DFFn meets pixel clock PCLK, and D is touched
Set end SET for sending out device DFFn meets set signal SET1, and the reset terminal CLR of d type flip flop DFFn connects reset signal CLR1.
From drive circuit 3, the essence of the present invention is using the d type flip flop with set function, using line of input synchronization
The low level set of signal HS, the d type flip flop group with reference to S/R latch and with set function realizes the generation of column selection signal.
With reference to Fig. 4, the course of work of circuit shown in Fig. 3 is described in detail：Set signal SET1 is always height
Level, first, T<T1Stage reset signal CLR1 is low level, and circuit enters reseting stage, T>T1Stage, CLR1 is high electricity
Flat, circuit starts normal work.HS is low level, makes first row column selection signal Q0 that DFF1 is exported be high level, and DFF2 is exported
Secondary series column selection signal Q1 be high level, VP1 is high level, through phase inverter VP2 be low level, during PCLK rising edges, VP2
For low level, so as to trigger generation Q0 low level is changed into, Q0 is changed into low level rest-set flip-flop output low level, and VP1 is changed into low electricity
Flat, VP2 is changed into high level.When next PCLK rising edges are triggered, VP2 is high level, and so as to trigger Q0 high level, Q1 are changed into
It is changed into low level.Q1 connects the input of next trigger, triggers successively in PCLK rising edges, produces the (n-1)th row column selection signal
Qn.Column selection signal Qn andIt is inverted relationship, so column selection signal needs high level pulse and low level pulse.
In high frequency, such as during 100M, 1TPCLK=10ns, the present invention only needs to pulsewidth T of HSHS>1TPCLK,Need not be to row
The pulsewidth of synchronizing signal HS makes narrow restriction, it is not required that propose phase to line synchronising signal HS and pixel clock signal PCLK
The requirement of potential difference.The generation of line synchronising signal HS burst pulse in circuit is avoided, the reliability of the circuit is enhanced.
The present invention is not limited to above-mentioned embodiment, no matter micro display resolution sizes, every employing S/R latch 1, instead
Phase device 2, the structure of d type flip flop group 3 with set function produces column selection signal, all should fall within the scope of the present application.
Part that the present invention does not relate to is same as the prior art or can be realized using prior art.
Claims (4)
1. a kind of silicon substrate micro display column selection driving method suitable for frequency applications, is characterized in that being touched using the D with set function
Device is sent out, using the low level set of input line synchronising signal HS, is realized with the d type flip flop group with set function with reference to S/R latch
The generation of column selection signal.
2. method according to claim 1, is characterized in that：The S/R latch can be set to " 1 " and " 0 " according to input signal
State, S/R latch includes NAND gate NAND1 and NAND gate NAND2, an input termination line synchronising signal of NAND gate NAND1
HS, the output end of another input termination NAND gate NAND2 of NAND gate NAND1；One input terminal strip of NAND gate NAND2
Output end Q0 of the d type flip flop DFF1 of set function, the output of another input termination NAND gate NAND1 of NAND gate NAND2；
The phase inverter realizes the anti-phase of S/R latch output end VP1 signal；The d type flip flop group with set function realizes that pulse is touched
Send out VP2 signals；D type flip flop group with set function includes d type flip flop DFF1 and d type flip flop DFF2 until DFFn, d type flip flop
DFF1 and d type flip flop DFF2, d type flip flop DFFn include set end SEL, reset terminal CLR, signal input part D, input end of clock
CK；The signal input part D of d type flip flop DFF1 meets the output VP2 of phase inverter 2, when the input end of clock of d type flip flop DFF1 connects pixel
Set end SET of clock PCLK, d type flip flop DFF1 connects input termination line synchronising signal HS of NAND gate NAND1, d type flip flop
The reset terminal CLR of DFF1 connects reset signal CLR1；The signal input part D of d type flip flop DFF2 connects d type flip flop DFF1 output ends Q0,
The input end of clock of d type flip flop DFF2 meets pixel clock PCLK, and set end SET of d type flip flop DFF2 meets set signal SET1, D
The reset terminal CLR of trigger DFF2 connects reset signal CLR1；It is defeated that the signal input part D of d type flip flop DFFn meets d type flip flop DFFn-1
Go out and hold Qn-1, the input end of clock of d type flip flop DFFn meets pixel clock PCLK, and set end SET of d type flip flop DFFn connects set letter
Number SET1, the reset terminal CLR of d type flip flop DFFn connect reset signal CLR1.
3. a kind of silicon substrate micro display column selection drive circuit suitable for frequency applications, is characterized in that it includes S/R latch（1）, instead
Phase device（2）With the d type flip flop group with set function（3）；The S/R latch（1）Output end VP1 connect phase inverter（2）Input
End, phase inverter（2）Output VP2 tape splicing set functions d type flip flop group（3）Input, the d type flip flop group with set function
（3）First d type flip flop DFF1 set end SET connect S/R latch（1）In NAND gate NAND1 an input.
4. drive circuit according to claim 3, is characterized in that the described d type flip flop group with set function is touched including D
Device DFF1 and d type flip flop DFF2 is sent out until DFFn, d type flip flop DFF1 and d type flip flop DFF2, d type flip flop DFFn include set
End SEL, reset terminal CLR, signal input part D, input end of clock CK；The signal input part D of d type flip flop DFF1 connects phase inverter 2
Output VP2, the input end of clock of d type flip flop DFF1 meets pixel clock PCLK, and set end SET of d type flip flop DFF1 connects NAND gate
One input termination line synchronising signal HS of NAND1, the reset terminal CLR of d type flip flop DFF1 connects reset signal CLR1；D type flip flop
The signal input part D of DFF2 connects d type flip flop DFF1 output ends Q0, and the input end of clock of d type flip flop DFF2 meets pixel clock PCLK,
Set end SET of d type flip flop DFF2 meets set signal SET1, and the reset terminal CLR of d type flip flop DFF2 connects reset signal CLR1；D is touched
The signal input part D for sending out device DFFn connects d type flip flop DFFn-1 output ends Qn-1, and the input end of clock of d type flip flop DFFn connects pixel
Set end SET of clock PCLK, d type flip flop DFFn meets set signal SET1, and the reset terminal CLR of d type flip flop DFFn connects reset letter
Number CLR1.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070247687A1 (en) * | 2006-04-24 | 2007-10-25 | Handschy Mark A | Spatial light modulators with changeable phase masks for use in holographic data storage |
| CN102360539A (en) * | 2011-10-10 | 2012-02-22 | 上海大学 | Drive circuit of silicon-based organic light emitting diode micro-display |
| CN104282341A (en) * | 2014-10-27 | 2015-01-14 | 南开大学 | Integrated asynchronous transmission shift register circuit of LCoS (Liquid Crystal On Silicon) and implementing method thereof |
| CN105355169A (en) * | 2015-11-24 | 2016-02-24 | 中国电子科技集团公司第五十五研究所 | Novel silicon-based OLED micro-display driving control circuit |
| CN106205481A (en) * | 2016-07-06 | 2016-12-07 | 昀光微电子（上海）有限公司 | A kind of microdisplay on silicon |
-
2017
- 2017-01-20 CN CN201710045984.9A patent/CN106652959B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070247687A1 (en) * | 2006-04-24 | 2007-10-25 | Handschy Mark A | Spatial light modulators with changeable phase masks for use in holographic data storage |
| CN102360539A (en) * | 2011-10-10 | 2012-02-22 | 上海大学 | Drive circuit of silicon-based organic light emitting diode micro-display |
| CN104282341A (en) * | 2014-10-27 | 2015-01-14 | 南开大学 | Integrated asynchronous transmission shift register circuit of LCoS (Liquid Crystal On Silicon) and implementing method thereof |
| CN105355169A (en) * | 2015-11-24 | 2016-02-24 | 中国电子科技集团公司第五十五研究所 | Novel silicon-based OLED micro-display driving control circuit |
| CN106205481A (en) * | 2016-07-06 | 2016-12-07 | 昀光微电子（上海）有限公司 | A kind of microdisplay on silicon |
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