CN105355169A - Novel silicon-based OLED micro-display driving control circuit - Google Patents
Novel silicon-based OLED micro-display driving control circuit Download PDFInfo
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Abstract
The invention relates to a novel silicon-based OLED micro-display driving control circuit and a control method. The characteristics are that an odd-number column shift register and an even-number column shift register respectively receive externally inputted 10-bit image data signals, data of the odd-number column shift register and data of the even-number column shift register are completely inputted into an odd-number column latch and an even-number column latch respectively after M/2 times of shifting is completed, a counter modules counts from 0 to 1023 and then back to 0 at the same time, counting is carried out in a circulation manner, the 10-bit image data signals outputted by the latches are compared with 10-bit signals outputted by a counter through an odd-number column comparator module and an even-number column comparator module, a comparison result is outputted through the above comparison so as to control a column selection switch of a pixel unit, and analog voltage outputted by a DAC is transmitted to the corresponding pixel unit. The driving mode provided by the invention avoids sudden changes between minimum voltage and maximum voltage of the DAC output voltage, thereby reducing requirements for the driving capability thereof, and reducing the system power consumption.
Description
Technical field
The present invention relates to a kind of microelectronics and display technique field, especially a kind of OLED technology, specifically a kind of Drive and Control Circuit of silica-based OLED micro display chip.
Background technology
The micro-display technique of silica-based OLED is the combination of oled light electronic technology and si-substrate integrated circuit microelectric technique, is mainly used in micro-display field.Be utilize ripe CMOS integrated circuit technology, after chip manufacturing is intact, then carry out the making of OLED, improve the yield of whole display.OLED is as display technique of new generation, there is active illuminating, visual angle is wide, driving voltage is low, luminescence efficiency is high, fast response time, low in energy consumption, OLED be full solid-state device, do not need heating and cooling just can be operated in the temperature range of-40 DEG C ~+70 DEG C, and Flexible Displays feature can be realized, there is very wide prospect.OLED micro-display volume is little, is easy to carry very much, and its nearly eye display effect relying on small size to provide can compare favourably with large scale displayer.
At present except the OLED of research high stable performance, study its Driving technique also very important.The micro-display technique of silica-based OLED is directly made in monocrystalline silicon integrated circuit (IC) chip OLED.Thus the integrated of its peripheral driving circuit and display pixel matrix circuit can be realized.Wherein can integrated row column control circuit, image element circuit, band-gap reference and other functional module on silica-based display driver chip, thus significantly reduce the cost of system, area and power consumption.And decrease external devices and intraconnections number, add reliability.
Summary of the invention
The object of the invention is the development in order to adapt to silica-based OLED display technique, inventing a kind of new driving method, provide a kind of corresponding driving circuit, the control signal part of driving circuit is supply voltage 1.8V, and image element circuit is supply voltage 5V simultaneously.
One of technical scheme of the present invention is:
The micro-display drive control circuit of a kind of novel silicon base OLED, it comprises odd column shift register, odd column latch, odd column comparer, odd column level shift, odd number column selection switch module, even column shift register, latch, even column comparer, even column level shift, even number column selection switch module, even column row cutting module, DAC module basic counter module, is characterized in that input signal clock signal PCLK and the 10 digital video signal datas respectively of described odd column shift register module.The output terminal of odd column shift register is connected with the input end of odd column latch, another input end connected row synchronizing signal HS of odd column latch, the output of odd column latch connects the input of odd column comparer, the output of odd column comparer connects the input of odd column level shift, the output of odd column level shift connects odd column switch, and odd column switch exports and connects OLED array odd column pixel.Input signal clock signal PCLK and the 10 digital video signal datas respectively of even column shift register module.The output terminal of even column shift register is connected with the input end of even column latch, another input end connected row synchronizing signal HS of even column latch, the output of even column latch connects the input of even column comparer, the output of even column comparer connects the input of even column level shift, the output of even column level shift connects even column switch, and even column switch exports and connects OLED array even column pixels.The input of counter meets line synchronizing signal HS, pixel clock PCLK, reset signal RST, the output of counter meets odd column comparer, even column comparer, 10 DAC, 10 DAC export and meet BUFFER1 and BUFFER2, the input of row cutting module meets line synchronizing signal HS, frame synchronizing signal VS, row cutting module exports and connects level shift, and level shift exports and connects OLED array.
The form that described odd column shift register and even column shift register all adopt M/2 d type flip flop connected in series, receives the viewdata signal of 10 respectively, exports as M/2 10 bit data parallel outputs.
Described odd column latch and even column latch input signal correspond to odd column shift register and even column shift register output signal, and clock input signal is line scanning synchronizing signal HS.
Described odd column comparer and even column comparer comprise M/2 comparator unit respectively.Input signal is the output signal of odd column latch and even column Latch output signal sum counter respectively.Compared with 10 signals that the viewdata signal of 10 and counter export by comparator module, comparative result outputs to electrical level shift units.
Described odd column level shift and even column level shift comprise M/2 electrical level shift units respectively.Odd column comparer and even column comparer Output rusults level are converted to 5V from 1.8V.
Described odd number column selection switch and even number column selection switch module comprise M/2 column selection switch element respectively.
Described pel array comprises M row × N capable pixel unit circuit;
Described line-scan circuit comprises the d type flip flop of N number of serially concatenated; Previous d type flip flop exports the next d type flip flop input end of termination, and first d type flip flop input signal comprises line synchronizing signal HS, frame synchronizing signal VS.
Described counter module input signal comprises line synchronizing signal HS, pixel clock PCLK, reset signal RST, exports the input connecting odd column comparer, even column comparer, 10 DAC.Counter module count down to 1023 again to 0 from 0, and circulation counts.
10 position digital signals being input as counter output of 10 described DAC, 10 DAC export and meet impact damper BUFFER1 and impact damper BUFFER2.
Two of technical scheme of the present invention is:
A kind of driving method of novel silica-based OLED micro display chip, it is characterized in that: from the viewdata signal of external control accepts 10, (shift register is divided into upper and lower two parts to chip shift register, odd column shift register receives odd column data above, even column shift register receives even column data below, odd column and even column work simultaneously), triggered by the pixel shift rising edge clock of shift register, viewdata signal is shifted from one end of shift register to the other end successively, complete all be shifted time, line synchronizing signal arrive; Latch, when line synchronizing signal arrives, is deposited with in latch whole for the data in shift register input latch; Counter module count down to 1023 again to 0 from 0, compared with 10 signals (10 the DAC input signals) viewdata signal of 10 and counter exported by comparator module, wherein the column selection control mode of odd-numbered line is: the gating time of column selection signal is the time that counter data is less than or equal to this row latch 10 digital video data-signal, and the column selection control mode of even number line is: the gating time of column selection signal is the time that counter data is greater than this row latch 10 digital video data-signal.Comparative result determines gating time size, corresponding odd number column selection and even number column selection switch is controlled by electrical level shift units, the analog voltage that DAC exports is transferred in corresponding pixel cell, meanwhile, line-scan circuit produces line scan signals and chooses in pel array the display line requiring to be lit line by line.
The invention has the beneficial effects as follows:
(1) type of drive of the present invention adds the gating time of column selection switch.
(2) type of drive of the present invention avoids the sudden change of DAC output voltage between minimum voltage and ceiling voltage, reduces the requirement to its driving force, reduces system power dissipation.
Accompanying drawing explanation
Fig. 1 is OLED of the present invention micro-display driver chip control circuit block diagram;
Fig. 2 is the Control timing sequence figure of the micro-display driver chip of OLED of the present invention;
Fig. 3 is pixel cell signal of the present invention write embodiment.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment one.
As shown in Figure 1.
The micro-display drive control circuit of a kind of novel silicon base OLED, it comprises odd column shift register, odd column latch, odd column comparer, odd column level shift, odd number column selection switch module, even column shift register, latch, even column comparer, even column level shift, even number column selection switch module, even column row cutting module, DAC module basic counter module, input signal clock signal PCLK and the 10 digital video signal datas respectively of odd column shift register module.The output terminal of odd column shift register is connected with the input end of odd column latch, another input end connected row synchronizing signal HS of odd column latch, the output of odd column latch connects the input of odd column comparer, the output of odd column comparer connects the input of odd column level shift, the output of odd column level shift connects odd column switch, and odd column switch exports and connects OLED array odd column pixel.Input signal clock signal PCLK and the 10 digital video signal datas respectively of even column shift register module.The output terminal of even column shift register is connected with the input end of even column latch, another input end connected row synchronizing signal HS of even column latch, the output of even column latch connects the input of even column comparer, the output of even column comparer connects the input of even column level shift, the output of even column level shift connects even column switch, and even column switch exports and connects OLED array even column pixels.The input of counter meets line synchronizing signal HS, pixel clock PCLK, reset signal RST, the output of counter meets odd column comparer, even column comparer, 10 DAC, 10 DAC export and meet BUFFER1 and BUFFER2, the input of row cutting module meets line synchronizing signal HS, frame synchronizing signal VS, row cutting module exports and connects level shift, and level shift exports and connects OLED array.
Fig. 3 is a) a complete concrete Drive and Control Circuit of odd column of the present invention, and the composition of even column is identical.Odd column Drive and Control Circuit in Fig. 3 is made up of the pixel cell 1 in 10 DAC, BUFFER1, odd number column selection switch, odd column level shift and dotted line frame, pixel cell 2.10 DAC export and connect odd number column selection switch through BUFFER1.Odd column level shift is input as COMP1 and COMP2, and odd column level shift output signal controls odd number column selection switch.The drain electrode of P type metal-oxide-semiconductor MP1 and the output of odd column switch, electric capacity C
pone end is connected, and the source electrode of P type metal-oxide-semiconductor MP1 is connected with the grid of one end of electric capacity C1, N-type metal-oxide-semiconductor MN1.The grid of P type metal-oxide-semiconductor MP1 selects control signal HS1 to be connected with row.Electric capacity C2, electric capacity C
pthe other end be connected with ground GND.The drain electrode of N-type metal-oxide-semiconductor MN1 is connected with voltage VDD, and the source electrode of N-type metal-oxide-semiconductor MN1 is connected with the source electrode of P type metal-oxide-semiconductor MP1_2, and the drain electrode of P type metal-oxide-semiconductor MP1_2 is connected with OLED anode, and the grid of P type metal-oxide-semiconductor MP1_2 is connected with ground GND.The negative electrode of OLED is connected with Vcom voltage.
Embodiment two.
As shown in Figure 2.
A kind of driving method of novel silica-based OLED micro display chip, first odd column shift register and even column shift register receive the viewdata signal of 10 of outside input respectively, after completing M/2 displacement, line synchronizing signal arrives, odd column shift register and even column shift register data are all input in odd column latch and even column latch respectively, unison counter module count down to 1023 again to 0 from 0, cycle count, then compared with 10 signals that the viewdata signal of 10 exported by latch with even column comparator module by odd column comparator module and counter are exported, wherein the column selection control mode of odd-numbered line is: the gating time of column selection signal is the 10 digital video data-signals that counter data is less than or equal to this row latch, the column selection control mode of even number line is: the gating time of column selection signal is the 10 digital video data-signals that counter data is greater than this row latch.Comparative result determines gating time size, comparative result carries out level conversion by electrical level shift units and controls corresponding odd number column selection and even number column selection switch, is transferred in corresponding pixel cell by the analog voltage that DAC exports by impact damper BUFFER1 and BUFFER2.Meanwhile, line-scan circuit produces line scan signals and chooses in pel array the display line requiring to be lit line by line.
As shown in Figure 2, t1 stage reset signal RST is low level to the groundwork sequential of chip, and circuit enters reseting stage, and in the t2 stage, RST is high level, and circuit starts normal work.Line period (odd-numbered line, a 1T
hS) inside counting device module count down to 1023 from 0, the control signal outputting to DAC is 0000000000-1111111111.DAC output voltage RAMPV is from 0 to 5V, more next line period (even number line) inside counting device module count down to 0 from 1023, and the control signal outputting to DAC is 1111111111-0000000000.DAC output voltage RAMPV is from 5 to 0V.DAC output voltage is changed to: 0V increases to 5V gradually and is reduced to 0V gradually again, not charging immediately or electric discharge, thus decreases the requirement to DAC driving force, reduces power consumption simultaneously.
Wherein the column selection control mode of odd-numbered line is: the gating time of column selection signal is the 10 digital video data-signals that counter data is less than or equal to this row latch, and the column selection control mode of even number line is: the gating time of column selection signal is the 10 digital video data-signals that counter data is greater than this row latch.Comparative result determines gating time size, in a line time, M/2 odd column comparer and M/2 even column comparer are transferred to odd column switch and even column switch comparative result by level shift simultaneously, make corresponding RAMPV voltage transmission in M row pixel cell.
Fig. 3 is pixel cell signal of the present invention write embodiment, and when the first row Q row comparator output signal COMP1 is effective, COMP1 controls odd column column selection switch conduction by odd number level shift circuit, and 10 DAC export and output to pixel cell through BUFFER1.When row selects signal HS1 effective, switching tube MP1 conducting, the corresponding voltage of RAMPV passes in electric capacity C1, and driving tube MN1 produces drive current makes OLED1 luminous.When second row Q row comparator output signal COMP2 is effective, COMP2 controls odd column column selection switch conduction by odd number level shift circuit, and 10 DAC export and output to pixel cell through BUFFER1.When row selects signal HS2 effective, switching tube MP2 conducting, the corresponding voltage of RAMPV passes in electric capacity C2, and driving tube MN2 produces drive current makes OLED2 luminous.
As shown in Figure 3 (b), during the first row, the gating time of column selection signal is the 10 digital video data-signals that counter data is less than or equal to this row latch, the column selection messenger that the first row Q row comparer exports is COMP1, gating time is t1, be less than or equal to the time of 10 digital video data-signal Data<9:0> of this row latch for counter data Counter<9:0>, when gating time t1, corresponding RAMPV voltage V1 is transferred in Q row pixel cell.During the second row, the gating time of column selection signal is the 10 digital video data-signals that counter data is greater than this row latch, the column selection messenger that Q row comparer exports is COMP2, gating time is t2, be greater than the time of 10 digital video data-signal Data<9:0> of this row latch for counter data Counter<9:0>, when gating time t2, corresponding RAMPV voltage V1 is transferred in Q row pixel cell.
The present invention is not limited to above-mentioned embodiment, every employing counter module count down to 1023 again to 0 from 0, cycle count, the gating time of the column selection signal of odd-numbered line is the 10 digital video data-signals that counter data is less than or equal to this row latch, and the gating time of the column selection signal of even number line is the 10 digital video data-signals that counter data is greater than this row latch.Comparative result determines gating time size, and controls the structure of column selection switch realization to pel array discharge and recharge by comparer, all should drop within scope.
The part that the present invention does not relate to prior art that maybe can adopt same as the prior art is realized.
Claims (10)
1. the micro-display drive control circuit of novel silicon base OLED, it comprises odd column shift register, odd column latch, odd column comparer, odd column level shift, odd number column selection switch module, even column shift register, latch, even column comparer, even column level shift, even number column selection switch module, even column row cutting module, DAC module basic counter module, is characterized in that input signal clock signal PCLK and the 10 digital video signal datas respectively of described odd column shift register module; The output terminal of odd column shift register is connected with the input end of odd column latch, another input end connected row synchronizing signal HS of odd column latch, the output of odd column latch connects the input of odd column comparer, the output of odd column comparer connects the input of odd column level shift, the output of odd column level shift connects odd column switch, and odd column switch exports and connects OLED array odd column pixel; Input signal clock signal PCLK and the 10 digital video signal datas respectively of even column shift register module; The output terminal of even column shift register is connected with the input end of even column latch, another input end connected row synchronizing signal HS of even column latch, the output of even column latch connects the input of even column comparer, the output of even column comparer connects the input of even column level shift, the output of even column level shift connects even column switch, and even column switch exports and connects OLED array even column pixels; The input of counter meets line synchronizing signal HS, pixel clock PCLK, reset signal RST, the output of counter meets odd column comparer, even column comparer, 10 DAC, 10 DAC export and meet BUFFER1 and BUFFER2, the input of row cutting module meets line synchronizing signal HS, frame synchronizing signal VS, row cutting module exports and connects level shift, and level shift exports and connects OLED array.
2. control circuit according to claim 1, it is characterized in that the form that described odd column shift register and even column shift register all adopt M/2 d type flip flop connected in series, receive the viewdata signal of 10 respectively, export as M/2 10 bit data parallel outputs.
3. control circuit according to claim 1, it is characterized in that described odd column latch and even column latch input signal correspond to odd column shift register and even column shift register output signal, clock input signal is line scanning synchronizing signal HS.
4. control circuit according to claim 1, it is characterized in that described odd column comparer and even column comparer comprise M/2 comparator unit respectively, input signal is the output signal of odd column latch and even column Latch output signal sum counter respectively;
Compared with 10 signals that the viewdata signal of 10 and counter export by comparator module, comparative result outputs to electrical level shift units.
5. control circuit according to claim 1, is characterized in that described odd column level shift and even column level shift comprise M/2 electrical level shift units respectively, and odd column comparer and even column comparer Output rusults level are converted to 5V from 1.8V.
6. control circuit according to claim 1, is characterized in that described odd number column selection switch and even number column selection switch module comprise M/2 column selection switch element respectively.
7. control circuit according to claim 1, is characterized in that described line-scan circuit comprises the d type flip flop of N number of serially concatenated; Previous d type flip flop exports the next d type flip flop input end of termination, and first d type flip flop input signal comprises line synchronizing signal HS, frame synchronizing signal VS.
8. control circuit according to claim 1, it is characterized in that described odd column shift register, odd column latch, odd column comparer, odd column level shift and odd number column selection switch module composition odd column Drive and Control Circuit, this odd column Drive and Control Circuit is made up of 10 DAC, BUFFER1, odd number column selection switch and odd column level shift, and the DAC analog voltage that it exports is for driving pixel cell 1 and pixel cell 2; Wherein 10 DAC export and connect odd number column selection switch through BUFFER1, and odd column level shift is input as COMP1 and COMP2, and odd column level shift output signal controls odd number column selection switch, the drain electrode of P type metal-oxide-semiconductor MP1 and the output of odd column switch, electric capacity C
pone end is connected, and the source electrode of P type metal-oxide-semiconductor MP1 is connected with the grid of one end of electric capacity C1, N-type metal-oxide-semiconductor MN1, and the grid of P type metal-oxide-semiconductor MP1 selects control signal HS1 to be connected with row, electric capacity C2, electric capacity C
pthe other end be connected with ground GND, the drain electrode of N-type metal-oxide-semiconductor MN1 is connected with voltage VDD, the source electrode of N-type metal-oxide-semiconductor MN1 is connected with the source electrode of P type metal-oxide-semiconductor MP1_2, the drain electrode of P type metal-oxide-semiconductor MP1_2 is connected with OLED anode, the grid of P type metal-oxide-semiconductor MP1_2 is connected with ground GND, and the negative electrode of OLED is connected with Vcom voltage.
9. the driving method of a novel silica-based OLED micro display chip, it is characterized in that first, make chip shift register from the viewdata signal of external control accepts 10, triggered by the pixel shift rising edge clock of shift register, viewdata signal is shifted from one end of shift register to the other end successively, complete all be shifted time, line synchronizing signal arrive; Secondly, latch when line synchronizing signal arrives, is deposited with whole for the data in shift register input latch in latch; 3rd, counter module count down to 1023 again to 0 from 0, and the output voltage of 10 DAC is corresponding with counter output signal, first rises to ceiling voltage from minimum voltage, then drops to minimum voltage successively from ceiling voltage, circulate successively; 4th, make the Simultaneous Transmission of Data of odd column and even column, wherein the column selection control mode of odd-numbered line is: the gating time of column selection signal is the time that counter data is less than or equal to 10 digital video data-signals of this row latch; The column selection control mode of even number line is: the gating time of column selection signal is the time that counter data is greater than this row latch 10 digital video data-signal.
10. method according to claim 1, it is characterized in that described shift register is divided into upper and lower two parts, odd column shift register receives odd column data above, below even column shift register receive even column data, odd column and even column work simultaneously.
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| CN106652959A (en) * | 2017-01-20 | 2017-05-10 | 中国电子科技集团公司第五十五研究所 | Silicon-based microdisplay column selection drive method and circuit suitable for high-frequency applications |
| CN108766333B (en) * | 2018-04-17 | 2022-09-09 | 昀光微电子（上海）有限公司 | Improved silicon-based micro display and driving circuit thereof |
| CN108766333A (en) * | 2018-04-17 | 2018-11-06 | 昀光微电子（上海）有限公司 | A kind of improved silicon-base miniature display and its driving circuit |
| CN109686335A (en) * | 2019-02-19 | 2019-04-26 | 京东方科技集团股份有限公司 | A kind of sequential control method, sequence controller and display device |
| CN109686335B (en) * | 2019-02-19 | 2021-04-27 | 京东方科技集团股份有限公司 | Time sequence control method, time sequence controller and display device |
| CN109872686A (en) * | 2019-04-19 | 2019-06-11 | 京东方科技集团股份有限公司 | A kind of production method of driving circuit, display panel and display panel |
| CN109872686B (en) * | 2019-04-19 | 2020-05-29 | 京东方科技集团股份有限公司 | Drive circuit, display panel and manufacturing method of display panel |
| CN111402786A (en) * | 2020-04-03 | 2020-07-10 | 中国科学院微电子研究所 | Display device and method of driving the same |
| CN114141202A (en) * | 2021-12-03 | 2022-03-04 | 湖畔光电科技（江苏）有限公司 | Micro-display active pixel circuit |
| CN114141202B (en) * | 2021-12-03 | 2024-03-15 | 湖畔光电科技（江苏）有限公司 | Micro-display active pixel circuit |
| CN114205581A (en) * | 2021-12-14 | 2022-03-18 | 南京国兆光电科技有限公司 | Time sequence design method for improving calibration precision of silicon-based OLED micro-display assembly |
| CN115775535A (en) * | 2022-11-30 | 2023-03-10 | 南京国兆光电科技有限公司 | Display driving circuit |
| CN115775535B (en) * | 2022-11-30 | 2023-10-03 | 南京国兆光电科技有限公司 | Display driving circuit |
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Effective date of registration: 20190412 Address after: 211100 Room 202, Zhongguancun Software Park, No. 7 Yingcui Road, Jiangning Development Zone, Nanjing City, Jiangsu Province Patentee after: Nanjing Guozhao Photoelectric Technology Co., Ltd. Address before: 210016 No. 524 Zhongshan East Road, Nanjing, Jiangsu Province Patentee before: No.55 Inst., China Electronic Science and Technology Group Corp. |