CN106649894A - Method for quickly generating device array in integrated circuit layout - Google Patents
Method for quickly generating device array in integrated circuit layout Download PDFInfo
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- CN106649894A CN106649894A CN201510708846.5A CN201510708846A CN106649894A CN 106649894 A CN106649894 A CN 106649894A CN 201510708846 A CN201510708846 A CN 201510708846A CN 106649894 A CN106649894 A CN 106649894A
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- device array
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- spacing
- devices
- integrated circuit
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Abstract
The invention discloses a method for quickly generating a device array in an integrated circuit layout. The device array with a specified spacing can be quickly and effectively generated in a graphic region according to graphs and devices selected by a user. In the whole process, the user can finish the creation of the device array only by specifying a deviation value, to-be-generated devices, a spacing between every two adjacent devices in X-axis and Y-axis directions, and a ratio of an area of an overlapped part of the devices and the graphic region to a device area. An automatic device generation method can greatly reduce the workload of the user and effectively avoid the dislocation problem caused by manual operation of the user, so that the layout design efficiency is improved.
Description
Technical field
In IC Layout, device array is quickly generated for the convenience of the user, improve the work efficiency of user, present invention achieves a kind of method that the device array for specifying Spacing is quickly generated in assignment graph.The invention belongs to layout design field in eda tool.
Background technology
Layout design is mostly important, the most key step in IC design, directly decides the success or failure of whole chip design.During IC Layout, need to generate in a specified area the device array for specifying Spacing.Now, the device arrangements of generation can not only be increased in specified figure by manual operations the workload of layout design, and is easily caused the problem of dislocation.
A kind of method for quickly generating device array that the present invention is realized, the figure selected according to user and device, fast and effeciently can generate the device array for specifying Spacing in the graphics field.The method can not only substantially reduce the workload of user, while can also be prevented effectively from the problem of misalignment that user's manual operations brings, improve the efficiency of layout design.
The content of the invention
The present invention proposes a kind of graphics field that basis is specified in IC Layout, the method that the device array for specifying Spacing fast and effeciently is generated in the graphics field.
Basic thought：According to the X-axis and the deviant of Y direction of the central point and user input of selected figure, datum mark during device generation is calculated.With the datum mark as origin, according to the device of user's selection and its in X-axis and the spacing of Y direction, uniform grid is divided with the boundary rectangle of selected graphics field and device to be filled and its pitch value, each grid is initialized as placing an inst that (inst is the example of a design cell）, then according to judging whether each grid is included by graphics field successively, if be not chosen figure contained, put current grid and cannot place an inst.If current grid is chosen visuals included, judge whether inclusion region meets the requirement of area accounting, be unsatisfactory for, then put current grid and cannot place an inst.After all grids determine whether to place inst, from one arrayInst of maximum subarray establishment that can continuously place inst is wherein found out, (arrayInst is to represent one group of inst using an object；This group of inst is two-dimentional, can have multiple lines and multiple rows, so represents and can facilitate user's subsequent editing operations）, and current these grids for having created arrayInst are set to cannot create inst, continue recurrence and find out maximum subarray to create arrayInst, till all grids that can produce inst are disposed.Meet area accounting and require to refer to the percentage ratio whether threshold values specified more than user of current grid region and visuals overlapping region divided by current grid region, meet more than or equal to then representing, less than then foot with thumb down.The deviant of specified X-axis and Y direction, the arrangement that user can be to device in graphics field are adjusted.
In whole process, need to only specify Offsets value, device to be generated, adjacent devices of user complete the establishment of device array by the ratio of the spacing and overlapping region of X-axis and Y direction, the huge time cost that Layout Design Engineer is spent in arranging devices can be greatly saved in this simple and effective realization, effectively accelerate layout design.
Description of the drawings
Fig. 1 most basic options are arranged
Fig. 2 is wide, high be respectively generating device array of figure on the ellipse of 300 * 400
Fig. 3
Internal diameter is generating device array of figure on donut that 360, external diameter is 380
Generating device array of figure on Fig. 4 width, the high respectively E shape polygons of 270*400
Oval upper generating device array of figure when Fig. 5 X-directions spacing is 5u, Y-direction spacing is 10u
Specific implementation step：
With reference to a practical operation to illustrate implementation steps, concrete operations flow process is as follows：
1）The figure for selecting device to be placed, the device for needing generation, the area accounting of lap, and device to be generated is specified in X-axis, the spacing of Y direction and its deviant；
2）According to selecting the boundary rectangle of graphics field to divide uniform grid with device to be filled and its spacing and deviant, each sizing grid is initialized as placing an inst.Required according to specified area accounting, determine that can grid place inst；
3）Find out from all grids and can continuously place the maximum subarray of inst and create an arrayInst, and these grids are set to cannot create inst；
Continue step 3）, until all grids that can produce inst are disposed.Now, all grids are set to create inst, complete automatically generating for device array.
Claims (1)
1. a kind of method that device array is quickly generated during IC Layout, its feature are as follows:
（1）According to the boundary rectangle and device to be filled that select graphics field, according to maximum subarray principle, device array is created on the graphics field；
（2）During device array is automatically generated, user with self-defined device and the area accounting of graphics field lap, and can support the graphics field of arbitrary shape；
（3）During device array is automatically generated, user can be with the spacing between self-defined device；
（4）During device array is automatically generated, user can arrange deviant and device array is finely adjusted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510708846.5A CN106649894A (en) | 2015-10-28 | 2015-10-28 | Method for quickly generating device array in integrated circuit layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510708846.5A CN106649894A (en) | 2015-10-28 | 2015-10-28 | Method for quickly generating device array in integrated circuit layout |
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| Publication Number | Publication Date |
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| CN106649894A true CN106649894A (en) | 2017-05-10 |
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| CN201510708846.5A Pending CN106649894A (en) | 2015-10-28 | 2015-10-28 | Method for quickly generating device array in integrated circuit layout |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109033545A (en) * | 2018-07-03 | 2018-12-18 | 北京华大九天软件有限公司 | A method of pixel domain is quickly generated according to the definition of pixel array |
| CN109670253A (en) * | 2018-12-26 | 2019-04-23 | 北京华大九天软件有限公司 | Two kinds of objects random equally distributed method in specified rectangular area |
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| US20110072407A1 (en) * | 2009-09-18 | 2011-03-24 | International Business Machines Corporation | Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design |
| CN102402633A (en) * | 2010-09-17 | 2012-04-04 | 中国科学院微电子研究所 | Method for establishing parameterized device physics territory unit generating program |
| US8201127B1 (en) * | 2008-11-18 | 2012-06-12 | Xilinx, Inc. | Method and apparatus for reducing clock signal power consumption within an integrated circuit |
| CN102831268A (en) * | 2012-08-16 | 2012-12-19 | 复旦大学 | Fast generating method of user-customizable PLD (programmable logic device) layouts |
| CN103034742A (en) * | 2011-09-30 | 2013-04-10 | 北京华大九天软件有限公司 | Method for generating devices rapidly |
| CN103366055A (en) * | 2013-06-28 | 2013-10-23 | 杭州广立微电子有限公司 | Method for generating addressable test chip layout |
| CN103970946A (en) * | 2014-04-30 | 2014-08-06 | 上海华力微电子有限公司 | Test structure and layout generating method thereof |
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2015
- 2015-10-28 CN CN201510708846.5A patent/CN106649894A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6957406B1 (en) * | 2001-11-28 | 2005-10-18 | Xilinx, Inc. | Analytical placement methods with minimum preplaced components |
| US8201127B1 (en) * | 2008-11-18 | 2012-06-12 | Xilinx, Inc. | Method and apparatus for reducing clock signal power consumption within an integrated circuit |
| US20100287519A1 (en) * | 2009-05-11 | 2010-11-11 | Anaglobe Technology, Inc. | Method and system for constructing a customized layout figure group |
| US20110072407A1 (en) * | 2009-09-18 | 2011-03-24 | International Business Machines Corporation | Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design |
| CN102402633A (en) * | 2010-09-17 | 2012-04-04 | 中国科学院微电子研究所 | Method for establishing parameterized device physics territory unit generating program |
| CN103034742A (en) * | 2011-09-30 | 2013-04-10 | 北京华大九天软件有限公司 | Method for generating devices rapidly |
| CN102831268A (en) * | 2012-08-16 | 2012-12-19 | 复旦大学 | Fast generating method of user-customizable PLD (programmable logic device) layouts |
| CN103366055A (en) * | 2013-06-28 | 2013-10-23 | 杭州广立微电子有限公司 | Method for generating addressable test chip layout |
| CN103970946A (en) * | 2014-04-30 | 2014-08-06 | 上海华力微电子有限公司 | Test structure and layout generating method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109033545A (en) * | 2018-07-03 | 2018-12-18 | 北京华大九天软件有限公司 | A method of pixel domain is quickly generated according to the definition of pixel array |
| CN109670253A (en) * | 2018-12-26 | 2019-04-23 | 北京华大九天软件有限公司 | Two kinds of objects random equally distributed method in specified rectangular area |
| CN109670253B (en) * | 2018-12-26 | 2020-09-11 | 北京华大九天软件有限公司 | Method for randomly and uniformly distributing two objects in specified rectangular area |
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Application publication date: 20170510 |