CN106649021B - PCIe is from equipment testing device - Google Patents
PCIe is from equipment testing device Download PDFInfo
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- CN106649021B CN106649021B CN201611061914.4A CN201611061914A CN106649021B CN 106649021 B CN106649021 B CN 106649021B CN 201611061914 A CN201611061914 A CN 201611061914A CN 106649021 B CN106649021 B CN 106649021B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
- G06F2211/002—Bus
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- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a kind of PCIe from equipment testing device, wherein includes: PCIe-IP core, for being converted to the physical signal of PCIe route for the output data packet of PCIE transaction layer data message module；The link state of PCIe-IP core is sent to processor by link state monitoring module；PCIE transaction layer data message processing module, for being unpacked the data packet of PCIe-IP core and being sent to equipment under test behavior monitoring module；Normally whether equipment under test behavior monitoring module judge in equipment under test returned data packet, and judging result be sent to processor；Test and excitation editor module generates corresponding test data, is sent to PCIE transaction layer data message processing module for the test instruction according to processor；Processor is exported for generating corresponding order, and the data packet returned according to equipment under test according to user instructions to user.
Description
Technical field
The present invention relates to a kind of computer testing device, in particular to a kind of PCIe is from equipment testing device.
Background technique
The present invention relates to a kind of PCIe board (PCIe from equipment) device for testing functions, are mainly used for using in computer
Autonomous Design PCIe board function test.
PCIe bus is a kind of local bus of the large-scale application in all kinds of computers at present.As connection Cache and
The extension of the system bus of main memory, playing major function is connection external equipment.The form of plate is used in general computer,
Plate and mainboard realize the extension to computer function by PCIe bus bar.After the completion of PCIe patch panel design, usually to it
The method of test is directly to be inserted into destination host, writes special software driver and test program for design function
Its function is tested.
When the PCIe board function used in the computer is various, if tested using conventional method it, have
Biggish limitation: due to the limitation of team's manpower and material resources factor, when PCIe patch panel design is completed, target cabinet, driving are soft
Part is not possible in place timely and effectively to be tested its function, this will drag slow development of projects significantly；In addition, certain situations
Under, it needs to carry out Maintenance and Repair to board at the scene, it is negative that bulky cabinet also brings biggish work to board maintenance personnel
Load.
Summary of the invention
The purpose of the present invention is to provide a kind of PCIe from equipment testing device, for solving asking for the above-mentioned prior art
Topic.
A kind of PCIe of the present invention is from equipment testing device, wherein includes: testing and control mainboard and interface conversion bottom plate；It surveys
Trying control mainboard includes: test and excitation editor module, equipment under test behavior monitoring module, embedded microprocessor, PCIe things
Layer data message processing module (MPM), PCIe-IP core and link state monitoring module；Interface conversion bottom plate includes: multiple testing and controls
Host slot and therewith one-to-one multiple equipment under test slots；Multiple testing and control host slots are used for and testing and control master
Plate connection；Multiple equipment under test slots are for connecting equipment under test；PCIe-IP core is used for PCIE transaction layer data message mould
The output data packet of block is converted to the physical signal of PCIe route, and the physical signal of PCIe route is converted to data packet
Input to PCIE transaction layer data message module；The link state of PCIe-IP core is sent to processing by link state monitoring module
Device, the request to link operation of processor, is transmitted to PCIe-IP core；PCIE transaction layer data message processing module, being used for will
The data packet of PCIe-IP core is unpacked and is sent to equipment under test behavior monitoring module, and by test and excitation editor module
Output data be packaged, be sent to PCIe-IP core；Equipment under test behavior monitoring module, judges equipment under test returned data
It is whether normal in packet, and judging result is sent to processor；Test and excitation editor module, for referring to according to the test of processor
It enables, generates corresponding test data, be sent to PCIE transaction layer data message processing module；Processor, for being referred to according to user
It enables and generates corresponding order, and the data packet returned according to equipment under test, export to user.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein multiple equipment under test slots have not
With link width and interface form.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein link state include link on-off,
Width and speed.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein test and excitation editor module tested is set
Standby behavior monitoring module, embedded microprocessor, PCIe transaction layer data message processing module, PCIe-IP core and link state
Monitoring module is realized by FPGA.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein interface conversion bottom plate further includes test
The power supply module of control mainboard and equipment under test, power reset management module and the clock driving mould according to PCIe specification design
Block.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein testing and control mainboard further include: user
Interactive interface control module is connected for testing and control mainboard and the external equipment of user.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein further include: display module connects embedding
Enter microsever, for showing the output result of embedded microprocessor.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein key operation module connects embedded
Microprocessor, for the operational order of user to be inputed to embedded microprocessor.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein PCIe-IP caryogamy is set to RC-Port.
An embodiment of the PCIe according to the present invention from equipment testing device, wherein testing and control mainboard further include: PCIe
Connector, for being connect with host slot.
To sum up, PCIe of the invention is from equipment testing device, using with the port PCIe RootComplex (RC-Port)
The FPGA of IP kernel carries out the device of functional test to realize to the board of autonomous Design, is able to ascend convenience, improves team
Working efficiency.
Detailed description of the invention
Fig. 1 show a kind of schematic diagram of the PCIe of the present invention from equipment testing device.
Specific embodiment
To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to of the invention
Specific embodiment is described in further detail.
Fig. 1 show a kind of schematic diagram of the PCIe of the present invention from equipment testing device, as shown in Figure 1, PCIe of the present invention from
Equipment testing device includes: testing and control mainboard 20 and interface conversion bottom plate 21.Testing and control mainboard 20 includes: FPGA system
19, user input interface, output display interface and PCIe connector 10.FPGA system 19 is by fpga chip and can guarantee FPGA
The minimum system of normal work forms, and fpga chip inner function module includes: test and excitation editor module 1, equipment under test row
For monitoring module 2, embedded microprocessor IP kernel 3, user's interactive interface control module 4, PCIe transaction layer data message (TLP)
Processing module 7, PCIe IP kernel 8 and link state monitoring module 9.Interface conversion bottom plate 21 includes: power supply and reset management module
14, PCIe clock management module 18, testing and control host slot 11-13 and therewith correspondingly have different link widths and
The equipment under test slot 15-17 of interface form.
As shown in Figure 1, being provided with power supply module, the electricity of testing and control mainboard 20 and equipment under test on interface conversion bottom plate 21
The timepiece drive module 18 that source resets management module 14 and designs according to PCIe specification.In view of the physical signal of PCIe bus is
High speed serial differential signal, in order to ensure the quality of signal transmission, on interface conversion bottom plate 21, for different link widths, no
Independent slot 15-17 is arranged in equipment under test with interface form, and each equipment under test slot 15-17 independently corresponds to a survey
Try control mainboard slot 11-13.The purpose for the arrangement is that the high speed signal on wiring board is avoided branch occur, signal transmission is influenced
Quality.
As shown in Figure 1, the function of testing and control mainboard 20 is mainly completed by a piece of fpga chip.Fpga chip needs to have
PCIe bus IP Core 8, and this IP kernel is configurable to RC-Port.In addition, the capacity of FPGA will also can satisfy application
It needs: supporting the logic of soft/hard IP kernel of embeded processor and data processing section.
As shown in Figure 1, PCIE connector 10 is for being inserted into corresponding host slot 11-13.Equipment under test insertion corresponds to
Equipment under test slot 15-17 in.
As shown in Figure 1, the output data packet of TLP module 7 is converted to PCIe route by PCIe-IP core 8 (RC mode)
Physical signal, and the physical signal of PCIe route is converted into data packet and inputs to TLP module 7.
As shown in Figure 1, link state monitoring module 9, is used for the link state (shapes such as on-off, width, speed of link
State) information is sent to link state monitoring module 9, when needing to change link state, such as speed, by PCIe-IP nuclear alteration and quilt
Link-speeds between measurement equipment.
The link state of PCIe-IP core 8 is sent to embedded microprocessor IP kernel 3 by link state monitoring module 9, embedding
The request to link operation for entering microsever IP kernel 3, is transmitted to PCIe-IP core 8.TLP processing module 7, by PCIe-IP core
8 data packet carry out unpack is sent to equipment under test behavior monitoring module 2, by the output data of test and excitation editor module 1 into
Row is packaged, and is sent to PCIe-IP core 8；Just whether equipment under test behavior monitoring module 2 judge in equipment under test returned data packet
Often, and by judging result it is sent to embedded microprocessor IP kernel 3, to be presented to the user；Test and excitation editor module 1, is used for
It is instructed according to the test of embedded microprocessor IP kernel 3, generates corresponding test data and be sent to TLP processing module 7；It is embedded
User instruction is generated corresponding order, and the data packet returned according to equipment under test, to be presented to use by microprocessor IP kernel 3
Family.User's interactive interface control module 4, for being interacted with key toggle switch 5 and LED light display screen 6.Key dial-up
Switch 5 is used for user input instruction.LED light display screen 6 is for showing equipment under test testing result and link-state information
Show to user.
As shown in Figure 1, PCIe-IP core 8 and PCIe connector 10 is connected directly in FPGA system, it is responsible for receiving PCIe electricity
Gas signal carries out the processing of physical layer and data link layer, then will receive TLP and be transferred to using logic；Application is received to patrol
The TLP editted is collected, then processing, packing by data link layer and physical layer are sent to tested set by PCIe bus
It is standby.PCIeIP core 8 also there is physical layer state to monitor and control interface, and the link state that can monitor physical layer sends behaviour to
Make user, or initiates the movement of change link width, link-speeds by operation user.TLP processing module 7 is responsible for receiving test
Excitation, and packaged data are required according to 8 interface protocol of PCIe IP kernel, test and excitation is sent, and receive number from PCIe IP kernel 8
According to protocol analysis is carried out, the data that equipment under test is sent are obtained, send equipment under test behavior monitoring module 2 to.Insertion declines
Processor IP nuclear 3 is responsible for the management and scheduling feature of system entirety: from user's interactive interface control module 4, obtaining user's input
Test and excitation attribute, by test and excitation attribute send to test and excitation editor module 1 carry out test and excitation；From equipment under test row
The data that equipment under test is sent are obtained for monitoring module 2, current link conditions information is obtained from link state monitoring module 9, leads to
It crosses user's interactive interface control module 4 and is shown to user.
As shown in Figure 1, PCIe can quickly survey PCIe from the basic function of equipment plate card from equipment testing device
Examination.The content tested equipment under test mainly has the following aspects: whether link can work normally, and the space BAR is read
It writes, interrupt signal is monitored, DMA transfer test.
As shown in Figure 1, after testing and control mainboard and equipment under test are powered on, resetted by interface conversion bottom plate 21,
Under normal circumstances, PCIe link training and initialization are carried out first, and after the completion of work, PCIe link terminal device can be normal
Work.This process can be obtained by the interface that link state monitoring module 9 monitors PCIe IP kernel 8.Monitored results are shown to behaviour
Make user, user can learn whether link training and initialization procedure successfully complete, and if the completion that fails, at which
Link there is a problem.
As shown in Figure 1, the read-write of the space BAR is the most basic function that PCIe device needs support.After the completion of link initialization,
User can the space carry out BAR readwrite tests to equipment under test.User firstly the need of editor need be written and read address, to
The test and excitations attributes such as the data of write-in, data number to be written, after starting test, FPGA system 19 will by PCIe IP kernel 8
Test and excitation is sent to equipment under test, is written and read to the space BAR of equipment under test.Certain form of read and write access, such as
The space Memory is read, and the operations such as input/output space reading and writing need equipment under test to return to completion message.Equipment under test behavior monitoring module 2
It is responsible for receiving these completion messages, and judges that these complete whether messages meet expection, such as whether returns expected correct negative
Carry, load number of words whether with number of words specified in packet header always etc., result be presented to user.
As shown in Figure 1, certain equipment under tests support interrupt function and DMA transfer function.Interrupt function and DMA function quintessence
On be all by equipment under test as transmission promoter, actively to link opposite end send message.When test, it is necessary first to empty with BAR
Between the mode read and write, edit test and excitation, equipment under test correctly configured, trigger the interruption of equipment under test or start quilt
Measurement equipment carries out DMA transfer.Then, equipment under test behavior monitoring module 2 monitors the message of equipment under test transmission, judgement receives
Whether interrupt message message or DMA read-write message hold water, and if whether message format is correct, interrupts and number whether correct, DMA
Access result be presented to user with the presence or absence of address out of range mistake etc., and untreated its module editor is notified to complete as required
Message returns to equipment under test to complete to communicate.
As shown in Figure 1, this PCIe is divided into testing and control mainboard 20 and interface conversion bottom plate 21 two from equipment testing device
Point.Interface conversion bottom plate 21 is used to provide installation's power source, reset function and reference clock, and to different link widths, difference
The equipment under test of interface form is adapted to.In testing and control mainboard 20, realized and equipment under test PCIe port by PCIe IP kernel
Connection and communication；Editor's parsing and the interface status monitor of data packet are realized by the general logic part in FPGA；FPGA
It is middle to realize that the management to test function entirety controls using embedded microprocessor IP kernel, and the control of user interface is come and behaviour
Make the interaction of user, receives the test and excitation attribute of operation user's input, and test result is shown to operation user.
PCIe of the present invention is from the PCIe of equipment testing device autonomous Design in Mr. Yu's model computer from equipment plate card function
It can test.Test function is controlled by operation user by key-press input, while can be passed through test result and operation interface aobvious
Display screen is presented to operation user.The use of PCIe IP kernel and embedded microprocessor IP kernel in FPGA integrates complicated function
In a piece of chip, improve level of integrated system, eliminate bulky cabinet and miscellaneous protocol chip, accomplished it is low at
Sheet and miniaturization, the operator that is more suitable is portable, is quickly and effectively tested from equipment PCIe whenever and wherever possible, Neng Gouyou
Effect ground promotes the working efficiency of team.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of PCIE is from equipment testing device characterized by comprising testing and control mainboard and interface conversion bottom plate；Test
Control mainboard includes: test and excitation editor module, equipment under test behavior monitoring module, embedded microprocessor, PCIE transaction layer
Data message processing module, PCIE-IP core and link state monitoring module；Interface conversion bottom plate includes: multiple testing and control masters
Plate slot and therewith one-to-one multiple equipment under test slots；
Multiple testing and control host slots with testing and control mainboard for connecting；
Multiple equipment under test slots are for connecting equipment under test；
PCIE-IP core, for being converted to the object of PCIE route for the output data packet of PCIE transaction layer data message processing module
Signal is managed, and the physical signal of PCIE route is converted into data packet and inputs to PCIE transaction layer data message processing module；
The link state of PCIE-IP core is sent to processor by link state monitoring module, by processor to link operation
Request is transmitted to PCIE-IP core；
PCIE transaction layer data message processing module, for the data packet of PCIE-IP core to be unpacked to and is sent to tested set
Standby behavior monitoring module, and the output data of test and excitation editor module is packaged, it is sent to PCIE-IP core；
Normally whether equipment under test behavior monitoring module judge in equipment under test returned data packet, and judging result be sent to
Processor；
Test and excitation editor module generates corresponding test data, is sent to PCIE thing for the test instruction according to processor
Nitride layer data message processing module；
Processor, for generating order accordingly, and the data packet returned according to equipment under test according to user instructions, output is to use
Family.
2. PCIE as described in claim 1 is from equipment testing device, which is characterized in that multiple equipment under test slots have difference
Link width and interface form.
3. PCIE as described in claim 1 is from equipment testing device, which is characterized in that link state include link on-off,
Width and speed.
4. PCIE as described in claim 1 is from equipment testing device, which is characterized in that test and excitation editor module tested is set
Standby behavior monitoring module, embedded microprocessor, PCIE transaction layer data message processing module, PCIE-IP core and link state
Monitoring module is realized by FPGA.
5. PCIE as described in claim 1 is from equipment testing device, which is characterized in that interface conversion bottom plate further includes test control
Power supply module, power reset management module and the timepiece drive module according to PCIE Specification Design of mainboard and equipment under test processed.
6. PCIE as described in claim 1 is from equipment testing device, which is characterized in that testing and control mainboard further include: user
Interactive interface control module is connected for testing and control mainboard and the external equipment of user.
7. PCIE as described in claim 1 is from equipment testing device, which is characterized in that further include: display module, connection insertion
Microsever, for showing the output result of embedded microprocessor.
8. PCIE as described in claim 1 is from equipment testing device, which is characterized in that key operation module connects embedded
Microprocessor, for the operational order of user to be inputed to embedded microprocessor.
9. PCIE as described in claim 1 is from equipment testing device, it is characterised in that PCIE-IP caryogamy is set to RC-Port.
10. PCIE as described in claim 1 is from equipment testing device, which is characterized in that testing and control mainboard further include: PCIE
Connector, for being connect with host slot.
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| CN201611061914.4A CN106649021B (en) | 2016-11-25 | 2016-11-25 | PCIe is from equipment testing device |
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| CN201611061914.4A CN106649021B (en) | 2016-11-25 | 2016-11-25 | PCIe is from equipment testing device |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109116829B (en) * | 2018-06-27 | 2019-07-23 | 苏州华兴源创科技股份有限公司 | The triggering implementation method and automatic test equipment of automatic test equipment |
| CN109446015B (en) * | 2018-10-26 | 2022-05-27 | 北京计算机技术及应用研究所 | NVMe prototype simulation verification structure |
| CN109710473A (en) * | 2018-12-19 | 2019-05-03 | 四川虹美智能科技有限公司 | A kind of SOC board measuring method, apparatus and system |
| CN110018923A (en) * | 2019-05-17 | 2019-07-16 | 宁波万德高科智能科技有限公司 | Safe-guard system towards industrial Internet of Things edge calculations server |
| JP7324637B2 (en) * | 2019-07-23 | 2023-08-10 | 株式会社Pfu | Computer device and restart method |
| CN112506728B (en) * | 2021-02-04 | 2021-06-04 | 上海国微思尔芯技术股份有限公司 | Test method and device for prototype verification system |
| CN114003450B (en) * | 2021-10-25 | 2024-01-12 | 苏州浪潮智能科技有限公司 | Test fixture, test method and computer equipment for automatically switching PCIE links |
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| CN102866948A (en) * | 2012-08-30 | 2013-01-09 | 中国人民解放军63928部队 | Testing platform and testing method for embedded basic software |
| CN103530211A (en) * | 2013-10-12 | 2014-01-22 | 江苏华丽网络工程有限公司 | PCIE loop back self-test method based on UVM platform |
| CN103530216A (en) * | 2013-10-12 | 2014-01-22 | 江苏华丽网络工程有限公司 | PCIE verification method based on UVM |
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| US8718967B2 (en) * | 2010-05-28 | 2014-05-06 | Advantest Corporation | Flexible storage interface tester with variable parallelism and firmware upgradeability |
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| CN102866948A (en) * | 2012-08-30 | 2013-01-09 | 中国人民解放军63928部队 | Testing platform and testing method for embedded basic software |
| CN103530211A (en) * | 2013-10-12 | 2014-01-22 | 江苏华丽网络工程有限公司 | PCIE loop back self-test method based on UVM platform |
| CN103530216A (en) * | 2013-10-12 | 2014-01-22 | 江苏华丽网络工程有限公司 | PCIE verification method based on UVM |
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