CN106646968B - Display substrate, manufacturing method, liquid crystal display panel and liquid crystal display device - Google Patents
Display substrate, manufacturing method, liquid crystal display panel and liquid crystal display device Download PDFInfo
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- CN106646968B CN106646968B CN201611029784.6A CN201611029784A CN106646968B CN 106646968 B CN106646968 B CN 106646968B CN 201611029784 A CN201611029784 A CN 201611029784A CN 106646968 B CN106646968 B CN 106646968B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133357—Planarisation layers
Abstract
The embodiment of the invention discloses a display substrate, a manufacturing method, a display panel and a display device, wherein the display substrate comprises: a display area and a non-display area surrounding the display area; a substrate; the color resistance layer is arranged in the display area; a planarization layer over the color resist layer, the planarization layer extending to the non-display region, wherein the planarization layer in the non-display region includes a first portion and a second portion, the first portion of the planarization layer is located at a greater distance from the display region than the second portion of the planarization layer, and the first portion of the planarization layer has a thickness less than the second portion of the planarization layer; an alignment film over the planarization layer. According to the technical scheme, the accumulation of the fragments of the alignment film at the junction of the display area and the non-display area can be reduced or avoided, and the picture quality and the yield of the liquid crystal display device are improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display substrate, a manufacturing method of the display substrate, a liquid crystal display panel and a liquid crystal display device.
Background
Flat panel displays are widely used for portable displays due to their advantages of lightness and thinness and low power consumption. Among various flat panel displays, liquid crystal display devices have been widely used in computer monitors, notebook computers, and televisions due to their advantages of high definition and picture quality. Therefore, it is popular in the scientific researchers and industry to improve the picture quality and the service life of the liquid crystal display device.
A conventional liquid crystal display device may be composed of two oppositely disposed substrates on which field generating electrodes such as pixel electrodes and a common electrode are formed. A liquid crystal layer may be interposed between two substrates, and a color resist layer is provided on any one of the two substrates. In general, a region of a substrate corresponding to a liquid crystal display device is divided into a display region and a non-display region according to whether or not an image can be displayed in the region. Generally, the color resist layer is only disposed in the display area of the substrate, and the color resist layer is not disposed in the non-display area, so that Ghost dots (Ghost mura) are easily generated at the edge of the color resist layer, that is, at the boundary between the display area and the non-display area, resulting in poor display and seriously affecting the picture quality and the yield of the liquid crystal display device.
Disclosure of Invention
To solve the above problems, the inventors have found that the design in which the non-display region does not have the color resist layer and the display region has the color resist layer results in a step at the boundary between the display region and the non-display region. In rubbing alignment, the step at the boundary of the display region and the non-display region is highly likely to generate accumulation of alignment film debris, thereby generating a peripheral Ghost spot (Ghost mura), resulting in poor display. In view of this, embodiments of the present invention provide a display substrate, a manufacturing method thereof, a liquid crystal display panel and a liquid crystal display device, so as to avoid a phenomenon of poor display and improve picture quality and yield.
In a first aspect, an embodiment of the present invention provides a display substrate, including:
a display area and a non-display area surrounding the display area; a substrate; the color resistance layer is arranged in the display area;
a planarization layer over the color resist layer, the planarization layer extending to the non-display region, wherein the planarization layer in the non-display region includes a first portion and a second portion, the first portion of the planarization layer is located at a greater distance from the display region than the second portion of the planarization layer, and the first portion of the planarization layer has a thickness less than the second portion of the planarization layer;
an alignment film over the planarization layer.
In a second aspect, an embodiment of the present invention further provides a liquid crystal display panel, including:
the liquid crystal display panel comprises a first substrate and a second substrate arranged opposite to the first substrate, wherein a liquid crystal layer is arranged between the first substrate and the second substrate, and the first substrate or the second substrate is any one of the substrates in the first aspect.
In a third aspect, an embodiment of the present invention further provides a liquid crystal display device, including the liquid crystal display panel of the second aspect.
In a fourth aspect, an embodiment of the present invention provides a method for manufacturing a display substrate, including:
providing a substrate;
forming a color resistance layer over the substrate, the color resistance layer being disposed in the display region;
forming a planarization layer over the color resist layer and extending to a non-display region, wherein the planarization layer in the non-display region includes a first portion and a second portion, the first portion of the planarization layer is located at a greater distance from the display region than the second portion of the planarization layer, and the first portion of the planarization layer has a thickness less than the second portion of the planarization layer;
an alignment film is formed over the planarization layer.
According to the invention, the thickness of the first part of the planarization layer, which is far away from the display area, is smaller than the thickness of the second part of the planarization layer, which is close to the display area, so that the first step is formed at the junction of the first part and the second part of the alignment film, and the first step can play a role in accumulating the alignment film scraps.
Drawings
Fig. 1a is a schematic cross-sectional view of a display substrate according to an embodiment of the invention;
FIG. 1b is a schematic cross-sectional view of another display substrate according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of another display substrate according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of another display substrate according to an embodiment of the invention;
FIG. 4 is a schematic cross-sectional view illustrating an LCD panel according to an embodiment of the present invention;
FIG. 5 is a flow chart of a method for fabricating a display substrate according to an embodiment of the present invention;
FIG. 6 is a flow chart of a method for fabricating a display substrate according to an embodiment of the present invention;
FIG. 7 is a flow chart of a method for fabricating a display substrate according to an embodiment of the present invention;
FIGS. 8 a-8 c are schematic cross-sectional views of the steps in FIG. 5;
FIGS. 9 a-9 e are schematic cross-sectional views of the steps in FIG. 6;
fig. 10a to 10e are schematic cross-sectional views corresponding to the steps in fig. 7.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
An embodiment of the present invention provides a display substrate, including: a substrate; the color resistance layer is arranged in the display area; and the planarization layer is positioned above the color resistance layer and extends to the non-display area, wherein the planarization layer positioned in the non-display area comprises a first part and a second part, the distance from the first part of the planarization layer to the display area is greater than that from the second part of the planarization layer to the display area, and the thickness of the first part of the planarization layer is smaller than that of the second part of the planarization layer. In addition, the liquid crystal display device further comprises an alignment film positioned above the planarization layer, and a first step is formed on the alignment film corresponding to the boundary of the first part and the second part.
In the embodiment of the invention, the color resistance layer of the display substrate is generally formed by combining a photoetching process and an evaporation process, and in addition, a flattening layer can be formed above the color resistance layer and in the non-display area by using a half-tone mask, so that the thickness of the first part of the flattening layer is smaller than that of the second part of the flattening layer.
In the invention, the thickness of the first part of the planarization layer is smaller than that of the second part of the planarization layer, so that a certain thickness difference can be formed at the boundary of the first part and the second part, and accordingly, the alignment film arranged above the planarization layer forms a first step at the boundary of the first part and the second part. The alignment layer generates debris during the rubbing process, and the first step can have the effect of accumulating the debris of the alignment layer.
In addition, in the embodiment of the present invention, the thickness of the second portion of the planarization layer may be larger than the thickness of the planarization layer above the color resist layer, and a certain thickness difference may be provided at the boundary between the second portion and the display region, and compared to the prior art in which the thickness of the second portion of the planarization layer is equal to the thickness of the planarization layer above the color resist layer, the height difference of the planarization layer at the boundary between the display region and the non-display region due to the provision of the color resist layer is eliminated as much as possible. The fragments of the alignment film generated in the rubbing process are mostly accumulated on the first step, and a small amount of fragments of the alignment film are further accumulated on the second step, so that the accumulation at the boundary between the display region and the non-display region can be reduced compared with the prior art in which the fragments of the alignment film are all accumulated on the second step. In addition, the thickness of the second part of the planarization layer can be further controlled to enable the height of the second part of the planarization layer to be the same as the planarization height of the display area, so that a planar structure is formed, fragments of the alignment film can not be accumulated at the boundary of the display area and the non-display area, and the image quality and the yield of the liquid crystal display device can be improved in both the two cases.
The above is the basic scheme of the present invention, and the technical scheme in the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 1a is a schematic cross-sectional structure diagram of a display substrate according to an embodiment of the invention. The display substrate comprises a substrate 1, a color resistance layer 2, a planarization layer 3 and an alignment film 4, wherein the color resistance layer 2 is arranged in a display area; the planarization layer 3 is positioned above the color resist layer 2, the planarization layer 3 extends to the non-display area, wherein the planarization layer 3 positioned in the non-display area B comprises a first portion 31 and a second portion 32, the first portion 31 of the planarization layer 3 is farther from the display area a than the second portion 32 of the planarization layer 3, the thickness h1 of the first portion 31 of the planarization layer 3 is smaller than the thickness h2 of the second portion 32 of the planarization layer 3; the alignment film 4 is located above the planarization layer 3.
On the basis of the above embodiment, optionally, the first step 5 is formed on the alignment film 4 corresponding to the boundary between the first portion 31 and the second portion 32. Specifically, the first step 5 is disposed in the non-display area B of the display substrate, and alignment film debris generated during rubbing alignment is accumulated at the first step 5, so that accumulation of alignment film debris at the boundary between the display area a and the non-display area B can be reduced or avoided, thereby avoiding occurrence of a peripheral Ghost mura, further preventing the alignment film debris from slipping to the display area a, forming protection for the display area a, and achieving an effect of improving the picture quality and the yield of the liquid crystal display device.
Optionally, the thickness h3 of the planarization layer 3 above the color resist layer 2 is smaller than the thickness h2 of the second portion 32. The planarization layer 3 above the color resistance layer 2 is located in the display area A of the display substrate, the second part 32 of the planarization layer 3 is located in the non-display area B of the display substrate, and the thickness h3 of the planarization layer 3 located in the display area A is smaller than the thickness h2 of the second part 32 of the planarization layer 3 of the non-display area B, so that compared with the prior art, the height difference of alignment films located in the display area A and the non-display area B can be reduced, and therefore alignment film fragments accumulated at the boundary of the display area A and the non-display area B can be reduced or avoided as much as possible, and the picture quality and the yield of the liquid crystal display device are improved.
Optionally, the thickness h2 of the second portion 32 is at least 0.5 μm greater than the thickness h3 of the planarization layer 3 above the color resist layer 2, and by increasing the thickness of the second portion to make the height of the upper portion of the second portion as close as possible to the height of the planarization layer above the color resist layer 2, so as to reduce the height difference between the two, excessive accumulation of alignment film debris at the interface between the display region and the non-display region can be avoided.
Optionally, the thickness h2 of the second portion 32 is 1.5 μm to 2 μm greater than the thickness h3 of the planarization layer 3 above the color resist layer 2. Considering that the thickness of the common color resist layer 2 is generally 1.5 μm to 2 μm, the thickness h2 of the second portion 32 can be 1.5 μm to 2 μm greater than the thickness h3 of the planarization layer 3 above the color resist layer 2, so as to minimize the height difference formed at the boundary between the display area a and the non-display area B of the alignment film 4 and reduce or avoid the accumulation of alignment film debris.
Alternatively, as described in the above embodiment, according to the thickness h2 of the second portion 32 of the planarization layer, the alignment film 4 may be a planar structure at the boundary between the planarization layer 3 located above the color resist layer 2 and the second portion 32, i.e., at the boundary between the display area a and the non-display area B, or may have a certain height difference, so as to form the second step 6, and the height difference of the second step 6 is reduced relative to the height difference of the step formed at the boundary between the display area a and the non-display area B in the prior art, so that the alignment film debris may be less accumulated, and in both cases, the picture quality and the yield of the liquid crystal display device may be improved. Wherein fig. 1a shows an embodiment having the second step 6, for an embodiment in which the alignment film has a planar structure at the boundary of the display region a and the non-display region B, see fig. 1B.
In the above-mentioned embodiment shown in fig. 1a and 1b, the first step 5 is an arc-shaped step, and may be further configured as a right-angle step or a diagonal step, and the second step 6 is an arc-shaped step, and may be further configured as a right-angle step or a diagonal step. In the implementation process of the invention, the specific shapes of the first step and the second step can be selected according to the actual process conditions, and are not limited.
In the above embodiment of the present invention, the colored resist layer is disposed on the display substrate, and when the display substrate is specifically applied to the technical field of liquid crystal display, the display substrate may be a color film substrate. In addition, the present invention may also be an array substrate integrated with a color resist layer, and the array substrate is usually provided with a thin film transistor array, a pixel electrode, a common electrode, and the like.
Fig. 2 is a schematic cross-sectional view of another display substrate according to an embodiment of the invention. The display substrate comprises a substrate 1, a color resistance layer 2, a planarization layer 3 and an alignment film 4, wherein the color resistance layer 2 is arranged in a display area A, the planarization layer 3 is arranged above the color resistance layer 2, the planarization layer 3 extends to a non-display area B, the planarization layer 3 arranged in the non-display area B comprises a first portion 31 and a second portion 32, the distance from the first portion 31 of the planarization layer 3 to the display area A is larger than the distance from the second portion 32 of the planarization layer 3 to the display area A, the thickness of the first portion 31 of the planarization layer 3 is smaller than the thickness of the second portion 32 of the planarization layer 3, and the alignment film 4 is arranged above the planarization layer 3.
In addition, the display substrate in the embodiment of the present invention further includes a thin film transistor array 7, a pixel electrode and a common electrode, in this embodiment, the pixel electrode and the common electrode are disposed on the film layer 8, the positional relationship between the pixel electrode and the common electrode in the film layer 8 is not limited in this embodiment, and may be disposed on the same layer or on different layers, the color resistance layer 2 is formed above the film layer 8 where the pixel electrode and the common electrode are located, and further, the planarization layer 3 and the alignment film 4 are disposed above the color resistance layer 2.
Fig. 3 is a schematic cross-sectional view of another display substrate according to an embodiment of the invention. The display substrate comprises a substrate 1, a color resistance layer 2, a planarization layer 3 and an alignment film 4, wherein the color resistance layer 2 is arranged in a display area A, the planarization layer 3 is arranged above the color resistance layer 2, the planarization layer 3 extends to a non-display area B, the planarization layer 3 arranged in the non-display area B comprises a first portion 31 and a second portion 32, the distance from the first portion 31 of the planarization layer 3 to the display area A is larger than the distance from the second portion 32 of the planarization layer 3 to the display area A, the thickness of the first portion 31 of the planarization layer 3 is smaller than the thickness of the second portion 32 of the planarization layer 3, and the alignment film 4 is arranged above the planarization layer 3.
In addition, the display substrate in this embodiment further includes a thin film transistor array 7, a pixel electrode and a common electrode, in this embodiment, the pixel electrode and the common electrode are disposed on the film layer 8, a positional relationship between the pixel electrode and the common electrode in the film layer 8 is not limited in this embodiment, and may be disposed on the same layer or on different layers, and the pixel electrode and the common electrode are both formed above the color resistance layer 2, specifically, the film layer 8 where the pixel electrode and the common electrode are located is disposed above the planarization layer 3.
In the embodiment of the invention shown in fig. 2 and fig. 3, for the case that the display panel is an array substrate, specifically, the non-display region B further includes a peripheral driving circuit 9, the planarization layer 3 located in the non-display region B covers the peripheral driving circuit 9, and usually, the peripheral driving circuit 9 is used for providing a driving signal for the thin film transistor array 7 in the display region and is generally disposed in the same layer as the thin film transistor array 7. In the above embodiments of the present invention, especially when the thickness of the second portion of the planarization layer located in the non-display region B is increased, the effect of protecting the peripheral driving circuit 9 can be achieved, and physical scratches are not easily generated during rubbing alignment, so that the peripheral driving circuit 9 can be effectively protected.
In the above embodiment of the present invention, the thickness of the first portion of the planarization layer in the non-display area is smaller than that of the second portion, and the thickness of the second portion of the planarization layer may also be larger than that of the planarization layer in the display area, and for the relationship between the thickness of the planarization layer in the display area and the thickness of the planarization layer in the first portion, the relationship may be set according to actual requirements, and if the thickness of the planarization layer in the first portion is larger than that of the planarization layer in the display area, and the thickness of the planarization layer in the non-display area B is larger than that of the planarization layer in the display area, the relationship may also function as a protection for the peripheral driving circuit, but in a case where the peripheral driving circuit does not extend below the planarization layer in the first portion, the thickness of the planarization layer in the first portion may be smaller than that of the planarization layer in the display area. In addition, as for the thickness of the alignment film above the planarization layer, in general, the thickness is set to be uniform in both the display region and the non-display region.
Fig. 4 is a schematic cross-sectional view of a liquid crystal display panel according to an embodiment of the invention. The liquid crystal display panel comprises a first substrate 10 and a second substrate 20 arranged opposite to the first substrate 10, a liquid crystal layer 30 is arranged between the first substrate 10 and the second substrate 20, and the first substrate 10 or the second substrate 20 adopts the display substrate described in any of the above embodiments.
Optionally, the liquid crystal display device further includes a frame sealing adhesive 40 disposed around the liquid crystal layer 30, where the frame sealing adhesive 40 is disposed corresponding to a boundary between the first portion 31 and the second portion 32 of the planarization layer 3.
In the liquid crystal display panel provided by the embodiment of the invention, the first substrate or the second substrate adopts the display substrate provided by the above embodiment, wherein the thickness of the first part of the planarization layer of the display substrate is smaller than that of the second part of the planarization layer, the first step is formed at the boundary of the alignment film corresponding to the first part and the second part, and the first step can play a role in accumulating alignment film scraps. Furthermore, the thickness of the first part of the planarization layer is set to be smaller, especially when the thickness of the first part of the planarization layer is smaller than that of the planarization layer of the display area, the thickness of the frame sealing glue corresponding to the first part in the direction perpendicular to the first substrate and the second substrate can be relatively increased when the frame sealing glue is set, and the width of the frame sealing glue in the direction parallel to the first substrate and the second substrate can be reduced for the frame sealing glue with the same volume, so that the width of the non-display area of the liquid crystal display panel can be further reduced, and a narrow frame is realized.
The invention also provides a liquid crystal display device which comprises the liquid crystal display panel according to the embodiment and has the same technical effects as the liquid crystal display panel.
Based on the same inventive concept, the embodiment of the invention also provides a manufacturing method of the display substrate. Fig. 5 is a schematic flow chart illustrating a method for manufacturing a display substrate according to an embodiment of the present invention. Fig. 8a to 8c are schematic cross-sectional structural diagrams corresponding to the steps in fig. 5, and as shown in fig. 5, the method of the embodiment includes the following steps:
step S110, providing the substrate 1.
Step S120, forming a color resist layer 2 on the substrate 1, the color resist layer 2 being disposed in the display area a.
Step S130, forming a planarization layer 3, where the planarization layer 3 is located above the color resist layer 2 and extends to the non-display region B, where the planarization layer 3 located in the non-display region B includes a first portion 31 and a second portion 32, a distance from the first portion 31 of the planarization layer 3 to the display region a is greater than a distance from the second portion 32 of the planarization layer 3 to the display region a, and a thickness of the first portion 31 of the planarization layer 3 is smaller than a thickness of the second portion 32 of the planarization layer 3.
In step S140, an alignment film 4 is formed over the planarization layer 3.
In the manufacturing method provided by the embodiment of the invention, the thickness of the first part of the planarization layer, which is far away from the display area, is smaller than the thickness of the second part of the planarization layer, which is close to the display area, so that the first step is formed at the boundary of the first part and the second part on the alignment film, and the first step can play a role in accumulating alignment film scraps.
Optionally, the step of forming the planarization layer 3 in step S130 may specifically be: the planarization layer 3 is formed over the color resist layer 2 and the non-display region B using a half-tone mask such that the thickness of the first portion 31 of the planarization layer 3 is smaller than the thickness of the second portion 32 located on the planarization layer 3.
The half-tone mask may be a mask including regions having different light transmittances. For example, the halftone mask may include a light-transmitting region that transmits all light, a light-blocking region that blocks all light, and a translucent region that transmits a portion of light. The translucent region may include a plurality of closely arranged slits, or a thin metal layer for controlling the amount of exposure. In this embodiment, the planarization layers having different thicknesses can be formed in the same process step by using the halftone mask.
Optionally, the step of forming the planarization layer 3 in step S130 may further include: a half-tone mask is used so that the thickness of the planarization layer 3 above the photoresist layer 2 is less than the thickness of the second portion 32. As described above, the planarization layers having different thicknesses can be formed in the same process step by using the halftone mask. In addition, the thickness of the planarization layer 3 above the color resist layer 2 is smaller than that of the second portion 32, so that the height difference of the alignment films in the display area a and the non-display area B can be reduced, further, the accumulation of alignment film debris at the boundary between the display area a and the non-display area B can be reduced or avoided as much as possible, and further, the picture quality and the yield of the liquid crystal display device are improved.
The display panel in the embodiment of the present invention may be an array substrate, and the thin film transistor array, the pixel electrode, the common electrode, and the like are disposed on the array substrate, and the manufacturing method may be included according to a difference in a positional relationship of the color resistance layer.
Fig. 6 is a schematic flow chart illustrating a manufacturing method of another display substrate according to an embodiment of the present invention. Fig. 9a to 9e are schematic cross-sectional structure diagrams corresponding to the steps in fig. 6, and as shown in fig. 6, the method of the present embodiment includes the following steps:
step S210, providing a substrate 1;
step S220, forming a thin film transistor array 7 on the substrate 1, please refer to fig. 9 a;
step S230, forming a pixel electrode and a common electrode on the thin film transistor array 7, specifically, the pixel electrode and the common electrode in this embodiment are located in the film layer 8, and the positional relationship between the pixel electrode and the common electrode in the film layer 8 is not limited in this embodiment, and may be set in the same layer or in different layers, please refer to fig. 9 b;
step S240 is to square the color resist layer 2 on the pixel electrode and the common electrode 6, and the color resist layer 2 is disposed in the display area a, please refer to fig. 9 c;
step S250, forming a planarization layer 3, wherein the planarization layer 3 is located above the color resist layer 2 and extends to the non-display region B, the planarization layer 3 located in the non-display region B includes a first portion 31 and a second portion 32, a distance from the first portion 31 of the planarization layer 3 to the display region a is greater than a distance from the second portion 32 of the planarization layer 3 to the display region a, and a thickness of the first portion 31 of the planarization layer 3 is smaller than a thickness of the second portion 32 of the planarization layer 3, please refer to fig. 9 d;
in step S260, an alignment layer 4 is formed on the planarization layer 3, please refer to fig. 9 e.
Fig. 7 is a schematic flow chart illustrating a manufacturing method of another display substrate according to an embodiment of the present invention. Fig. 10a to 10e are schematic cross-sectional structure diagrams corresponding to the steps in fig. 7, and as shown in fig. 7, the method of the present embodiment includes the following steps:
step S310, providing a substrate 1;
step S320, forming a thin film transistor array 7 on the substrate 1, please refer to fig. 10 a;
step S330, forming a color resistance layer 2 on the thin film transistor array 7, and referring to fig. 10b, the color resistance layer 2;
step S340, forming a planarization layer 3, wherein the planarization layer 3 is located above the color resist layer 2 and extends to the non-display region B, the planarization layer 3 located in the non-display region B includes a first portion 31 and a second portion 32, a distance from the first portion 31 of the planarization layer 3 to the display region a is greater than a distance from the second portion 32 of the planarization layer 3 to the display region a, and a thickness of the first portion 31 of the planarization layer 3 is smaller than a thickness of the second portion 32 of the planarization layer 3, please refer to fig. 10 c;
step S350, forming a pixel electrode and a common electrode above the planarization layer 3, where the pixel electrode and the common electrode are formed above the color resistance layer 2, specifically, the pixel electrode and the common electrode in this embodiment are located on the film layer 8, and the positional relationship between the pixel electrode and the common electrode in the film layer 8 is not limited in this embodiment, and may be set on the same layer or on different layers, please refer to fig. 10 d.
In step S360, an alignment film 4 is formed on the film layer 8 where the pixel electrode and the common electrode are located, please refer to fig. 10 e.
In the above embodiments of the present invention, optionally, a first step is formed on the alignment film corresponding to the boundary between the first portion and the second portion.
Optionally, the thickness of the planarization layer 3 above the color resist layer 2 is smaller than the thickness of the second portion.
Optionally, the thickness of the second portion is at least 0.5 μm greater than the thickness of the planarization layer 3 above the color-resist layer 2.
Optionally, the thickness of the second portion is 1.5 μm to 2 μm greater than the thickness of the planarization layer 3 located above the color resist layer 2.
Optionally, at the boundary between the planarization layer 3 and the second portion above the color resist layer 2, the alignment film is formed with a second step or a planar structure.
Optionally, the non-display area B further includes a peripheral driving circuit, and the planarization layer 3 located in the non-display area B covers the peripheral driving circuit.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (15)
1. A display substrate including a display area and a non-display area surrounding the display area, comprising:
a substrate;
the color resistance layer is arranged in the display area;
wherein the planarization layer located above the color-resist layer extends to the non-display region, wherein the planarization layer located in the non-display region includes a first portion and a second portion, the first portion of the planarization layer is farther from the display region than the second portion of the planarization layer is, the first portion of the planarization layer has a thickness smaller than the second portion of the planarization layer, and the planarization layer located above the color-resist layer has a thickness smaller than the second portion; and
and a first step is formed on the alignment film corresponding to the junction of the first part and the second part so as to accumulate friction debris of the alignment film, wherein the first step is a right-angle step.
2. The display substrate of claim 1, wherein the thickness of the second portion is at least 0.5 μm greater than the thickness of the planarization layer over the color-resist layer.
3. The display substrate of claim 1, wherein the thickness of the second portion is 1.5 μm to 2 μm greater than the thickness of the planarization layer over the color resist layer.
4. The display substrate of claim 1, wherein the alignment film is formed with a second step or a planar structure at an interface between the planarization layer and the second portion over the color resist layer.
5. The display substrate of claim 4, the second step being an arc-shaped step, a right-angled step, or a diagonal step.
6. The display substrate of claim 1, further comprising:
a thin film transistor array;
a pixel electrode and a common electrode;
the color resistance layer is formed over the pixel electrode and the common electrode.
7. The display substrate of claim 1, further comprising:
a thin film transistor array;
a pixel electrode and a common electrode;
the pixel electrode and the common electrode are formed over the color resistance layer.
8. The display substrate according to claim 1, wherein the non-display region further comprises a peripheral driving line, and the planarization layer in the non-display region covers the peripheral driving line.
9. A liquid crystal display panel comprising a first substrate and a second substrate disposed opposite to the first substrate, wherein a liquid crystal layer is disposed between the first substrate and the second substrate, and the first substrate or the second substrate is the display substrate according to any one of claims 1 to 8.
10. The lcd panel of claim 9, further comprising a sealant disposed around the liquid crystal layer, wherein the sealant is disposed corresponding to a boundary between the first portion and the second portion of the planarization layer.
11. A liquid crystal display device comprising the liquid crystal display panel according to claim 9 or 10.
12. A method of manufacturing a display substrate according to any one of claims 1 to 8, comprising the steps of:
providing a substrate;
forming a color resistance layer over the substrate, the color resistance layer being disposed in the display region;
forming a planarization layer over the color resist layer and extending to a non-display region, wherein the planarization layer in the non-display region includes a first portion and a second portion, the first portion of the planarization layer is located at a greater distance from the display region than the second portion of the planarization layer is located at the display region, the first portion of the planarization layer has a thickness less than the second portion of the planarization layer, and the forming a planarization layer further includes using a halftone mask to make the thickness of the planarization layer over the color resist layer less than the second portion;
and forming an alignment film above the planarization layer, wherein a first step is formed on the alignment film corresponding to the junction of the first part and the second part so as to accumulate friction debris of the alignment film, and the first step is a right-angle step.
13. The method for manufacturing a display substrate according to claim 12, wherein the forming of the planarization layer specifically comprises:
and forming a planarization layer above the color resist layer and the non-display region using a half-tone mask so that a thickness of a first portion of the planarization layer is smaller than a thickness of a second portion of the planarization layer.
14. The method for manufacturing a display substrate according to claim 12, further comprising:
forming a thin film transistor array on the substrate;
forming a pixel electrode and a common electrode on the thin film transistor array;
and forming the color resistance layer above the pixel electrode and the common electrode.
15. The method for manufacturing a display substrate according to claim 12, further comprising:
forming a thin film transistor array on the substrate;
forming the color resistance layer on the thin film transistor array;
and forming the pixel electrode and the common electrode above the color resistance layer.
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| CN109239963B (en) * | 2018-09-12 | 2021-04-02 | 重庆惠科金渝光电科技有限公司 | Display panel, manufacturing method thereof and display device |
| CN109713019A (en) * | 2019-01-17 | 2019-05-03 | 深圳市华星光电技术有限公司 | OLED display panel and preparation method thereof |
| KR20200113077A (en) * | 2019-03-21 | 2020-10-06 | 삼성디스플레이 주식회사 | Display panel |
| CN110137385A (en) * | 2019-04-09 | 2019-08-16 | 深圳市华星光电半导体显示技术有限公司 | Organic LED display panel and its manufacturing method |
| CN110634390A (en) * | 2019-09-20 | 2019-12-31 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111007686A (en) * | 2019-11-14 | 2020-04-14 | Tcl华星光电技术有限公司 | Array substrate, display panel and preparation method |
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