CN106603889A - Ultra high-definition VR solid-state delayer based on FPGA chip - Google Patents
Ultra high-definition VR solid-state delayer based on FPGA chip Download PDFInfo
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- CN106603889A CN106603889A CN201710069841.1A CN201710069841A CN106603889A CN 106603889 A CN106603889 A CN 106603889A CN 201710069841 A CN201710069841 A CN 201710069841A CN 106603889 A CN106603889 A CN 106603889A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
Abstract
The invention discloses an ultra high-definition VR solid-state delayer based on an FPGA chip. The delayer comprises a 12G SDI signal data serial-parallel conversion processing module; a data buffer storage time-delay processing module of ultra high-definition video/audio baseband data SDI-YUV quantification, synchronization, video and audio embedding/de-embedding and large-scale DDRIII memory particle groups; a 12G SDI data parallel-serial conversion and serial data SDI output module; an NMI/TICO decoding and 10G IP network data input processing module; an NMI/TICO encoding and 10G IP network data SFP output processing module; a large-capacity SSD original data storage standby processing module; and a processing module of ultra high-definition solid-state delayer whole-machine panel control, 1G network SNMP control and delayer function control.
Description
Technical field
The present invention relates to the shooting of ultra high-definition/high definition/VR video frequency programs and Internet video, making, storage and transmission technology
A kind of field, and in particular to ultra high-definition VR solid time delayers based on fpga chip module.
Background technology
At present, the functional design basis mainly realized depending on sound chronotron of the prior art and structure can not meet and regard
The demand that frequency definition increases into geometry multiple, its weak point includes：
1）The video input of existing design, output, the process for quantifying and storing are just for high definition and the signal of SD.
2）Existing design makees delays time to control just for high definition, standard definition signal.
2）Existing design carries out the process of signal data using DSP or ARM programming Controls mostly, also there is employing individually
Fpga chip and DSP/ARM are processed respectively, in conjunction with for common structure.
3）Existing design also has using the small-sized mainboards of CPU based on LINUX system（Or WINDOWS operating systems）And increase
The input/output interface of high standard definition signal is programmed makees delay process；
4）The input of existing design, output signal interface can not support digital media signal interface, the HDMI of ultra high-definition/high definition
Interface or DP interfaces.
5）The input of existing design, output signal interface can not support the IP network signal interfaces of ultra high-definition/high definition.
6) as the pure solid-state delay process of high definition base band video/audio signal, the high-definition signal that existing design is supported prolongs
When the time it is short, at 120 seconds（2 minutes）Or within, the various signal formats of ultra high-definition can not be supported completely.
7）Storage for solid-state time delay is partially due to be using the slow DDR of processing speed is secondary or finished product of more older version
Memory bar, cause to meet it is higher, faster, more flexible real-time read-write, detection and error correction in time of video data etc. it is various
The requirement of high-speed data process.
8）Each function majority is based on ready-made chip, to cause structure versus busy in existing design, and a lot
Function can not be optimized, so as to eventually affect the stability of product operation.
9）Existing design basis does not possess to supporting higher video signal format demand and various processing functions extendible
Probability.
10）Existing design basis does not possess to the extendible of ultra high-definition/high resolution video and audio signal IP networking requirements
Probability.
11）Existing design basis do not possess the video/audio signal to 10G IP networks receive and change, synchronization process
Probability.
12）Existing design basis does not possess the digital video-audio signal to ultra high-definition/high definition and does synchronization, conversion, time delay etc.
Data processing, and in real time with 10G IP networks according to SMPTE-2022 groups agreement output in real time process, and according to
SMPTE802.3a standards carry out the probability of UDP message broadcast distribution process.
13）Existing design basis do not possess the ultra high-definition video signal to 6G/12G go here and there and bi-directional conversion, quantify and
The probability of the data processing such as synchronous.
14）Existing design basis does not possess the ultra high-definition/high resolution video and audio signal data to required time delay buffering and makees online
The probability that time delay is saved backup particular data while output.
15）Existing design basis does not possess the conversion that international standard NMI formatted data is done to ultra high-definition video/audio signal
With the probability of delay process.
16）Existing design basis does not possess the conversion that international standard TICO formatted data is done to ultra high-definition video/audio signal
With the probability of delay process.
The content of the invention
In order to overcome problems of the prior art, the present invention to provide a kind of ultra high-definition VR based on fpga chip module
Solid time delayer, it is each that the solid time delayer provides 10G IP, DP, 12G/6G/3G/1.5G SDI etc. for high-end media user
Plant Digital Media, the data between VR systems and video signal format mutually process, change, transmitting and synchronizing relay function, and together
When there is provided ultra high-definition, high-definition digital video/audio signal IP networkings broadcast and transmit possibility, so as to filling up significantly and simplifying
The high-quality ultra high-definition video for lacking in the market and networked system and signal processing needed for various processing links,
Conversion, synchronization, time delay and IP video network broadcast distribution equipment, can be widely applied to current VR, high definition, 3D Video processings
With following 4K ultra high-definitions Video processing and IP network distributing broadcasting system, including the network media make, it is live and relay, electricity
Shadow, TV shoot, make, preserving, broadcasting and tradition regards the field such as message number and the IP digital video-audio network transmissions in future.
For achieving the above object, the ultra high-definition VR solid time delayers based on fpga chip module of the present invention include：
1）12G SDI signal data serioparallel exchange processing modules, referred to as module one；
2）Ultra high-definition video/audio base band data SDI-YUV quantizations, synchronization, video and audio add/de-embedding and extensive DDRIII internal memories
The data buffering storage delay process module of particle group, referred to as module two；
3）12G SDI data parallel-serial conversions, referred to as serial data SDI output module, module three；
4）NMI/TICO is decoded and 10G IP network data input processing modules, referred to as module four；
5）NMI/TICO is encoded and 10G ip network numbers are according to SFP output processing modules, referred to as module five；
6）Large Copacity SSD initial datas save backup processing module, referred to as module six；
7）The whole machine side plate control of ultra high-definition solid time delayer and 1G networks SNMP controls, and the process of each function control of chronotron
Module, referred to as module seven；
In wherein described module two, contain：
1）Independent video/audio adds de-embedding, the referred to as large-scale FPGA chip modules of video data synchronization process, module
2-1；For completing：1）The 4 of digital ultra high-definition SDI-YUV video datas：2：2 matrix sampling quantification treatment functions；2）Numeral
Base band video time base correction and inside/outside clock synchronizing function；3）Video/audio embedding processing function；4）It is multigroup with extensive
DDRIII memory grains group carries out in real time the high-speed channel interface of read-write, detection, error correction and the identification function of video/audio；
2）Independent smaller fpga chip module, referred to as module 2-2；It is designed for completing：The audio frequency of 8 group of 16 passage
The resampling of data 48K, clock resetting function；
3）Independent extensive multigroup DDRIII memory grains group array module, referred to as module 2-3；For completing：Superelevation
The data preservation of any, real-time read-write, storage, detection, interleaving error correction and the identification of clearly/high definition base band vast capacity data,
Delay function.
Wherein, module one is connected with module two, and the parallel data after conversion process is delivered to into module two；Module one is also simultaneously
It is connected with module seven, makes operation user by module seven come the input signal format of selecting module one, and detection module one at any time
Input signal it is whether normal；
Module 2-1 is connected with module one, and the ultra high-definition/high-definition signal data of the various forms for module one to be received are separated
The data of digital video are YUV4 by the digital video-audio data of de-embedding SDI/DP/HDMI digital signals：2：2 quantify sampling
Process, while Video Baseband data make time base correction processing and SRC clock synchronizations, reference signal is external two-stage or grade III Standard
Signal；Module 2-1 is also connected with module four, is designed for when extraneous signal is network IP signals, by module four as mark
The decoded ultra high-definition video/audio of quasi- NMI/TICO forms inputs to module 2-1, carries out same video and audio frequency
Plus/de-embedding, quantization and synchronization process function；Module 2-1 is also connected with module seven at any time, makes peripheral operation user pass through module
The seven when bases and synchronizing function to arrange, define and control ultra high-definition/high-definition digital video signal；
Module 2-2 is also connected with module seven at any time, there is provided operation user selects the channel data output function of audio frequency embedding；
Module 2-3 is connected with module 2-1, and the video/audio quantified after synchronization process and after resampling is carried out receiving and storehouse
In pushing DDRIII memory grain groups, as the time delay pooling feature of video and audio base band data；Module 2-3 also at any time with mould
Block seven is connected, there is provided operation user selects selection and the set-up function for carrying out the signal lag time；
Module three is connected with module five, for needing to make during the output of 10G IP network signals, by ultra high-definition base band video and audio number
According to module five is delivered to, after carrying out the compression of NMI or TICO forms of standard, IP data SMPTE802.3a are packaged as
Standard carries out UDP message broadcast distribution fuction output；Module three is also connected with module seven at any time, there is provided peripheral operation user enter
The selection of row output signal form and set-up function；
Module four is connected with module 2-1；The input of module four by 10G IP signal inputs to module four, according to format standard
It is decoded as ultra high-definition base band YUV 4：2：2 data, and send into module 2-1, by base band video/audio synchronize with time delay
Reason；Module four is also connected with module seven at any time, there is provided peripheral operation user carries out the selection of input signal format and set-up function；
Module five is connected with module three, and the base band video/audio after quantization, synchronization and delay process is conveyed to module five,
Data compression is carried out, is packaged as meeting the packet of NMI or TICO forms, exported in real time with SMPTE-2022 group agreements,
And SFP transmission output functions are carried out according to SMPTE802.3a data distributions standard with the network schemer of UDP；Module five is also
It is connected with module seven at any time, there is provided peripheral operation user carries out the selection of output signal form and set-up function；
Module six is connected with module 2-1, for the ultra high-definition/high resolution video and audio base band data after quantization, synchronization process to be had into choosing
Selecting property is preserved saving backup as initial data, and can be used as the function of emergent switching output；Module six is also
It is connected with module seven at any time, there is provided peripheral operation user also enters the ultra high-definition/high-definition data of required period while time delay
Row preserves the selection function of backup.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are used to realize ultra high-definition/high definition base
Delay process with uncompressed signal.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are used to realize ultra high-definition/high definition
The delay process of IP network data signals.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
Ultra high-definition/high-definition signal carries out input/output, string and data conversion treatment.Ultra high-definition/high-definition signal form is according to digital superelevation
Clearly/high definition SMPTE 2036, SMPTE 2048, SMPTE ST 2082, SMPTE ST 2081, SMPTE 424M, SMPTE
The standard of 372 and SMPTE ST 292.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The input of ultra high-definition/high definition IP network signal, according to SMPTE-2022 group agreement input signals, does data-measuring process.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
Ultra high-definition/high-definition signal carries out video/audio plus de-embedding is processed, video data YUV 4：2：2 matrix sampling quantification treatment.Number
Word ultra high-definition video data is processed according to SMPTE 2036, SMPTE 2048, SMPTE ST 2082, SMPTE ST's 2081
Standard；Standard of the digital high-definition video data process according to SMPTE 424M, SMPTE 372 and SMPTE ST 292.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The data clock of ultra high-definition/high-definition video signal is synchronous, rebuild, when base process.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
Digital audio and video signals 48K resamplings, the process of clock resetting.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The Intelligent Measurement of ultra high-definition/high-definition signal, seamless switching process.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The data of the multigroup Large Copacity DDRIII memory grain groups of ultra high-definition/high-definition signal interleave in real time read-write, detection, identification and interleave
Correction process.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The process that ultra high-definition/high-definition signal data are saved backup in real time with Large Copacity SSD read-writes, detection and data.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The encoding function of the NMI forms of ultra high-definition/high-definition signal is processed.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The decoding function of the NMI forms of ultra high-definition/high-definition signal is processed.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The encoding function of the TICO forms of ultra high-definition/high-definition signal is processed.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The decoding function of the TICO forms of ultra high-definition/high-definition signal is processed.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
The 10G IP networks of ultra high-definition signal are marked with SMPTE-2022 groups agreement output in real time process according to SMPTE802.3a
Standard carries out UDP message broadcast distribution function treatment.
Ultra high-definition VR solid time delayers based on fpga chip module of the present invention are realized using fpga chip design
Operations control function between people, machine is processed, and realizes doing machine operation with SNMP V1.0 agreements by 1G networks
State-detection, display and control function are processed.
The invention has the advantages that：Ultra high-definition VR solid time delayers based on fpga chip module of the present invention with
Prior art is compared, for high-end media user provide the various Digital Medias such as 10G IP, DP, 12G/6G/3G/1.5G SDI,
Data between VR systems and video signal format are mutually processed, changed, transmitting and synchronizing relay function, and while provide superelevation
Clearly, the possibility of high-definition digital video/audio signal IP networkings broadcast and transmission, so as to filling up significantly and simplifying in the market
The high-quality ultra high-definition video for lacking and networked system and the signal processing needed for various processing links, conversion, synchronization, prolong
When and IP video network broadcast distribution equipment, can be widely applied to current VR, high definition, 3D Video processings and the 4K in future surpass
HD video process and IP network distributing broadcasting system, including network media making, live and relay, film, TV shoot, system
Make, preserve, broadcasting and tradition regards the field such as message number and the IP digital video-audio network transmissions in future.
Multigroup DDRIII memory grain pool-size of the present invention as time delay is huge, while the design of FPGA can be at any time
Large Copacity SSD is called to do the preservation and time delay of uncompressed data, the FPGA controls of this kind of design by the control function of panel
Data processed are read and write in real time, the performance of error correction flexible, and the delay time of ultra high-definition 4K 12G SDI digital video-audio signals is supported
It is most long to the delay time of high definition SDI video/audio signal to can reach 7200 seconds, i.e., 2 hour up to 900 seconds.
Description of the drawings
Fig. 1 is that the overall structure of the ultra high-definition VR solid time delayers based on fpga chip module of the present invention is illustrated
Figure.
Fig. 2 is FPGA modules 2-1 in the ultra high-definition VR solid time delayers based on fpga chip module of the present invention
Ultra high-definition data processing principle figure.
Fig. 3 is the ultra high-definition video data processing format figure of one embodiment.
Fig. 4 is the ultra high-definition video data processing format figure of another embodiment.
Specific embodiment
Following examples are used to illustrate the present invention, but are not limited to the scope of the present invention.
As shown in figure 1, the ultra high-definition VR solid time delayers based on fpga chip module of the present invention include seven numbers
According to processing module, respectively：
1）Module one：12G SDI signal data serioparallel exchange processing modules.
2）Module two：Ultra high-definition video/audio base band data SDI-YUV quantizations, synchronization, video and audio add/de-embedding and big rule
The data buffering storage delay process module of mould DDRIII memory grain groups.
3）Module three：12G SDI data parallel-serial conversions, serial data SDI output module.
4）Module four：NMI/TICO is decoded and 10G IP network data input processing modules.
5）Module five：NMI/TICO is encoded and 10G ip network numbers are according to SFP output processing modules.
6）Module six：Large Copacity SSD initial datas save backup processing module.
7）Module seven：The whole machine side plate control of ultra high-definition solid time delayer and 1G networks SNMP controls, and each work(of chronotron
The processing module that can be controlled.
As shown in figure 1, the function that each processing module design is realized:
First, module one：12G SDI signal data serioparallel exchange processing modules：
Module one is used as the digital video-audio signal of ultra high-definition/high definition SDI of various forms and the number of ultra high-definition HDMI/DP
The reception of word media video/audio signal outside input, format detection and conversion processing module, realize various ultra high-definition signal formats
Serial data and conversion process function.
The design of module one supports that the ultra high-definition/high-definition signal form of external reception input includes：1）The digital high-definition of multichannel
The 5Gbps of baseband signal SMPTE ST 292 1.（SDI inputs 1）； 2）The digital high-definition baseband signal SMPTE 424M on 4 tunnels
2.97Gbps（SDI inputs 2）；3）The digital ultra high-definition SDI baseband signals DUAL 6G SDI SMPTE ST 2081 of two-way
6Gbps（SDI inputs 3）；4）The digital 12Gbps of ultra high-definition baseband signal SMPTE ST 2082 of single-link（SDI inputs 4）；5）
The RGB ternary chrominance signals of the 4K 25/30/50/60Hz of digital media interface HDMI or DP（HDMI/DP is input into）.
Module one is connected with module two, and the parallel data after conversion process is delivered to into module two.
Module one is also connected with module seven simultaneously, makes operation user by module 7 come the input signal lattice of selecting module 1
Formula, and at any time whether the input signal of detection module 1 is normal.
2nd, module two：Ultra high-definition video/audio base band data SDI-YUV quantizations, synchronization, video and audio add/de-embedding and big rule
The data buffering storage delay process module of mould DDRIII memory grain groups：
Module two contains that three relatively independent, FPGA function module 2-1,2-2 that resource size is different and 2-3：
1st, module 2-1：Independent video/audio adds the large-scale FPGA cores of de-embedding, video data quantization, inside/outside synchronization process
Piece module.Module 2-1 is designed for completing：1）The 4 of digital ultra high-definition SDI-YUV video datas：2：At 2 matrix sampling quantizations
Reason function；2）The time base correction of digital baseband video and inside/outside clock synchronizing function；3）Video/audio embedding processing function；4）
With the height of read-write, detection, error correction and the identification function that extensive multigroup DDRIII memory grains group carries out in real time video/audio
Fast channel interface.
Module 2-1 is connected with module one, and the ultra high-definition/high-definition signal data of the various forms for module one to be received are done
The digital video-audio data of de-embedding SDI/DP/HDMI digital signals are separated, the data of digital video are done into YUV 4：2：2 quantify
Sampling processing, while Video Baseband data make time base correction processing and SRC clock synchronizations, reference signal is external two-stage（BI-
LEVEL）Or three-level（TRI-LEVEL）Or black field standard signal.Baseband video data after through quantifying synchronization process is again and Jing
The voice data crossed after DAB module 2-2 is processed does video and audio embedding process, then video/audio is pushed into module
As prolonged data in the DDRIII fast memory particle group battle arrays of the multi-group RECC verifying functions of 2-3 vast capacities
Storage and time delay space.
As shown in Fig. 2 pointers and related data mark of the FPGA of module 2-1 as the read-write in real time of core control data
The information of position is preserved；Fpga core control also needs to carry out the detection of the image frame by frame of original base band video data, search, to phase
Closing the information of frame image carries out record preservation, while the corresponding digital audio-frequency data of sampling clock is matched, by corresponding digital sound
Frequency data message is also carried out record and preserves.Ultra high-definition 4K digital video time base correction modules are also provided in this module 2-1, and regarding sound
Frequency according to interaction process module, for calibrating ultra high-definition/high definition according to the video phase and clock of external reference lockin signal
Digital video signal row, field phase value；Including de-noising circuit, time base corrector, loss compensation circuit；
Module 2-1 is processed the SRC clocks synchronization of the video data of 8 times of digital high-definitions with ultra large scale FPGA chip and is entered
Line timebase correction process, and while the storage granule matrix group for controlling multigroup memory grain composition of vast capacity does substantial amounts of number
According to synchronization, detection, search, time delay, hand-off process.For when time delay is needed to the base band video and audio signal of current input
Controllable delay process is carried out, the data after delay process are sent to module three, processed as video/audio signal output.
Data Detection and identification module are also provided in module 2-1, in video/audio interaction process module each
The index of the signal of digital video-audio output interface output is detected, and selective goal meets the letter of output all the way of preset standard
Number output is to external digital video/audio signal receiving device；Using the differentiation electricity being made up of several controlling switches and microprocessor
Realize on road.
The processing format of two kinds of ultra high-definition video datas shown in present invention design compatibility Fig. 3 and Fig. 4.Module 2-1 is designed
Based on the design pattern of 12G SDI digital channels, base band video image procossing is done, video data of the base band without compression is compatible following
Two kinds of image procossing modes：
1）As shown in figure 3, the subimage that view picture 4K video images are divided into 4 parts up and down is processed using 4 distribution SQD modes
Module, the video frequency signal processing for carrying out respectively.This processing mode at least needs the number of 1 frame for the signal transmission of whole system
It is used as the needs of synchronization process image according to buffering.
2）Using per 2 sampled point interleave samples 2SI（2 SAMPLE INTERLEAVE）Sampling processing pattern, will be with 1
Adjacent 2 pixels insert sample information as 1 sample unit in row.Even number line carries out 1, and 2 points interleave, and odd-numbered line does 3,4 points
Interleave, and each sampled point is accompanied with 1/4 information of original 4K images, the pixel after sampling processing according to oneself
Number order is separately constituting 4 subimages.This processing mode only needs to the data buffering of 2 rows and carrys out synchronization process view picture figure
Picture.
Module 2-1 is also connected with module four, is designed for when extraneous signal is network IP signals, by the conduct of module four
The decoded ultra high-definition video/audio of standard NMI/TICO form inputs to module 2-1, carries out same video and sound
Frequency plus/the processing function such as de-embedding, quantization, synchronization.Module 2-1 is also connected with module six, for quantifying, after synchronization process
Ultra high-definition/high resolution video and audio base band data is selective is preserved, saving backup as initial data, and can also using
It is used as the function of emergent switching output.
Module 2-1 is also connected with module seven at any time, makes peripheral operation user and is arranged by module seven, defined and controlled and be super
The when base and synchronizing function of high definition/high-definition digital video signal, including video line, the setting of field phase value, inside/outside genlock
Set-up function.
2）Module 2-2：Independent smaller fpga chip module, design does the sound after de-embedding is processed with module 2-1
Frequency according to completing the voice data 48K resamplings of 8 group of 16 passage, clock resetting function, and being connected with module 2-1 at any time, work
Match for the clock information after audio resampling with video data.
Module 2-2 is also connected with module seven at any time, can provide the channel data output that operation user selects audio frequency embedding
Function.
3）Module 2-3：Independent extensive multigroup DDRIII memory grains group array module.
The multigroup extensive DDRIII memory grain groups with RECC verifications of module 2-3 design are used as ultra high-definition/height
Any, the real-time read-write of clear base band vast capacity data, storage, detection, the interleaving data such as error correction and identification preservation, time delay work(
Energy.This design makes the real-time read or write speed of jumbo data faster, more flexible, and makes the detection work(of correcting data error at any time
Energy.
Module 2-3 is connected with module 2-1, and the video/audio quantified after synchronization process and after resampling is received
And storehouse is pushed in DDRIII memory grain groups, as the time delay pooling feature of video and audio base band data.
Module 2-3 is also connected with module seven at any time, there is provided operation user selects to carry out the selection of signal lag time and sets
Determine function.
3rd, module three：The process of 12G SDI ultra high-definition digital video-audios serial mode and output module：
Module three is used for the ultra high-definition/high resolution video and audio data convert after delay process for ultra high-definition base band sdi signal
Output.The same compatible various ultra high-definitions of output signal form and high-definition digital signal format, including：
1）The 5Gbps of digital high-definition baseband signal SMPTE ST 292 1. of multichannel；
2）The digital high-definition baseband signal SMPTE 424M 2.97Gbps on 4 tunnels；
3）The digital ultra high-definition SDI baseband signals SMPTE ST 2081-10 6Gbps of two-way；
4）The digital 12Gbps of ultra high-definition baseband signal SMPTE ST 2082 of single-link；
5）The RGB ternary chrominance signals of the 4K 25/30/50/60Hz of digital media interface HDMI or DP.
Module three is connected with module five, for when needing to make the output of 10G IP network signals, ultra high-definition base band being regarded
Voice data delivers to module five, after carrying out the compression of NMI or TICO forms of standard, is packaged as IP data
SMPTE802.3a standards carry out UDP message broadcast distribution fuction output.
Module three is also connected with module seven at any time, there is provided peripheral operation user carries out the selection and setting of output signal form
Function.
4th, module four：NMI/TICO is decoded and 10G IP network data input processing modules：
Module four is performed the decoding of NMI or TICO forms using ultra large scale FPGA chip and is driven.（NMI or TICO forms
For the ultra high-definition code/decode format of international standard, we have been authorized to use both standards）.
Process and YUV quantization of the module four to ultra high-definition video data is identical with the data processing mode of module 2-1, adopts
Based on the full 4K or 8K compressions of pixel in the ranks, newest based on the advanced extensive interface AXI interfaces of ARM LIMITED
Huge data compression process is realized for Advanced Microcontroller Bus structure AMBA4.0 of 4.0 versions.
Module four is connected with module 2-1.The input of module four by 10G IP signal inputs to this module, according to form mark
Standard is decoded as ultra high-definition base band YUV 4：2：2 data, and module 2-1 is sent into, base band video/audio is synchronized and time delay
Process.
Module four is also connected with module seven at any time, there is provided peripheral operation user carries out the selection and setting of input signal format
Function.
5th, module five：NMI/TICO is encoded and 10G ip network numbers are according to SFP output processing modules：
Module five is performed the coding of NMI or TICO forms using ultra large scale FPGA chip and is driven.（NMI or TICO forms
For the ultra high-definition code/decode format of international standard, we have been authorized to use both standards）.
Module five is connected with module three, and the base band video/audio after quantization, synchronization and delay process is conveyed to mould
Block five, carries out data compression, is packaged as meeting the packet of NMI or TICO forms, real-time with SMPTE-2022 group agreements
Output, and SFP transmission output functions are carried out according to SMPTE802.3a data distributions standard with the network schemer of UDP.
Module five is also connected with module seven at any time, there is provided peripheral operation user carries out the selection and setting of output signal form
Function.
6th, module six：Large Copacity SSD initial datas save backup processing module：
Module six is connected with module 2-1, for the ultra high-definition/high resolution video and audio base band data after quantization, synchronization process to be had into choosing
Selecting property is preserved saving backup as initial data, and can also be used to the function as emergent switching output.
Module six is also connected with module seven at any time, there is provided peripheral operation user is by the ultra high-definition/high-definition data of required period
Also carry out preserving the selection function of backup while time delay.
7th, module seven：The whole machine side plate control of ultra high-definition solid time delayer and 1G networks SNMP controls, and each work(of chronotron
The processing module that can be controlled：
Module seven realizes human-computer interactive control by fpga chip, for arranging the input/output signal lattice with display delayed device
The parameter of the selection of formula, every video and audio frequency is selected, the setting of the delay time of various signal formats, and while can be passed through
Network SNMP V1.0 agreements are controlled and monitor the working condition of chronotron.
Module seven is connected respectively with 6 functional modules of all of the above, for receive external user input instruction after,
Each module is selected, controlled and set.
Although the present invention is described in detail above to have used general explanation and specific embodiment, at this
On the basis of invention, it can be made some modifications or improvements, this will be apparent to those skilled in the art.Therefore,
Without departing from theon the basis of the spirit of the present invention these modifications or improvements, belong to the scope of protection of present invention.
Claims (16)
1. a kind of ultra high-definition VR solid time delayers based on fpga chip module, it is characterised in that described based on fpga chip mould
The ultra high-definition VR solid time delayers of block include：
1）12G SDI signal data serioparallel exchange processing modules, referred to as module one；
2）Ultra high-definition video/audio base band data SDI-YUV quantizations, synchronization, video and audio add/de-embedding and extensive DDRIII internal memories
The data buffering storage delay process module of particle group, referred to as module two；
3）12G SDI data parallel-serial conversions, referred to as serial data SDI output module, module three；
4）NMI/TICO is decoded and 10G IP network data input processing modules, referred to as module four；
5）NMI/TICO is encoded and 10G ip network numbers are according to SFP output processing modules, referred to as module five；
6）Large Copacity SSD initial datas save backup processing module, referred to as module six；
7）The whole machine side plate control of ultra high-definition solid time delayer and 1G networks SNMP controls, and the process of each function control of chronotron
Module, referred to as module seven；
In wherein described module two, contain：
1）Independent video/audio adds de-embedding, the referred to as large-scale FPGA chip modules of video data synchronization process, module
2-1；For completing：1）The 4 of digital ultra high-definition SDI-YUV video datas：2：2 matrix sampling quantification treatment functions；2）Digital base
Band video time base correction and inside/outside clock synchronizing function；3）Video/audio embedding processing function；4）It is multigroup with extensive
DDRIII memory grains group carries out in real time the high-speed channel interface of read-write, detection, error correction and the identification function of video/audio；
2）Independent smaller fpga chip module, referred to as module 2-2；It is designed for completing：The sound of 8 group of 16 passage
Frequency is according to 48K resamplings, clock resetting function；
3）Independent extensive multigroup DDRIII memory grains group array module, referred to as module 2-3；For completing：Superelevation
Any, the real-time read-write of clearly/high definition base band vast capacity data, storage, detection, interleave error correction, the data of identification preserve and
Delay function；
Wherein, module one is connected with module two, and the parallel data after conversion process is delivered to into module two；Module one is also while and mould
Block seven is connected, and makes operation user by module seven come the input signal format of selecting module one, and detection module one at any time is defeated
Whether normal enter signal；
Module 2-1 is connected with module one, and the ultra high-definition/high-definition signal data of the various forms for module one to be received are separated
The data of digital video are YUV 4 by the digital video-audio data of de-embedding SDI/DP/HDMI digital signals：2：2 quantify sampling
Process, while Video Baseband data make time base correction processing and SRC clock synchronizations, reference signal is external two-stage or grade III Standard
Signal；Module 2-1 is also connected with module four, is designed for when extraneous signal is network IP signals, by module four as mark
The decoded ultra high-definition video/audio of quasi- NMI/TICO forms inputs to module 2-1, carries out same video and audio frequency
Plus/de-embedding, quantization and synchronization process function；Module 2-1 is also connected with module seven at any time, makes peripheral operation user pass through module
The seven when bases and synchronizing function to arrange, define and control ultra high-definition/high-definition digital video signal；
Module 2-2 is also connected with module seven at any time, there is provided operation user selects the channel data output function of audio frequency embedding；
Module 2-3 is connected with module 2-1, and the video/audio quantified after synchronization process and after resampling is carried out receiving and storehouse
In pushing DDRIII memory grain groups, as the time delay pooling feature of video and audio base band data；Module 2-3 also at any time with mould
Block seven is connected, there is provided operation user selects selection and the set-up function for carrying out the signal lag time；
Module three is connected with module five, for needing to make during the output of 10G IP network signals, by ultra high-definition base band video and audio number
According to module five is delivered to, after carrying out the compression of NMI or TICO forms of standard, IP data SMPTE802.3a are packaged as
Standard carries out UDP message broadcast distribution fuction output；Module three is also connected with module seven at any time, there is provided peripheral operation user enter
The selection of row output signal form and set-up function；
Module four is connected with module 2-1；The input of module four by 10G IP signal inputs to module four, according to format standard solution
Code is ultra high-definition base band YUV 4：2：2 data, and module 2-1 is sent into, base band video/audio is synchronized and delay process；
Module four is also connected with module seven at any time, there is provided peripheral operation user carries out the selection of input signal format and set-up function；
Module five is connected with module three, and the base band video/audio after quantization, synchronization and delay process is conveyed to module five,
Data compression is carried out, is packaged as meeting the packet of NMI or TICO forms, exported in real time with SMPTE-2022 group agreements,
And SFP transmission output functions are carried out according to SMPTE802.3a data distributions standard with the network schemer of UDP；Module five is also
It is connected with module seven at any time, there is provided peripheral operation user carries out the selection of output signal form and set-up function；
Module six is connected with module 2-1, for the ultra high-definition/high resolution video and audio base band data after quantization, synchronization process to be had into choosing
Selecting property is preserved saving backup as initial data, and can be used as the function of emergent switching output；Module six is also
It is connected with module seven at any time, there is provided peripheral operation user also enters the ultra high-definition/high-definition data of required period while time delay
Row preserves the selection function of backup.
2. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
Module 2-1 includes the fpga chip mould of independent ultra high-definition/HD video data-measuring, synchronization, time base correction, detection and switching
Block；For realizing：1）The 4 of digital ultra high-definition SDI-YUV video datas：2：2 matrix sampling quantification treatment functions；2）Digital baseband
Video time base correction and inside/outside clock synchronizing function；3）Video/audio embedding processing function；4）With extensive multigroup DDRIII
Memory grain group carries out in real time the high-speed channel interface of read-write, detection, error correction and the identification function of video/audio.
3. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
Module 2-2 includes the fpga chip module that independent voice data is processed；For realize ultra high-definition/high definition parallel data regarding sound
Frequency de-embedding separating treatment function.
4. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
Module 2-3 includes carrying out extensive multigroup DDRIII memory grains group in real time the read-write of video/audio, Data Detection and entangles
Wrong, the fpga chip module of identification function；For completing：Any, the real-time reading of ultra high-definition/high definition base band vast capacity data
Write, store, detecting, interleaving data preservation, the delay function of error correction and identification.
5. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
Ultra high-definition VR solid time delayers based on fpga chip module are used to realize at the time delay of ultra high-definition/high definition base band uncompressed signal
Reason.
6. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
Ultra high-definition VR solid time delayers based on fpga chip module are used to realize the time delay of ultra high-definition/high definition IP network data signals
Process.
7. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
Ultra high-definition VR solid time delayers based on fpga chip module realize the defeated of ultra high-definition/high-definition signal using fpga chip design
Enter/export, according to digital ultra high-definition/high definition SMPTE 2036, SMPTE 2048, SMPTE ST 2082, SMPTE ST
The standard of 2081, SMPTE 424M, SMPTE 372 and SMPTE ST 292.
8. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
Ultra high-definition VR solid time delayers based on fpga chip module realize ultra high-definition/high definition IP network letter using fpga chip design
Number input, according to SMPTE-2022 group agreement input signals, do data-measuring process.
9. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
Ultra high-definition VR solid time delayers based on fpga chip module realize that ultra high-definition/high-definition signal is regarded using fpga chip design
Voice data adds de-embedding to process, video data YUV 4：2：2 matrix sampling quantification treatment；Digital ultra high-definition video data processes root
According to SMPTE 2036, SMPTE 2048, SMPTE ST 2082, the standard of SMPTE ST 2081；At digital high-definition video data
Manage the standard according to SMPTE 424M, SMPTE 372 and SMPTE ST 292.
10. the ultra high-definition VR solid time delayers of fpga chip module are based on as claimed in claim 1, it is characterised in that described
The ultra high-definition VR solid time delayers based on fpga chip module using fpga chip design realize ultra high-definition/high-definition video signal
The inside and outside clock of data it is synchronous, rebuild and when base process.
The 11. ultra high-definition VR solid time delayers based on fpga chip module as claimed in claim 1, it is characterised in that described
The ultra high-definition VR solid time delayers based on fpga chip module realize the intelligence of ultra high-definition/high-definition signal using fpga chip design
Can detection and seamless switching process.
The 12. ultra high-definition VR solid time delayers based on fpga chip module as claimed in claim 1, it is characterised in that described
The ultra high-definition VR solid time delayers based on fpga chip module using fpga chip design realize that ultra high-definition/high-definition signal is multigroup
Correction process is read and write in real time, detects, recognizes and interleaved to the data of Large Copacity DDRIII memory grain groups.
The 13. ultra high-definition VR solid time delayers based on fpga chip module as claimed in claim 1, it is characterised in that described
The ultra high-definition VR solid time delayers based on fpga chip module using fpga chip design realize ultra high-definition/high-definition signal data
The process for saving backup with Large Copacity SSD read-writes, detection and data in real time.
The 14. ultra high-definition VR solid time delayers based on fpga chip module as claimed in claim 1, it is characterised in that described
The ultra high-definition VR solid time delayers based on fpga chip module using fpga chip design realize ultra high-definition/high-definition signal
The codec functions of NMI forms are processed.
The 15. ultra high-definition VR solid time delayers based on fpga chip module as claimed in claim 1, it is characterised in that described
The ultra high-definition VR solid time delayers based on fpga chip module realize the TICO of ultra high-definition signal using fpga chip design
The decoding function of form is processed.
The 16. ultra high-definition VR solid time delayers based on fpga chip module as claimed in claim 1, it is characterised in that described
The ultra high-definition VR solid time delayers based on fpga chip module realize the 10G nets of ultra high-definition signal using fpga chip design
Network carries out UDP message distribution function with SMPTE-2022 groups agreement output in real time process according to SMPTE802.3a standards
Process.
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| CN116132615A (en) * | 2023-01-14 | 2023-05-16 | 北京流金岁月传媒科技股份有限公司 | Conversion method and device for ultrahigh-definition 8K HDMI2.1 to 4x12G-SDI |
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