CN106601740A - Silicon-based InGaAs channel dual gate COMS device - Google Patents
Silicon-based InGaAs channel dual gate COMS device Download PDFInfo
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- CN106601740A CN106601740A CN201611226809.1A CN201611226809A CN106601740A CN 106601740 A CN106601740 A CN 106601740A CN 201611226809 A CN201611226809 A CN 201611226809A CN 106601740 A CN106601740 A CN 106601740A
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 title claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 28
- 239000010703 silicon Substances 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 27
- 230000009977 dual effect Effects 0.000 title claims abstract 5
- 229910052751 metal Inorganic materials 0.000 claims description 38
- 239000002184 metal Substances 0.000 claims description 38
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 22
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 4
- 229910052760 oxygen Inorganic materials 0.000 claims 4
- 239000001301 oxygen Substances 0.000 claims 4
- 229910052735 hafnium Inorganic materials 0.000 claims 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a silicon-based InGaAs channel dual gate COMS device. According to the invention, the device integrates a silicon-based semiconductor material and an InGaAs channel dual gate CMOS device by using the medium bonding method so as to increase the level of heterogeneous integration of the CMOS device. The dual gate structure also achieves reduction in power consumption of the device. The device makes it easy to adjust the threshold voltage thereof.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of silicon substrate InGaAs channel dual-bar COMS devices.
Background technology
Integrated circuit is developed so far, it is already possible to integrated more than one hundred million transistors on silicon, the power consumption of individual devices and
Fuel factor has become the key element of restriction integrated circuit development.IntegratecCMOS devices have become and work as on silicon-based semiconductor
Front study hotspot and frontline technology.But, two disasters that current InGaAs cmos devices face are entitled：1)InGaAs CMOS
The Manufacturing resource of device and silicon substrate；2) power problemses of integrated post CMOS.Need for this improve InGaAs cmos devices with
The Manufacturing resource mode of silicon substrate, and realize the performance of the low-power consumption of device.
The content of the invention
The silicon substrate InGaAs channel dual-bar COMS devices that the present invention is provided, using medium bonding method silicon-based semiconductor is realized
Material is integrated with InGaAs channel dual-bar cmos devices, and to improve the Manufacturing resource degree of cmos device, and double-gate structure can
The low-power consumption work of device is realized, and the threshold voltage adjustments of device are easier.
It is in a first aspect, the present invention provides a kind of silicon substrate InGaAs channel dual-bar COMS devices including silicon substrate (1), described
Bonding medium (2) and (3) on silicon substrate (1) and by InGaAs raceway groove nmos devices (4), InGaAs channel PMOS devices
(5) and the InGaAs channel dual-bar cmos devices that constitute of interconnection metal (6), wherein, the bonding medium (2) and (3) are for general
The InGaAs channel dual-bars cmos device is bonded with the silicon substrate (1), and interconnection metal (6) is described for connecting
InGaAs raceway groove nmos devices (4) and the InGaAs channel PMOS devices (5)；
The InGaAs raceway grooves nmos device (4) is including eigen I nGaAs channel layer (401), positioned at eigen I nGaAs raceway groove
Layer (401) both sides top n-type doping InGaP boundary layer (402) and bottom p-type adulterate InGaP boundary layers (403), positioned at institute
State GaAs source and drain Ohmic contact cap layers (404), the position of the top n-type doping above top n-type doping InGaP boundary layer (402)
The GaAs source and drain Ohmic contact cap layers of the bottom p-type doping below the bottom p-type adulterates InGaP boundary layers (403)
(405), Source and drain metal level (406), the position above GaAs source and drain Ohmic contact cap layers (404) of the top n-type doping
Top gate medium (407) above the top n-type doping InGaP boundary layer (402), on the top gate medium (407)
The top-gated metal (408) of side, adulterate positioned at the bottom p-type bottom gate medium (407) below InGaP boundary layers (403) and
Bottom gate metal (410) below the bottom gate medium (409)；
The InGaAs channel PMOS devices (5) are including eigen I nGaAs channel layer (501), positioned at eigen I nGaAs raceway groove
Layer (501) both sides top n-type doping InGaP boundary layer (502) and bottom p-type adulterate InGaP boundary layers (503), positioned at institute
State GaAs source and drain Ohmic contact cap layers (504), the position of the top n-type doping above top n-type doping InGaP boundary layer (502)
The GaAs source and drain Ohmic contact cap layers of the bottom p-type doping below the bottom p-type adulterates InGaP boundary layers (503)
(505), Source and drain metal level (506), the position below GaAs source and drain Ohmic contact cap layers (505) of bottom p-type doping
Top gate medium (507) above the top n-type doping InGaP boundary layer (502), on the top gate medium (507)
The top-gated metal (508) of side, the bottom gate medium (509) below InGaP boundary layers (503) of adulterating positioned at the bottom p-type, it is located at
Bottom gate metal (510) below the bottom gate medium (509).
Silicon substrate InGaAs channel dual-bar COMS devices provided in an embodiment of the present invention, using medium bonding method silicon substrate is realized
Semi-conducting material is integrated with InGaAs channel dual-bar cmos devices, and to improve the Manufacturing resource degree of cmos device, and double grid is tied
Structure can realize the low-power consumption work of device, and the threshold voltage adjustments of device are easier.
Description of the drawings
Fig. 1 is the structural representation of one embodiment of the invention silicon substrate InGaAs channel dual-bar COMS devices.
Specific embodiment
To make purpose, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only
Only it is a part of embodiment of the invention, rather than the embodiment of whole.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
The present invention provides a kind of silicon substrate InGaAs channel dual-bar COMS devices, as shown in figure 1, the device includes silicon
Bonding medium 2 and 3 on substrate 1, the silicon substrate 1 and by InGaAs raceway grooves nmos device 4, InGaAs channel PMOS devices
The 5 InGaAs channel dual-bar cmos devices constituted with interconnection metal 6, wherein, the bonding medium 2 and 3 is used for will be described
InGaAs channel dual-bars cmos device is bonded with the silicon substrate 1, and the interconnection metal 6 is used to connect the InGaAs ditches
Road nmos device 4 and the InGaAs channel PMOS devices 5；
The InGaAs raceway grooves nmos device 4 is including eigen I nGaAs channel layer 401, positioned at eigen I nGaAs channel layer
The top n-type doping InGaP boundary layer 402 of 401 both sides and bottom p-type doping InGaP boundary layers 403, positioned at the top N-type
The GaAs source and drain Ohmic contacts cap layers 404 of the top n-type doping of the top of doping InGaP boundary layers 402, positioned at the bottom p-type
The GaAs source and drain Ohmic contacts cap layers 405 of the bottom p-type doping of the lower section of doping InGaP boundary layers 403, positioned at the top N-type
The Source and drain metal level 406 of the top of GaAs source and drain Ohmic contacts cap layers 404 of doping, positioned at the top n-type doping InGaP interface
The top gate medium 407 of the top of layer 402, the top-gated metal 408 positioned at the top of the top gate medium 407, mix positioned at the bottom p-type
The bottom gate medium 407 and the bottom gate metal 410 positioned at the lower section of the bottom gate medium 409 of the lower section of miscellaneous InGaP boundary layers 403；
The InGaAs channel PMOS devices 5 are including eigen I nGaAs channel layer 501, positioned at eigen I nGaAs channel layer
The top n-type doping InGaP boundary layer 502 of 501 both sides and bottom p-type doping InGaP boundary layers 503, positioned at the top N-type
The GaAs source and drain Ohmic contacts cap layers 504 of the top n-type doping of the top of doping InGaP boundary layers 502, positioned at the bottom p-type
The GaAs source and drain Ohmic contacts cap layers 505 of the bottom p-type doping of the lower section of doping InGaP boundary layers 503, positioned at the bottom p-type
The Source and drain metal level 506 of the lower section of GaAs source and drain Ohmic contacts cap layers 505 of doping, positioned at the top n-type doping InGaP interface
The top gate medium 507 of the top of layer 502, the top-gated metal 508 positioned at the top of the top gate medium 507, mix positioned at the bottom p-type
The bottom gate medium 509 of the lower section of miscellaneous InGaP boundary layers 503, the bottom gate metal 510 below the bottom gate medium 509.
Silicon substrate InGaAs channel dual-bar COMS devices provided in an embodiment of the present invention, using medium bonding method silicon substrate is realized
Semi-conducting material is integrated with InGaAs channel dual-bar cmos devices, and to improve the Manufacturing resource degree of cmos device, and double grid is tied
Structure can realize the low-power consumption work of device, and the threshold voltage adjustments of device are easier.Specifically, with compound semiconductor work
For the double-gated devices structure of raceway groove so that the device has high mobility characteristic and good grid voltage control characteristic concurrently, so as to more hold
The low-power consumption work of device is easily realized, and threshold voltage adjustments are easier.
Alternatively, in the eigen I nGaAs channel layer 401 and the eigen I nGaAs channel layer 501 InGaAs In groups
The thickness for being divided into 0.25-0.4, the eigen I nGaAs channel layer 401 and the eigen I nGaAs channel layer 501 is 7 nanometers.
Alternatively, in the top n-type doping InGaP boundary layer 402 and the top n-type doping InGaP boundary layer 502
The In components of InGaAs are 0.5, the top n-type doping InGaP boundary layer 402 and the top n-type doping InGaP boundary layer
502 doping content is 5 × 1017-1×1018cm-3, the top n-type doping InGaP boundary layer 402 and the top N-type are mixed
The thickness of miscellaneous InGaP boundary layers 502 is 2 nanometers.
Alternatively, in the bottom p-type doping InGaP boundary layers 403 and bottom p-type doping InGaP boundary layers 503
The In components of InGaAs are 0.4, and bottom p-type doping InGaP boundary layers (403) and the bottom p-type are adulterated InGaP interfaces
The doping content of layer 503 is 8 × 1017-2×1018cm-3, bottom p-type doping InGaP boundary layers 403 and the bottom p-type
The thickness of doping InGaP boundary layers 503 is 3 nanometers.
Alternatively, the GaAs source and drain Ohmic contacts cap layers 404 of the top n-type doping and the top n-type doping
The thickness of GaAs source and drain Ohmic contacts cap layers 504 is 50 nanometers, the GaAs source and drain Ohmic contact cap layers of the top n-type doping
404 and the top n-type doping GaAs source and drain Ohmic contacts cap layers 504 doping content be 5 × 1018cm-3。
Alternatively, the GaAs source and drain Ohmic contacts cap layers 405 and the bottom p-type of the bottom p-type doping are adulterated
The thickness of GaAs source and drain Ohmic contacts cap layers 505 is 50 nanometers, the GaAs source and drain Ohmic contact cap layers of the bottom p-type doping
405 and the bottom p-type doping GaAs source and drain Ohmic contacts cap layers 505 doping content be 2 × 1019cm-3。
Alternatively, it is characterised in that the Source and drain metal level 406 is nickel that thickness is 10 nanometers, thickness is 20 nanometers
Germanium or thickness are 100 nanometers of gold；The top gate medium 407 is the hafnium oxide that thickness is 2.5 nanometers, the top-gated metal
408 is tungsten that thickness is 100 nanometers；The bottom gate medium 409 is the aluminum oxide that thickness is 3 nanometers, and the bottom gate metal 410 is
Thickness is 100 nanometers of aluminium.
Alternatively, it is characterised in that the Source and drain metal level 506 is platinum that thickness is 10 nanometers, thickness is 30 nanometers
Titanium or thickness are 100 nanometers of gold；The top gate medium 507 is the aluminum oxide that thickness is 2.5 nanometers, the top-gated metal
508 is aluminium that thickness is 100 nanometers；The bottom gate medium 509 is the hafnium oxide that thickness is 3 nanometers, and the bottom gate metal 510 is
Thickness is 100 nanometers of titanium-tungsten.
Alternatively, the bonding medium (2) is SiO2, the bonding medium (3) is BCB or Al2O3.Alternatively, it is described
Interconnection metal 4 is titanium or gold.
The above, the only specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, the change or replacement that can be readily occurred in, all should
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be defined by scope of the claims.
Claims (10)
1. a kind of silicon substrate InGaAs channel dual-bar COMS devices, it is characterised in that including on silicon substrate (1), the silicon substrate (1)
Bonding medium (2) and (3) and by InGaAs raceway groove nmos devices (4), InGaAs channel PMOS devices (5) and interconnection metal
(6) the InGaAs channel dual-bar cmos devices for constituting, wherein, the bonding medium (2) and (3) are for by the InGaAs raceway grooves
Dual gate CMOS device is bonded with the silicon substrate (1), and the metal (6) that interconnects is for connecting the InGaAs raceway grooves NMOS
Device (4) and the InGaAs channel PMOS devices (5)；
The InGaAs raceway grooves nmos device (4) is including eigen I nGaAs channel layer (401), positioned at eigen I nGaAs channel layer
(401) top n-type doping InGaP boundary layer (402) of both sides and bottom p-type doping InGaP boundary layers (403), positioned at described
GaAs source and drain Ohmic contact cap layers (404) of the top n-type doping above top n-type doping InGaP boundary layer (402), it is located at
GaAs source and drain Ohmic contact cap layers (405) of the bottom p-type doping below bottom p-type doping InGaP boundary layers (403),
Source and drain metal level (406) above GaAs source and drain Ohmic contact cap layers (404) of the top n-type doping, positioned at described
Top gate medium (407), the top above the top gate medium (407) above top n-type doping InGaP boundary layer (402)
Grid metal (408), adulterate bottom gate medium (407) below InGaP boundary layers (403) and positioned at institute positioned at the bottom p-type
State the bottom gate metal (410) below bottom gate medium (409)；
The InGaAs channel PMOS devices (5) are including eigen I nGaAs channel layer (501), positioned at eigen I nGaAs channel layer
(501) top n-type doping InGaP boundary layer (502) of both sides and bottom p-type doping InGaP boundary layers (503), positioned at described
GaAs source and drain Ohmic contact cap layers (504) of the top n-type doping above top n-type doping InGaP boundary layer (502), it is located at
GaAs source and drain Ohmic contact cap layers (505) of the bottom p-type doping below bottom p-type doping InGaP boundary layers (503),
Positioned at the bottom p-type doping GaAs source and drain Ohmic contact cap layers (505) below Source and drain metal level (506), positioned at described
Top gate medium (507), the top above the top gate medium (507) above top n-type doping InGaP boundary layer (502)
Grid metal (508), the bottom gate medium (509) below InGaP boundary layers (503) of adulterating positioned at the bottom p-type, positioned at the bottom
Bottom gate metal (510) below gate medium (509).
2. device according to claim 1, it is characterised in that the eigen I nGaAs channel layer (401) and described intrinsic
The In components of InGaAs are 0.25-0.4 in InGaAs channel layers (501), the eigen I nGaAs channel layer (401) and described
The thickness for levying InGaAs channel layers (501) is 7 nanometers.
3. device according to claim 1, it is characterised in that the top n-type doping InGaP boundary layer (402) and institute
The In components for stating InGaAs in top n-type doping InGaP boundary layer (502) are 0.5, the top n-type doping InGaP boundary layer
(402) and the top n-type doping InGaP boundary layer (502) doping content be 5 × 1017-1×1018cm-3, the top N
The thickness of type doping InGaP boundary layers (402) and the top n-type doping InGaP boundary layer (502) is 2 nanometers.
4. device according to claim 1, it is characterised in that bottom p-type doping InGaP boundary layers (403) and institute
The In components for stating InGaAs in bottom p-type doping InGaP boundary layers (503) are 0.4, the bottom p-type doping InGaP boundary layers
(403) and the bottom p-type doping InGaP boundary layers (503) doping content be 8 × 1017-2×1018cm-3, the bottom P
The thickness of type doping InGaP boundary layers (403) and bottom p-type doping InGaP boundary layers (503) is 3 nanometers.
5. device according to claim 1, it is characterised in that the GaAs source and drain Ohmic contact caps of the top n-type doping
The thickness of GaAs source and drain Ohmic contact cap layers (504) of layer (404) and the top n-type doping is 50 nanometers, the top N-type
GaAs's source and drain Ohmic contact cap layers (404) of doping and GaAs source and drain Ohmic contact cap layers (504) of the top n-type doping
Doping content is 5 × 1018cm-3。
6. device according to claim 1, it is characterised in that the GaAs source and drain Ohmic contact caps of the bottom p-type doping
The thickness of layer (405) and GaAs source and drain Ohmic contact cap layers (505) of bottom p-type doping is 50 nanometers, the bottom p-type
GaAs's source and drain Ohmic contact cap layers (405) of doping and GaAs source and drain Ohmic contact cap layers (505) of bottom p-type doping
Doping content is 2 × 1019cm-3。
7. device according to claim 1, it is characterised in that the Source and drain metal level (406) is 10 nanometers for thickness
Nickel, thickness are 20 nanometers of germanium or gold that thickness is 100 nanometers；The top gate medium (407) is oxygen that thickness is 2.5 nanometers
Change hafnium, the top-gated metal (408) is tungsten that thickness is 100 nanometers；The bottom gate medium (409) is oxygen that thickness is 3 nanometers
Change aluminium, the bottom gate metal (410) is aluminium that thickness is 100 nanometers.
8. device according to claim 1, it is characterised in that the Source and drain metal level (506) is 10 nanometers for thickness
Platinum, thickness are 30 nanometers of titanium or gold that thickness is 100 nanometers；The top gate medium (507) is oxygen that thickness is 2.5 nanometers
Change aluminium, the top-gated metal (508) is aluminium that thickness is 100 nanometers；The bottom gate medium (509) is oxygen that thickness is 3 nanometers
Change hafnium, the bottom gate metal (510) is titanium-tungsten that thickness is 100 nanometers.
9. device according to claim 1, it is characterised in that the bonding medium (2) is SiO2, the bonding medium (3)
For BCB or Al2O3。
10. device according to claim 1, it is characterised in that the interconnection metal (4) is titanium or gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611226809.1A CN106601740B (en) | 2016-12-27 | 2016-12-27 | Silicon substrate InGaAs channel dual-bar cmos device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611226809.1A CN106601740B (en) | 2016-12-27 | 2016-12-27 | Silicon substrate InGaAs channel dual-bar cmos device |
Publications (2)
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| CN107833923A (en) * | 2017-10-30 | 2018-03-23 | 桂林电子科技大学 | A kind of silicon substrate InGaAs channel dual-bar MOSFET elements and preparation method thereof |
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