RU2513644C1 - Semiconductor device with negative resistance (versions) - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: suggested device unites three field effect transistors into a unified vertical structure with channels of n- and p-type conductivity thus forming an electrical junction between them, at that the source of p-type channel is located opposite the source of n-type channel, and the source of p-type channel is located opposite the source of n-type channel. Sources of the channels are interconnected by a conductor and an additional zone with n⁺-type conductivity where the source of n-type channel is formed, and drains of the channels have separate outputs. The device can be equipped with one gate (three-terminal device - version 1) or two gates (four-terminal device - version 2) located at the other (second) lateral side of the channels. Current in the channels passes in one direction and creates back voltage in the junction thus locking the channels. The device can contain more than one structure, at that gates are common for neighbouring structures.

EFFECT: invention allows reducing dimensions, increasing operational speed, current and output power of the device.

4 cl, 6 dwg

Description

The invention relates to the field of semiconductor electronics, namely, devices with adjustable negative differential resistance, and can be used in various electronic devices and integrated circuits designed to generate, amplify and convert electrical signals with modulation of output signals.

Known vertical field-effect transistor (PT) containing a semiconductor substrate, drain (source) with n ⁺ -type of conductivity, vertical conductive channels with n-type of conductivity, a gate made in the form of a metal tape perforated within the semiconductor structure, and a source (drain ) with n ⁺ -type of conductivity [1]. Schottky barriers form between the gate and the channels. The transistor is made of gallium arsenide (GaAs).

However, this device uses vertical channels with only n-type conductivity.

A known vertical PT [2], containing a substrate with n ⁺ -type of conductivity, which is the source (drain) of channels with n-type conductivity, metal gates placed on non-conductive areas of the device structure and forming Schottky barriers with channels, as well as drains with n ⁺ -type of conductivity. In addition, a Schottky diode (LH) is additionally formed on the same crystal, moreover, one contact of the diode is combined with the source (drain) contact of the vertical transformer, and the other DS contact is connected to the drain (source) contact of the transformer. A vertical focal point with a longitudinal beam forms a composite device.

However, this device also uses vertical channels with only n-type conductivity.

Known vertical PT [3], containing the metal output of the source, ohmic contact to the source, the source made of an n ⁺ -type semiconductor, vertical conductive channels with n-type conductivity, the shutter made in the form of a metal tape perforated within the semiconductor structure , and sink with n ⁺ -type of conductivity. Schottky barriers form between the gate and the channels.

This device also uses vertical channels with only n-type conductivity.

Closest to the claimed device is a semiconductor device - a lambda transistor [4], consisting of three depleted field-effect transistors, which is selected as a prototype. In this case, two transistors with channels of n- and p-types of conductivity (complementary field effect transistors) form a lambda diode, and the third transistor serves to change the current of the device. It is usually placed between complementary transistors. The middle transistor can have a channel with n- or p-type conductivity, and the corresponding voltage is applied to the gate to change the channel resistance. The complementary transistors are interconnected as follows: the drain terminal of the transistor with an n-type channel is connected to the gate terminal of another transistor with a p-channel, the drain terminal of which is connected to the gate of the transistor with an n-channel, and the source terminals of the complementary transistors are connected to the drain and source terminals medium transistor. A positive voltage is applied to the drain of a transistor with an n-channel with respect to the drain of a transistor with a p-channel.

The main disadvantages of this device:

- the device consists of three separate field effect transistors, so the size of the device increases;

- cross-metal connections between the electrodes complicate the design of the device, especially when using a sufficiently large number of unit structures.

The technical result of the invention is to reduce the size, increase speed and increase the current and output power of the device with adjustable negative differential resistance.

The essence of the invention lies in the fact that in the device containing channels with n- and p-types of conductivity, gates, sources and drains of channels, vertical channels are used that are parallel to each other. Moreover, the channels are in contact with each other on the sides, and an electrical transition is formed. A distinctive feature of the proposed device is the location of the source of the p-channel opposite the drain of the n-channel, and the drain of the p-channel is opposite the source of the n-channel. To connect the sources of the channels to each other, an additional region with an n ⁺ -type of conductivity is formed. The source of the p-channel is connected to the additional area using a conductor, and the source of the n-channel is placed directly on the additional area. Channel drains have separate leads. The current in the channels flows in one direction. Unlike a lambda transistor, the proposed device does not have metal connections between the channel drains and the corresponding gates. In the device, an electrical transition locking the channels is formed directly between the channels, which simplifies the design of the device and reduces its size.

The gates are formed on the other side of the channels and are located on non-conductive areas (dielectric). Schottky barriers, metal-oxide structures, or control pn junctions can be used to control channel resistances. The shutter thickness should correspond to the length of the channel and may have submicron dimensions. To reduce the resistance of the shutter, its thickness in the middle part may be greater than at the edges.

In the first version, the device has only one gate to the channel with n- or p-type conductivity (three-electrode device). In a three-electrode device, when using more than one unit structure, unit structures can be combined as follows: channels with the same type of conductivity, to which the gates are not formed, are combined into one common channel and it is placed between channels with a different type of conductivity, and new combined structures are formed.

In the second embodiment, the gates are formed to both channels (four-electrode device), and the second gate can be used to adjust the parameters of the device. When using more than one unit structure in a four-electrode device, unit structures can be combined using a common gate to channels of the same conductivity type of neighboring structures.

The vertical structure provides the ability to reduce channel lengths, which will improve the performance of the device. The device can have only one unit structure or contain a sufficiently large number of unit structures, in this case, the current and output power of the device can be increased. In the proposed device, three field-effect transistors are combined into a single vertical structure, thereby achieving the claimed technical result.

Figure 1 shows a possible variant of a single structure of a three-electrode device (option 1) in plan and its longitudinal section, figure 2 shows cross-sections of a device, figure 3 shows a possible version of a three-electrode device with two new structures in plan and a longitudinal section. Figure 4 shows a possible variant of the unit structure of a four-electrode device (option 2) in plan and its longitudinal section, figure 5 shows the cross-sections of a four-electrode device, figure 6 shows a possible version of a four-electrode device with two unit structures in plan and a longitudinal section.

In the first embodiment, a single structure is formed on the substrate 1 (Figure 1), in the device channel 2 with p-type conductivity is in contact with channel 3 with n-type conductivity. The source 4 of the p-channel is opposite the drain 5 of the n-channel, and the drain 6 of the p-channel is opposite the source 7 of the n-channel. Source 4 and drain 6 of the p-channel have p ⁺ -type conductivity, and drain 5 and source 7 of the n-channel have n ⁺ -type conductivity. The drain 6 of the p-channel is connected to terminal 8, and the drain 5 of the n-channel has terminal 9. The source 7 of the n-channel is located on an additional region 10 with an n ⁺ type of conductivity. The source 4 of the p-channel is connected to the source 7 of the n-channel using the region 10 and the conductor 11, which forms ohmic contacts with the region 10 and the source 4 of the p-channel. The dielectric film 12 isolates the p-channel drain terminal 8 from region 10. The n-channel drain terminal 9 is connected to bus 13, and the p-channel drain terminal 8 to bus 14. Gate 15 forms a Schottky barrier with n-type channel 3. The combination of the gate 15 with the channel 3 is made using a dielectric film 16. The gate is connected to the bus 17. The tires 13 and 17 are located on the dielectric film 16, and the bus 14 is on the substrate 1.

When using more than one unit structure, channels with a p-type conductivity, to which no gates are formed, are combined into one common channel and it is placed between channels with an n-type conductivity, and a new structure is formed (figure 3).

In the second embodiment (figures 4-6), a second gate 18 is formed to the p-channel 2, which also forms a Schottky barrier with channel 2. The gate 18 is formed on a dielectric film 16. The gates 15 and 18 are connected to the buses 17 and 19, respectively. The output of the p-channel drain 8 is connected to the bus 14, and the n-channel drain 5 has a separate terminal 9. The two unit structures are combined using the common gate 18 to the p-channels of 2 adjacent structures (Figure 6).

The device operates as follows. At the drain 9 of the n-channel serves a positive voltage U ₀ relative to the drain 6 of the p-channel (figure 1,4). Current in one direction will flow through n-channel 3 and p-channel 2. The current creates a voltage drop on the n-channel U _n , and on the p-channel U _p . If you do not take into account the voltage drop at the drain, the source of the channels and region 10, then U _n + U _p = U ₀ . At the electrical transition between channels with n- and p-types of conductivity, reverse voltage appears. The potential difference at the junction varies from U _p in the lower part of the electrical transition between the source 7 of the n-channel and the drain 6 of the p-channel to U _n in the upper part of the transition between the drain 5 of the n-channel and the source 4 of the p-channel. Reverse voltage closes each channel from source to drain. In the general case, U _{n is} not equal to U _p , but a variant is possible when U _n = U _p. However, in any case, with an increase in the reverse voltage at the junction, the thickness of the depletion layer in each channel increases, which leads to a decrease in the thickness of the conducting part of the channel, therefore, with an increase in U _{0, the} current first increases, reaches its maximum value, then due to the overlap of the channels and an increase in their resistances, the current will be to decrease. When the channels are completely blocked by depleted layers, the current will be determined by the leakage currents of the reverse biased transitions.

With an increase in the reverse voltage at the gate, the channel resistance will increase, which leads to a decrease in the maximum current and the cutoff voltage of the device when the current of the device is minimal. Thus, the current-voltage characteristics of the lambda transistor are formed in the device.

In the first version of the device, when using more than one unit structure (Figure 3), in each new structure, currents will flow in the same direction along the n-channels 3 and p-channel 2. The sources of 7 n-channels in each new structure are interconnected using the formed region 10, so the voltage drops on the n-channels U _n will be the same (currents in n-channels in the general case may not be equal to each other). The current in the p-channel is equal to the sum of the currents flowing in the adjacent n-channels. To equalize the values of the resistance of the p-channel and the total resistance of the n-channels, it is possible, for example, to reduce the thickness of the n-channels or to reduce the concentration of impurities in these channels.

In both versions of the device, when using more than one unit structure (Figures 3 and 6), the gates are common to neighboring structures, and channels with the same type of conductivity are placed symmetrically with respect to the gates.

The device can be made of silicon or of semiconductor materials of group A ^III B ^V with higher electron mobility.

Compared with the prototype, the proposed device with a vertical structure and parallel n- and p-channels, in which the current flows in one direction, will allow:

- reduce the size and simplify the design of the device;

- increase the performance of the device by reducing the length of the channels;

- increase current and output power when using more than one unit structure in the device.

Information sources

1. Hollis M.A., Bozler C. O., Nichols K.B., Bergeron N.J. Vertical transistor device fabricated with semiconductor regrowth. Patent No. US 4903089 (A), IPC: H01L 29/80, claimed 02/02/1988, publ. 02/20/1990

2. Brar B.P.S., On W. Vertical field-effect transistor and method of forming the same. Patent No. US 7663183, pending. 06/19/2007, publ. 02.16.2010

3. Semenov A.V., Khan A.V., Khan V.A. Vertical field effect transistor. Patent No. RU 2402105, IPC: H01L 29/772, claimed 08/03/2009, publ. 10.20.2010 g.

4. Lambda diode - a multifunctional device with negative resistance. G. Kano, X. Ivazo, X. Takagi, I. Teramoto. Electronics. - 1975, T. 48, No. 13 - p. 48-53.

Claims (4)

1. A semiconductor device with negative resistance (options), containing channels with n- and p-types of conductivity, gates, sources and drains of channels, characterized in that the device uses vertical channels with n- and p-types of conductivity in contact the sides of the channel, while the source of the p-channel is opposite the drain of the n-channel, and the drain of the p-channel is opposite the source of the n-channel, the sources of the channels are interconnected using a conductor and an additional region with an n ⁺ type of conductivity on which the source is formed n-channel, and drains to the analogs have separate conclusions, and the device may have one shutter (option 1) or two shutters (option 2). 2. The device according to claim 1, characterized in that in the first embodiment, the gate is formed on the side of the n-channel or p-channel, which does not contact the channel with a different type of conductivity, and if there is more than one unit structure in the device, adjacent channels, to which the gates are not formed, are combined into one common channel and it is placed between channels with a different type of conductivity. 3. The device according to claim 1, characterized in that in the second embodiment, the gates are formed on the sides of the n-channel and p-channel, not in contact with the channels with a different type of conductivity. 4. The device according to claim 1, characterized in that in both cases, if there is more than one unit structure in the device, the gates are common to neighboring structures, and channels with the same type of conductivity are placed symmetrically with respect to the gates.

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