CN106601739A - 具有薄化介电材料的结构 - Google Patents

具有薄化介电材料的结构 Download PDF

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CN106601739A
CN106601739A CN201610054742.1A CN201610054742A CN106601739A CN 106601739 A CN106601739 A CN 106601739A CN 201610054742 A CN201610054742 A CN 201610054742A CN 106601739 A CN106601739 A CN 106601739A
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dielectric
tin
nfet
sides
pfet
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CN106601739B (zh
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R·鲍
T·安多
A·达斯古普塔
K·赵
U·权
S·A·克里希南
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GlobalFoundries US Inc
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Abstract

本发明是涉及具有薄化介电材料的结构，是关于半导体结构，并且更具体地说，是关于具有薄化介电材料的结构及制造方法。本方法包括在基板上沉积高k介电质。本方法更包括直接在该高k介电质上沉积氮化钛膜，并同时蚀刻该高k介电质。

Description

具有薄化介电材料的结构
技术领域
本发明是关于半导体结构，并且更具体地说，是关于具有薄化介电材料的结构及制造方法。
背景技术
现代积体电路制造的趋势在于生产尽量小的半导体装置，例如场效晶体管(FET)。在一般的FET中，源极与漏极是通过在半导体材料中布植n型或p型杂质，于半导体基板的主动区中形成。置于源极与漏极之间的是通道(或本体)区。置于本体区上方的是栅极电极。栅极电极与本体是通过栅极介电层隔开。
虽然制造更小的晶体管容许在单一基板上置放更多的晶体管，以便在相对较小的晶粒面积中形成相对较大的电路系统，这样的尺寸缩减可以提升效能，但也会降低可靠度。举例而言，n通道场效晶体管(nFET)及p通道场效晶体管(pFET)的尺寸缩减可调整位于栅极金属与半导体基板之间反转层厚度(Tinv)的大小，用以增强效能。
在调整装置尺寸时，通过调整介电质厚度来提升介于nFET装置与pFET装置之间的可靠度仍然存在着冲突。举例而言，更薄的介电材料会提升nFET装置的正偏压温度不稳定性(pBTI)可靠度，但更厚的介电材料则会有助于pFET装置的负偏压温度不稳定性(nBTI)可靠度。然而，事实上，使用现有的技术进行此类调整会有困难。
发明内容
在本发明的一态样中，一种方法包括在基板上沉积高k介电质。本方法更包括直接在该高k介电质上沉积氮化钛膜，并同时蚀刻该高k介电质。
在本发明的一态样中，一种方法包括在基板的pFET侧及nFET侧上沉积高k介电材料。本方法更包括直接在该基板的pFET侧及nFET侧的至少一者的该高k介电材料上沉积具有TiCl4的先驱物的氮化钛(TiN)，以薄化接触该TiCl4TiN的该高k介电材料。
在本发明的一态样中，结构包括：在基板上具有高k介电材料的nFET装置；以及在该基板上具有该高k介电材料的pFET装置。该nFET装置及该pFET装置的至少一者的高k介电材料包括Cl且不具有C。
附图说明
本发明是通过本发明的例示性具体实施例的非限制性实施例的方式，参照注记的多个图式，在以下的详细说明中予以说明。
图1至图3根据本发明的态样，显示nFET及pFET装置的结构及各别制造处理。
图4根据本发明的附加态样，显示nFET及pFET装置的结构及各别制造处理。
图5a至图5c根据本发明的进一步态样，显示nFET及pFET装置的结构及各别制造处理。
图6根据本发明的又进一步态样，显示nFET及pFET装置的结构及各别制造处理。
图7显示实施如本发明中所述的程序时，介电膜中的Cl浓度。
图8显示金属有机(MO)TiN及高温TiCl4TiN沉积后介电质厚度的比较图。
图9显示TiCl4TiN的介电损耗(厚度损耗)与沉积温度的关系比较图。
具体实施方式
本发明是关于半导体结构，并且更具体地说，是关于具有薄化介电材料的结构及制造方法。更具体而言，本发明是针对例如HfO2(二氧化铪)的高k介电材料的原子性(选择性)蚀刻，使用的是高温TiCl4TiN，用于缩减nFET及pFET装置的尺寸。有助益的是，在具体实施例中，本文中所述的方法提升经尺寸调整装置的可靠度，所采用的方式在一项实作态样中，是以更厚的HfO2改善pFET负偏压温度不稳定性(nBTI)并以更薄的HfO2改善nFET正偏压温度不稳定性(pBTI)。
在具体实施例中，原子层沉积(ALD)TiN是在高温下使用TiCl4(四氯化钛)先驱物进行制备。举一例子来说，HCl(盐酸)是TiN(氮化钛)沉积期间，先驱物TiCl4与先驱物NH3(氨)之间高温反应的副产物。诸如HfO2的高k材料无法通过常用的HCl程序进行蚀刻：然而，发明人已发现，某些条件下TiCl4TiN沉积的HCl副产物容许高k膜在原子级控制下进行蚀刻。因此，TiCl4TiN可用于以可控制方式薄化例如HfO2的介电材料，该可控制方式容许进一步调整装置尺寸并提升可靠度。本文中所述的方法可通过选择性或非选择性蚀刻来执行。
本发明的装置可使用若干不同的工具以若干的方式来制造。不过，一般来说，该些方法及工具是用于形成微米及纳米级尺寸的结构。用于制造本发明的装置的方法，即技术，已用在积体电路(IC)技术。举例而言，该些结构是建置在晶圆上，并且是在晶圆上方通过光微影程序以制作材料膜图案(pattern)的方式来实现。特别的是，制造该些装置使用了三个基本建构块：(i)在基板上沉积材料的薄膜，(ii)通过光微影成像术在膜上涂敷图案化遮罩，以及(iii)选择性地对遮罩进行膜的蚀刻。
图1根据本发明的态样，显示nFET及pFET装置的结构及各别制造处理。在具体实施例中，结构5包含在基板10的nFET侧及基板10的pFET侧形成有多个沟槽12的基板10。在具体实施例中，基板10可以是氧化物材料或一或多种介电材料。如本领域技术人员应理解，结构5可以是平面结构或finFET结构，因此不需多作阐释。
在具体实施例中，沟槽12是在基板10的nFET侧及pFET侧两者形成。沟槽12可通过常用的微影及蚀刻(例如反应性离子蚀刻(RIE)或润湿)程序来形成。更具体地说，阻剂是在基板10上形成，并且曝露至能量(光)以形成图案(开口)。反应性离子蚀刻(RIE)或润湿是通过开口进行以形成沟槽12。阻剂可接着通过氧气灰化或其它常用的条化剂(stripant)进行移除。
再请参阅图1，介面材料14是沉积于基板10上及沟槽12内的表面上。介面材料14可以是氧化物材料，例如SiO2。介面材料14可通过任何常用的沉积程序来形成，举例来说，例如化学气相沉积(CVD)。介电材料16是在介面材料14上形成。介电材料16较佳为高k介电材料，例如以铪(hafnium)为主的材料(HfO2)。介电材料16可通过原子层沉积(ALD)程序进行沉积，但其它沉积程序也在本发明的考量范围内，例如CVD或电浆增强型CVD(PECVD)程序。介电材料16的沉积厚度可以是约1.5nm至约3nm；但其它尺寸也在本发明的考量范围内。在具体实施例中，介电材料16可经受后沉积退火程序。
图1进一步显示形成于介电材料16上的TiN层18。在具体实施例中，如本领域技术人员应理解，TiN层18可包括金属有机(MO)先驱物。在具体实施例中，TiN层18的沉积厚度约为至约但其它尺寸也在本发明的考量范围内。阻剂或遮罩20是在pFET侧的TiN层18上方形成。更具体地说，阻剂或遮罩20是在nFET及pFET两者的TiN层18上形成。阻剂20是曝露至能量(光)以形成图案。如图1所示，此图案是曝露基板的nFET侧的开口，亦即，曝露nFET侧的TiN层18。
在图2中，nFET侧的TiN层18是使用RIE或润湿程序进行移除。在具体实施例中，移除TiN层18会曝露基板的nFET侧下面的介电层16。应了解的是，RIE或润湿程序对TiN层18具有选择性，因此不会侵蚀基板的nFET侧的介电层16。移除TiN层18及阻剂层之后，一层具有先驱物的TiN材料22是在高温下，于(pFET侧的)TiN层18及(nFET侧的)介电层16上沉积。在具体实施例中，先驱物是TiCl4及NH3，而TiCl4TiN层22(又称为TiCl4TiN)可使用ALD或CVD程序，以等于或高于约300℃的温度沉积，更高的温度更佳，例如450℃至500℃。在附加或替代的具体实施例中，先驱物可以是TiCl4及NH3的混合先驱物来源。在具体实施例中，范围0.1g/min至1.2g/min的TiCl4及1slm至10slm的NH3可用于在给定温度范围内蚀刻HfO2。
发明人已发现，沉积TiN层22(又称为TiCl4TiN)会薄化基板的nFET侧下面的介电层16(亦即原子性(选择性)蚀刻高k介电材料)。举例而言，发明人已发现，TiN层22(又称为TiCl4TiN)可自基板的nFET侧下面的介电层16起，蚀刻大约(埃)；然而，pFET侧的介电层16仍会维持其原来的沉积厚度，如参考元件符号16a所表示的接面处所示。更具体地说，基板的pFET侧的介电层16仍受到TiN层18保护，因此，不会经受薄化程序。
如图3所示，可移除TiN层22(又称为TiCl4TiN)及TiN层18，以曝露位在pFET侧及nFET侧的介电层16。此结构接着可经受常用的金属栅极程序，例如：沉积金属填充材料及图案化程序，以形成栅极结构。按照这个方式，更厚的介电材料，例如HfO2，可用于pFET nBTI，而更薄的介电材料，例如HfO2，则可用于nFET pBTI。
图4根据本发明的附加态样，显示替代结构及各别制造程序。在图4的结构5'中，TiN层22(又称为TiCl4TiN)会留在nFET侧及pFET侧两者的介电材料16上。类似于参阅图1至图3所述，TiN层22(又称为TiCl4TiN)(具有先驱物TiCl4及先驱物NH3或TiCl4与NH3先驱物的混合物)可自基板的nFET侧下面的介电层16起，进行蚀刻至大约 然而，位在pFET侧的介电层16则会维持其原来的沉积厚度，如参考元件符号16a表示的接面处所示(原因在于层件18提供保护)。nFET金属堆叠30接着是在TiN层22(又称为TiCl4TiN)上沉积。在具体实施例中，nFET金属堆叠30可包括TiAlC、TaAlC、TiAl、Ti(钛)及Al(铝)中的一者，接着是金属填料，例如TiN、钨、铝或其它金属填料。
图5a至图5c根据本发明的附加态样，显示替代结构及各别制造程序。类似于参阅图1所述，在图5a的结构5”中，介面材料14，例如SiO2，是在基板10上沉积，而且是在沟槽12内。介电材料16是在介面材料14上形成。介电材料16较佳为高k介电材料，例如HfO2，是通过原子层沉积(ALD)程序沉积至约1.5nm至约3nm的厚度(如“y”所表示)。在具体实施例中，介电材料16可经受后沉积退火程序。
如图5b所示，TiN层22(又称为TiCl4TiN)(具有先驱物TiCl4及先驱物NH3或TiCl4与NH3先驱物的混合物)是在nFET侧及pFET侧两者的介电材料16上以高温进行沉积。类似于参阅图1至图3所述，TiN层22(又称为TiCl4TiN)(具有先驱物TiCl4及先驱物NH3或TiCl4与NH3先驱物的混合物)可自下面的介电层16起，选择性地进行原子性蚀刻至大约达到如“x”(其中x<y)表示的薄化尺寸。在具体实施例中，蚀刻可大于端视TiN的成核时间(nucleation time)而定。介电层16，例如HfO2，上一旦形成均匀的TiN，便会终止蚀刻。代表性地如图5b及图5c中以参考符号“x”所示，随着TiN层22(又称为TiCl4TiN)在nFET侧及pFET侧两者沉积，现将薄化装置两侧的介电层16。在图5c中，TiN层是使用常用的蚀刻程序进行移除。接着可进行金属填充程序，以便形成nFET及pFET栅极堆叠。
图6相比于图1至图3所示的结构，显示具有不同极性的结构。尤其是，图6的结构5”'显示在基板的pFET侧薄化介电材料16(亦即原子性(选择性)蚀刻高k介电材料16)。为此，应了解的是，由于HfO2能隙偏移的关系，pFET漏电远低于nFET漏电。因此，若pFET可靠度不是问题，位在基板的pFET侧的介电材料(例如HfO2)可缩减厚度，以便根据本发明的态样改善尺寸调整。
更具体地说，且类似于图1所示及所述，介面材料14，例如SiO2，是沉积于基板10上及沟槽12内。介电材料16是在介面材料14上形成。介电材料16较佳为高k介电材料，例如HfO2，是通过ALD程序进行沉积；但其它沉积程序也在本发明的考量范围内，例如CVD或PECVD程序。介电材料16的沉积厚度可以是约1.5nm至约3nm；但其它尺寸也在本发明的考量范围内。在具体实施例中，介电材料16可经受后沉积退火程序。
再请参阅图6，阻障层18，例如MO TiN或PVD TiN，是在介电材料16上形成，接着是nFET金属，例如层件30(例如TiAlC、TaAlC、TiAl、Ti及Al)，以及覆盖层32，例如TiN层。层件18、30及32可通过常用的沉积程序，例如ALD，进行沉积。在具体实施例中，层件18可沉积约或更小的厚度，层件30可沉积约至的厚度，而层件32可沉积约1.5nm至3nm的厚度；但其它尺寸仍在本文的考量范围内。在沉积之后，层件18、30及32可通过常用的微影与蚀刻(RIE)程序制作图案，例如：自基板的pFET侧移除。此图案化程序会曝露位在基板的pFET侧的介电材料16。
位在pFET侧的层件18、30、32移除后，一层具有先驱物(例如：先驱物TiCl4及先驱物NH3或TiCl4与NH3先驱物的混合物)的TiN层22(又称为TiCl4TiN)是在基板的nFET侧的覆盖层32及pFET侧的介电层16上，以高温进行沉积。如前述，用于TiN层22(又称为TiCl4TiN)的先驱物为高温TiCl4，而且TiCl4TiN层22(又称为TiCl4TiN)可使用ALD或CVD程序以等于或高于约350℃的温度进行沉积，更佳为等于或高于约390℃，而更佳为约450℃。在附加或替代的具体实施例中，先驱物可以是TiCl4与NH3的混合型先驱物。
如本文中已说明，发明人已发现，TiN层22(又称为TiCl4TiN)会薄化(亦即，原子性蚀刻)下面的介电层16，在本具体实施例中，该介电层会位在基板的pFET侧。举例而言，发明人已发现，TiN层22(又称为TiCl4TiN)可自基板的pFET侧下面的介电层16蚀刻大约然而，nFET侧的介电层16仍会维持其原来的沉积厚度，如参考元件符号16a所表示的接面处所示。移除TiN层22(又称为TiCl4TiN)之后，可在该些程序后进行金属填充程序。
如发明人所发现，在使用本文所述程序的各具体实施例中，举TiN层22(又称为TiCl4TiN)为例，可发现Cl是内含于经沉积的TiN膜及介电材料16，但不具有C。相比之下，在使用具有NH3先驱物的MO TiN的常用的程序中，可发现C是内含于经沉积的TiN及介电材料16中。与具有Ti靶材及N2气体先驱物的常用的PVD TiN进一步比较，Cl(氯)、C(碳)或O(氧)无法在经沉积的TiN中发现，而C无法在下面的介电材料中发现。因此，本文所述的结构可通过注意Cl与C是否会在TiN中发现，或C是否会在下面的介电材料中发现，而与创作观点有所区别。在具体实施例中，高k材料可当作用于半导体装置的晶体管的栅极材料。
更具体地说，图7显示实施如本发明中所述的程序时，经沉积的TiCl4TiN中的Cl浓度。如图7所示，所示Cl浓度随着沉积温度从300℃升至450℃而降低。
图8根据本发明的态样，显示高温下沉积的MO TiN及TiCl4TiN进行后沉积的介电质厚度比较图。如图所示，与用于MO TiN的介电材料的无厚度损耗相比较，高温TiCl4TiN沉积后的介电质厚度损耗(即厚度)约为
图9显示TiCl4TiN的介电损耗(厚度损耗)与沉积温度的关系比较图。在此图中，y轴表示介电材料，例如HfO2，的损耗，而x轴表示TiCl4TiN的沉积温度。如此图所示，介电损耗随着沉积温度而增加。举例而言，沉积温度约390℃时出现约的介电损耗；而沉积温度约450℃时出现约的介电损耗。
上述该(些)方法是用于制造积体电路芯片。产生的积体电路芯片可由制造商以空白晶圆(亦即，具有多个未封装芯片的单一晶圆)、裸晶粒、或已封装等形式进行分配。在已封装的例子中，芯片是嵌装于单一芯片封装(诸如塑胶载体，具有黏贴至主机板或其它更高阶载体的引线)中，或多芯片封装(诸如具有表面互连或埋置型互连任一者或两者的陶瓷载体)中。在任一例子中，该芯片接着与其它芯片、离散电路元件、及/或其它信号处理装置整合成下列的部分或任一者：(a)诸如主机板的中间产品，或(b)最终产品。最终产品可以是包括积体电路芯片的任何产品，范围涵盖玩具及其它低阶应用至具有显示器、键盘或其它输入装置、及中央处理器的进阶电脑产品。
本发明的各项具体实施例已为了说明而介绍，但不是意味着穷举或受限于所揭示的具体实施例。许多修改及变例对本领域技术人员将会显而易见，但不会脱离所述具体实施例的范畴及精神。本文中选用的术语是为了最佳阐释具体实施例的原理、实际应用、或对市场现有技术的技术改进，或是为了让本领域技术人员能够理解本文中所揭示的具体实施例。

Claims (20)

1.一种方法，其包含：
在基板上沉积高k介电质；以及
直接在该高k介电质上沉积氮化钛膜，并同时蚀刻该高k介电质。
2.如权利要求1所述的方法，其中，该沉积该TiN更包括使用含有TiCl4的先驱物。
3.如权利要求2所述的方法，其中，该先驱物更包含NH3。
4.如权利要求2所述的方法，其中，该具有先驱物的TiN是以等于或高于约300℃的温度沉积。
5.如权利要求4所述的方法，其中，该具有先驱物的TiN是以约500℃的温度沉积。
6.如权利要求1所述的方法，其更包含在该蚀刻之前，先直接在pFET侧的该高k介电质上沉积材料，使得该材料阻止该具有先驱物的TiN直接在该pFET侧的该高k介电质上沉积，而且仅位在该基板的nFET侧的该高k介电质是通过使位在该nFET侧上的该高k介电质曝露至该具有先驱物的TiN来进行薄化。
7.如权利要求6所述的方法，其中，该材料是在该基板的该nFET侧上沉积，并且随后经移除以使位在该基板的该nFET侧的该高k介电质曝露，以便该具有先驱物的TiN直接在该nFET侧的该高k介电质上沉积。
8.如权利要求1所述的方法，其中，通过在该高k介电质的经曝露部分上沉积该具有先驱物的TiN，于该pFET侧及该nFET侧两者蚀刻该高k介电质。
9.如权利要求1所述的方法，其中，该高k介电质是HfO2。
10.一种方法，其包含：
在基板的pFET侧及nFET侧上沉积高k介电材料；以及
直接在该基板的该pFET侧及该nFET侧中至少一者的该高k介电材料上沉积具有TiCl4先驱物的氮化钛(TiN)，以薄化接触该TiCl4TiN的该高k介电材料。
11.如权利要求10所述的方法，其中，该先驱物更包含NH3。
12.如权利要求10所述的方法，其中，该高k介电质是HfO2。
13.如权利要求10所述的方法，其中，该TiN TiCl4是以等于或高于约300℃的温度沉积。
14.如权利要求13所述的方法，其中，该TiN TiCl4是以约500℃的温度沉积。
15.如权利要求10所述的方法，其更包含直接在该pFET侧的该高k介电材料上沉积材料，使得该材料阻止该TiCl4 TiN直接在该pFET侧的该高k介电质上沉积，而且仅位在该基板的该nFET侧的该高k介电质才进行薄化。
16.如权利要求15所述的方法，其中，该材料是在该基板的该nFET侧上沉积，并且随后经移除以曝露位在该基板的nFET侧的该高k介电质，以便该TiCl4 TiN仅薄化位在该nFET侧旳该高k介电质。
17.如权利要求10所述的方法，其中，该材料是TiN。
18.如权利要求10所述的方法，其中，通过位在该pFET侧及该nFET侧两者的该高k介电质的经曝露部分上沉积该TiCL4 TiN，于该pFET侧及该nFET侧两者蚀刻该高k介电质。
19.一种结构，其包含：
在基板上具有高k介电材料的nFET装置；以及
在该基板上具有该高k介电材料的pFET装置，
其中，该nFET装置及该pFET装置的至少一者的高k介电材料不具有C。
20.如权利要求19所述的结构，其中，位在该nFET装置与该pFET装置的该高k介电材料的厚度差仅介于约1埃与约3埃之间。
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