CN106601732A - Element lattice structure of fin type field effect transistor - Google Patents
Element lattice structure of fin type field effect transistor Download PDFInfo
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- CN106601732A CN106601732A CN201611191717.4A CN201611191717A CN106601732A CN 106601732 A CN106601732 A CN 106601732A CN 201611191717 A CN201611191717 A CN 201611191717A CN 106601732 A CN106601732 A CN 106601732A
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
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Abstract
Disclosed is an element lattice structure of fin type field effect transistor. The element lattice structure comprises multiple polysilicon lines in an element lattice and multiple fin-shaped oxidation diffusion areas in the element lattice. The polysilicon lines are horizontally configured and are averagely spaced through a picture of X. The fin-shaped oxidation diffusion areas are vertically configured and are averagely spaced through a pitch Y. The pitch Y of the fin-shaped oxidation diffusion areas defines a width of the element lattice. The element lattice structure further comprises multiple P-type and N-type metal oxide semiconductor transistors. These P-type and N-type metal oxide semiconductor transistors are provided with source nodes and drain nodes formed in the fin-shaped oxidation diffusion areas and grids connected with the polysilicon lines. These P-type and N-type metal oxide semiconductor transistors are connected together to form one or more complementary type metal-oxide semiconductor devices in the element lattice.
Description
Technical field
This disclosure relates generally to a kind of manufacture of semiconductor, and in particular to fin field-effect transistor
(FinFETs) element lattice structure.
Background technology
With the rapid progress of semi-conductor industry, CMOS (complementary
metal oxide semiconductor；CMOS) fin field-effect transistor (finfield-effect transistor；
FinFET) device receives an acclaim in many logics and other application.Therefore, fin field-effect transistor (FinFET) device is now
It is integrated in various forms and the semiconductor device that manufactured.Fin field effect transistor device generally comprises multiple high apertures
Fin-shaped oxide-diffused (oxidediffused；OD) region.Fin-shaped oxide-diffused region is formed perpendicular to the upper surface of substrate.
Fin-shaped oxide-diffused region defines action zone.Action zone is formed with the passage and regions and source/drain of CMOS transistor.One
As for, fin-shaped oxide-diffused region be insulation and projection three-dimensional (3D) structure.The grid of CMOS FinFET devices is formed at
The top of fin is simultaneously formed along the side of fin, to accumulate increased advantage with source/drain region surface using passage, is produced faster
The semiconductor transistor device of fast, more reliable and more preferable control.Polysilicon (Polycrystalline silicon；POLY)
Line is used to the grid for carrying control signal to CMOS transistor.In certain embodiments, grid can also be manufactured with POLY.
Element lattice are a kind of component structures, and its various CMOS realized using fin-shaped OD region and POLY lines in circuit is brilliant
Body pipe.Fin-shaped OD region is formed at the different layers on semiconductor substrate with POLY lines with orthogonal direction.In the process of circuit design
In, the height of element lattice is suitably chosen according to circuit, and the width of element lattice is according to the number of the CMOS device in element lattice
Amount is determined.The quantity of CMOS device is more, and the width of element lattice is bigger, so as to the area of element lattice is bigger.
The content of the invention
One embodiment of this disclosure is that, with regard to a kind of element lattice structure, which includes a plurality of polysilicon in element lattice
Line, multiple fin-shaped oxide-diffused regions and multiple P-type mos in element lattice in element lattice are brilliant
Body pipe and N-type metal oxide semiconductor transistor.Polysilicon lines are configured with first direction and with first segment between fifty-fifty
Every.Fin-shaped oxide-diffused region is configured with second direction and with second section away from being fifty-fifty spaced.Fin-shaped oxide-diffused region
Second section is away from the width for defining element lattice.The plurality of P-type mos transistor AND gate N-type metal-oxide half
Conductor transistor has the source node and drain node for being formed in corresponding fin-shaped oxide-diffused region, and is connected to phase
The grid of the polysilicon lines answered.The plurality of P-type mos transistor AND gate N-type metal-oxide semiconductor (MOS) crystal
Pipe is connected together to form one or more the CMOS devices in element lattice.
Description of the drawings
One or more embodiments are illustrated with examples, and are not limited, in the accompanying drawing of accompanying drawing, wherein with identical
The element of reference number title represents all similar components., it is emphasized that can according to industry multiple types latent structure standard practice
Not can draw to scale, and be only for example purpose and be used.In fact, the size of multiple types latent structure arbitrarily can increase in accompanying drawing
Add deduct few definition discussed with profit.
Figure 1A～1B is the example of two different elements lattice layouts depicted in some embodiments according to this disclosure
Property plane graph, the width of the wherein element lattice layout are defined by the pitch of POLY lines；
Fig. 2A～2B is two element lattice of Figure 1A～1B for being illustrated according to some embodiments of this disclosure respectively
The plane graph of the different examples of layout, the wherein width of the element lattice are defined by the pitch in fin-shaped OD region rather than POLY lines；
Fig. 3 A～3B is the exemplary elements lattice layout of the Fig. 2A depicted in some embodiments according to this disclosure
It is different to launch (folding) figure；
Fig. 4 A～4B is that the another of element lattice of Fig. 3 A～3B depicted in some embodiments according to this disclosure shows
The different expanded views of example property layout, wherein these devices are all connected together to form a CMOS inverter；
Fig. 5 A～5B is the exemplary layout of the element lattice of the Figure 1A depicted in some embodiments according to this disclosure
Different expanded views, wherein adjacent fin-shaped OD regional water level land is staggered and a specific range apart；
Fig. 6 A～6B is that the another of element lattice of Fig. 5 A～5B depicted in some embodiments according to this disclosure shows
The different expanded views of example property layout, wherein these devices are all joined together to form a CMOS inverter；And
Fig. 7 is that utilization one or more the FinFET devices depicted in some embodiments according to this disclosure form unit
The flow chart of the method for part lattice, the wherein width of the element lattice are determined by the pitch of the pitch in fin-shaped OD region rather than POLY lines
Justice.
Specific embodiment
Content disclosed below provides many different embodiments, for example, implement disclosed patent target different characteristic construction.Unit
Part is as discussed below with the particular example of arrangement to simplify this disclosure, and is not limited to by way of example only originally take off
Show content.For example, fisrt feature is formed in back segment narration fisrt feature and second feature may be included in second feature
It is the embodiment formed in directly contact mode, it is also possible to be formed between the first second feature comprising other features, so that first
And second feature may not be the embodiment of directly contact.In addition, the repeatable reference number of this disclosure and/or word be not in
In same example.This repetition is to simplify and clearly purpose and and non-limiting discussed different embodiments and/or matching somebody with somebody
Relation between putting.
In addition, the term with space correlation, for example " ... it is beneath ", " below ", " being less than ", " ... on ", it is " high
In " etc., in this can be used to the element that is briefly described in accompanying drawing and/or feature and another (or multiple) element and/or
The relation of feature.These also include in addition to comprising the direction shown in accompanying drawing with the term of space correlation and use and/or grasp
The different direction of the device in work.Device otherwise can orient (be for example rotated by 90 ° or in other directions) and
Used herein and space correlation descriptor is interpreted accordingly.It is to be understood that when an element is claimed " being connected to "
Or during " being coupled to " another element, this can be to be directly connected to or be coupled to other elements, or there are one or more medium elements.
According to some embodiments, fin-shaped oxide-diffused (the oxide diffused being used in element lattice structure；OD) area
Domain and polysilicon (polycrystalline silicon；POLY) line is spaced uniformly and fifty-fifty.A pair adjacent fin-shapeds
Interval between the adjacent POLY lines of the interval in OD regions or a pair be referred to as respectively the pitch in these fin-shaped OD regions or these
The pitch of POLY lines.In one embodiment, the width of element lattice can be multiplied by POLY lines in element lattice by the pitch of POLY lines
Quantity is defined, or is defined by the quantity that the pitch in fin-shaped OD region is multiplied by fin-shaped OD region in element lattice, as following
What is carried out discusses in detail.With the progress of manufacture of semiconductor technology, the pitch in fin-shaped OD region is persistently reduced, and in some realities
Apply in example, the pitch in fin-shaped OD region is less than the pitch of POLY lines.
According to some embodiments, width element lattice structure defined in fin-shaped OD region can be used to layout go out and
Produce semiconductor element lattice (cell grid)/circuit.Semiconductor element lattice/circuit has multiple utilization FinFET processing procedures institutes
CMOS (the complementary metal oxide semiconductor of making；CMOS) fill
Put.In this, the width of element lattice is determined by the quantity that the pitch in fin-shaped OD region is multiplied by fin-shaped OD region in element lattice.Work as fin
When the pitch in shape OD region is less than the pitch of POLY lines, if the CMOS device of equal number is realized out in element lattice, with fin-shaped
Defined in the pitch in OD regions, the width of element lattice is less than with the width of element lattice defined in the pitch of POLY lines.Such one
Come, as the height of element lattice has been fixed in circuit design, by using with unit defined in the pitch in fin-shaped OD region
Part lattice, the layout area of element lattice can be lowered.
For example, Figure 1A～1B is according to fin field-effect transistor (fin field-effect transistor；FinFET)
The plane graph of two different elements lattice layouts depicted in device topology, the width of the element lattice layout is by the section of POLY lines
Away from being defined.
For with 1A and 1B illustrated examples, polysilicon of each element lattice comprising a plurality of equispaced
(polycrystalline silicon；POLY) fin-shaped oxide-diffused (the oxide of line 102 and multiple equispaceds
diffused；OD) region 104.POLY lines 102 with first direction (for example：Vertically) configure.Fin-shaped OD region 104 is with second party
To (for example：Level) configuration.POLY lines 102 and fin-shaped OD region 104 substantially each other with orthogonal direction (for example：Vertical direction
Relative to horizontal direction) it is configured in the different layers of semiconductor substrate.Each element lattice include n type material 106 and P-type material 108.
N type material 106 is utilized to form multiple PMOS devices.P-type material 108 is utilized to form multiple NMOS devices.Two kinds of types
The material of formula is respectively displayed on the top and bottom of element lattice and is separated by separator bar 109.With 1A and 1B illustrated examples
For, the pitch of POLY lines 102 is the distance between center line of two adjacent POLY lines 102, and is represented with X.Similarly, fin-shaped
The pitch in OD regions 104 is the distance between the center line in two adjacent fin-shaped OD regions 104, and is represented with Y.In Figure 1A and figure
In the example of 1B, the ratio between X and Y is X=2Y.That is, the pitch in fin-shaped OD region 104 is the section of POLY lines 102
Away from half.
For Figure 1A examples, the height of element lattice is determined in circuit design process and generally in the layout of element lattice
During will not be changed, and the height of element lattice is equal to pitch Y in fin-shaped OD region 104 and is multiplied by equispaced in element lattice
The quantity in fin-shaped OD region 104.For Figure 1A examples, the height of element lattice is that (8 fin-shaped OD regions 104 and 4 are not for 12Y
11 intervals between the point 110 being occupied, add 1/2 interval of 2 tops and base for being located at element lattice, total to provide
Common 12Y).Note, based on the position of device in design rule and/or element lattice, some point/places 110 can not be by fin-shaped OD
Region 104 occupies (that is, the diffusion of not oxidized thing).In Figure 1A, the width of element lattice is taken advantage of equal to the pitch of POLY lines 102
The quantity of POLY lines 102 in upper element lattice.In this example, its be equal to 3X (2 between 3 POLY lines 102 intervals, plus
1/2 interval on upper 2 left sides and the right for being located at element lattice, to provide 3 intervals or pitch altogether), as shown in Figure 1A.Such as
This, as the area of the element lattice in X=2Y, therefore Figure 1A in this example is 3X × 12Y=18X2。
For the element lattice layout of another kind (different) example as shown in fig. 1b, although based on device in element lattice
Quantity and/or height, there are in the element lattice fin-shaped OD region 104 of lesser amt (in this example be 4), element lattice
Height predetermined and can be still calculated as 12Y (between 8 fin-shaped OD regions 104 and 4 points 110 not being occupied
11 intervals, add 1/2 interval of 2 tops and base for being located at element lattice, to provide 12Y altogether).The width of element lattice
Degree can also be decided to be 3X according to the quantity of POLY lines 102 in element lattice, and (2 intervals between 3 POLY lines 102, add 2
1/2 interval on the individual left side and the right positioned at element lattice, to provide 3 intervals or pitch altogether), as shown in Figure 1B.Thus,
Even if (this example is 8) Tu1BZhong for the example of 4, Figure 1A to have small number of fin-shaped OD region 104 in this example
The area of element lattice is mutually all 3X × 12Y=18X with the area of element lattice in Figure 1A2。
Fig. 2A shows the example layout with Figure 1A identical element lattice, but the width of element lattice is by with fin-shaped OD region 104
Pitch Y rather than pitch X of POLY lines 102 defined.The element lattice of Fig. 2A realize the element group identical transistor with Figure 1A
And device.However, from unlike the layout of the element lattice of Figure 1A, in present example, these fin-shaped OD regions 104 are
Vertically configure and stagger.Fin-shaped OD region 104 is vertically configured along horizontal direction (for example, X-direction).POLY lines 102
Compared to the fin-shaped OD region 104 (for example, X-direction) in horizontal direction, orthogonally (for example, Y direction) is arranged.Using this
Kind of layout type, the height of element lattice maintain identical and equal to POLY lines 102 pitch to be multiplied by element lattice between POLY lines 102
Pitch quantity (this example be 6).That is, 6X shown in the 2nd figure.However, the width of element lattice be now with
Position or the quantity institute of point that pitch Y in fin-shaped OD region 104 is occupied by one or more fin-shaped OD regions 104 in being multiplied by element lattice
Determine.Each point is equal to the width in a fin-shaped OD region 104 along the width of horizontal direction.For with Fig. 2A examples, with fin-shaped
Element lattice width defined in OD regions 104 is equal to 4Y (that is, between 3 between 4 staggered OD regions 104
Every add 2 left sides and the right for being located at element lattice 1/2 is spaced, to provide 4 intervals or pitch altogether).Each position
It is occupied forming 8 fin-shaped OD regions 104 altogether by the OD regions 104 of two vertical orientations.The OD areas of two vertical orientations
Domain 104 forms one group.Two 104 relative misalignments of OD regions of each group are in the OD regions of adjacent another group of two vertical orientations
104.Thus, being based on X=2Y, in Fig. 2A, the area of element lattice is 6X × 4Y=12X2.This is considerably smaller than Figure 1A similar elements
Layout area (the 18X of lattice2Relative to 12X2)。
For with Fig. 2A examples, when the height of element lattice is predetermined and generally will not in the layout process of element lattice
It is changed, the pitch for defining element lattice width and fin-shaped OD region 104 by the pitch with fin-shaped OD region 104 can be less than
The pitch of POLY lines 102, the layout area of element lattice can have and be significantly reduced.Multiple fin-shaped OD regions 104 can be identical
Horizontal level staggers to save the space of the point 110 not occupied by fin-shaped OD region 104 in Figure 1A.With another example
Speech, Fig. 2 B show the example layout with Figure 1B identical element lattice, but the width of element lattice is by with the pitch in fin-shaped OD region 104
Pitch X of Y rather than POLY lines 102 is defined.As the example of element lattice layout shown in Fig. 2 B is compared in Fig. 2A
Example has the fin-shaped OD region 104 of lesser amt (4 relative to 8), the width of the element lattice defined with fin-shaped OD region 104
Equal to 2Y (that is, 1 interval between 2 OD regions 104 staggered, adds 2 left sides and the right side for being located at element lattice
1/2 interval on side, to provide 2 intervals or pitch altogether).Thus, working as X=2Y, the area of element lattice is now equal to 6X × 2Y
=12X2.Compared to the layout of identical element lattice in Figure 1B, this causes the layout area of element lattice to have quite huge reduction
(18X2Relative to 6X2)。
Fig. 3 A and Fig. 3 B show that the different of the exemplary layout of the element lattice of Fig. 2A launch (folding) figure.Each element lattice
Width is defined with pitch Y in fin-shaped OD region 104.The layout of Fig. 3 A display element lattice, element lattice are comprising in element lattice
POLY lines, OD regions, cutting POLY (Cut-POLY), and vertical metal line.As shown in Figure 3A, POLY lines 102_1 is extremely
102_7 is configured to the horizontal line section of equispaced across element lattice.Fin-shaped OD region 104_1 to 104_4 is vertical across element lattice
Ground is arranged and is staggered in many horizontal levels.Electric lines of force 112 and 114 is to be respectively connecting to high voltage source VDD and low-voltage
The vertical metal line of source VSS.Vertical metal line 116 is used to the different device in connecting element lattice.
Fig. 3 B more show the multiple P-type mos (p-type for being implemented (or staggering) in element lattice
metal oxide semiconductor；PMOS) device 120 and multiple N-type metal-oxide semiconductor (MOS) (n-type
metal oxide semiconductor；NMOS device 122.As multiple PMOS or NMOS device can share identical
POLY lines 102, such as Fig. 3 B, multiple cutting POLY (CPOs) 118 are by multiple PMOS devices or NMOS device shared POLY lines
102 cut into multiple not connected line segments, so that each PMOS device 120 or NMOS device 122 have certainly in becoming element lattice
The self-contained unit of the POLY line line segments of body.CPOs118 is the POLY to cutting element, to will be multiple devices shared each
POLY lines 102 cut into detached fragment.As shown in Figure 3 B, each PMOS device 120 and NMOS device 122 have its grid
Pole, its grid are connected to wherein one POLY line (for example：Respectively 102_2,102_3,102_5 and 102_6), these POLY
Line carries input signal to corresponding grid.The source electrode and drain electrode of each PMOS and NMOS device is formed at corresponding fin-shaped
OD regions 104_1 to 104_8.In certain embodiments, the OD regions that the drain electrode of PMOS and NMOS device is located respectively by
POLY lines 102_1,102_4 and 102_7 connect.In certain embodiments, one or more PMOS devices 120 are (for example：
PMOS-3) and one or more NMOS devices 122 (for example：NMOS-1 a CMOS dress can) be joined together to form
Put 130.For a nonrestrictive example, as shown in Figure 3 B, by contact perforation 128 connect two OD regions 104 to
POLY line 102_4, PMOS device 120 is (for example：PMOS-3 drain electrode connection NMOS device 122) is (for example：NMOS-1 drain electrode).
The drain electrode of PMOS device 120 (PMOS-3) is formed at corresponding OD regions 104_1.NMOS device 120 is (for example：PMOS-3 leakage)
Pole is formed at corresponding OD regions 104_1.The drain electrode of NMOS device 122 (NMOS-1) is formed at corresponding OD regions 104_6.
In some embodiments, POLY line 102_3 and 102_5 carry the grid of input signal to PMOS-3 and NMOS-1 respectively.
POLY lines 102_3 and 102_5 can also be connected by connecting line (not shown), so that two devices are able to share a phase
Same input.In this manner, PMOS-3 and NMOS-1 can be connected by draining and be input into its grid
It is connected, to form CMOS device 130.The source electrode of the source electrode of PMOS-3 devices and NMOS-1 devices through corresponding CPO118 that
This insulation.The source electrode of PMOS-3 devices is formed at the OD regions 104_1 above PMOS-4 devices.The source electrode of NMOS-1 devices is formed
OD regions 104_6 below NMOS-1 devices.In certain embodiments, the source electrode of the source electrode and NMOS-1 of PMOS-3 is passed through
Conductive line segment or line (not shown) are respectively connecting to VDD and VSS.Extra CMOS device 130 can shape in a similar manner
Into in other to PMOS device 120 with NMOS device 122 (for example：PMOS-4 and NMOS-2) between.In addition, what is be appreciated that is
Drain electrode in PMOS device 120 and NMOS device 122, the different connections between source electrode and/or grid can according to demand shape
Into the CMOS device of multi-form.
Fig. 4 A～4B shows the different expanded view of another embodiment of the layout of the element lattice of Fig. 3 A～3B, to depict
How two or more PMOS devices can be abreast joined together to form a larger PMOS device, and two
Or how more NMOS devices can be abreast joined together to form a larger NMOS device.In Fig. 4 A～4B
POLY line 102_1 to 102_7 and OD region 104_1 to 104_8 are same as shown in Fig. 3 A～3B.Fig. 4 A are according to an embodiment
The layout of display element lattice.The layout shown by example compared to Fig. 3 A, the layout depicted in Fig. 4 A is also comprising level gold
Category line 124_1 to 124_6, which 112,114 and 116 can be contacted in different metal levels and by metal from vertical metal line/
Perforation 126 and be connected to vertical metal line 112,114 and 116.As shown in Figure 4 A, metal wire 116_1 passes through perforation 126_1 extremely
126_4 connects POLY line 102_2,102_3,102_5 and 102_6 respectively.These POLY lines carry input and fill to these PMOS
Put the grid of 120 and these NMOS devices 122.Thus, all of PMOS device 120 and NMOS device 122 share identical
Input.Similarly, metal wire 116_2 passes through perforation 126_5 to 126_8 respectively by horizontal metal wire 124_1,124_3,124_
4 and 124_6 link together.In certain embodiments, these horizontal metal wires according to circuit design/placement rules from
The drain electrode of PMOS device 120 and NMOS device 122 carries output.Thus, all of PMOS device 120 and NMOS device
122 shared identical outputs.Horizontal metal wire 124_2 and 124_5 pass through vertical metal line 112 and vertical metal line respectively
114 are connected to VDD and VSS.CPOs (Cut-POLYs) 118 is used to the specific POLY lines for terminating being shared by multiple devices
102.Due to the shared identical input now of multiple PMOS devices 120 and NMOS device 122, therefore compared to Fig. 3 A～3B's
Example (8 CPOs), Fig. 4 A and Fig. 4 B need small number of CPO118 (4 CPOs).
Fig. 4 B show the multiple PMOS devices 120 and NMOS device 122 for being implemented (and staggering) in element lattice, additional
POLY lines 102, fin-shaped OD region 104 and cutting POLYs118 in Fig. 4 A.In certain embodiments, it is two or more
PMOS device is (for example：PMOS-3 and PMOS-4) the drain electrode for being formed at its corresponding fin-shaped OD region 104_1 and 104_3
Can be by POLY lines 102_4 through the electric property coupling each other of perforation 128 is contacted, so that shared identical drain electrode (its of PMOS device
Source electrode can be connected to VDD perforation, for example：Horizontal metal wire 124_2 shown in Fig. 4 A).As PMOS device 120 is also shared
Identical be input into and export, as that described for the discussion of Fig. 4 A, its now in a parallel manner connection (that is, its
Share identical source electrode, drain electrode/output, and grid/input) forming a bigger PMOS device 132.PMOS device 132
Width be several times of width of single PMOS device 120.Note, in instead embodiment, PMOS device 120
Various between NMOS device 122 to be instead connected and form instead circuit and/or device according to demand, which is not
It is same as depicted specific connection in Fig. 4 B.For example, extra PMOS device is (for example：PMOS-1 and PMOS-2 and/or
The extra PMOS device not being shown) drain electrode can also be coupled to through extra (multiple) connecting element (not shown)
The drain electrode of PMOS-3 and PMOS-4 so that the shared identical drain electrode of all of PMOS device.
For example, in one embodiment, the length of the OD regions 104_2 by prolongation below POLY line 102_3,
Or take and the ground in generation by provide electric conductivity line segment (not shown) so that POLY line 102_3 are electrically connected to 102_4, PMOS-1
Drain electrode can be connected to the drain electrode of PMOS-3 and PMOS-4.The drain electrode of PMOS-1 is formed in and is intersected with POLY line 102_3
The lower half of fin-shaped OD region 104_2.In this example, as the drain electrode of PMOS-1 is also connected to PMOS-3 and PMOS-4
Grid, the drain electrode of PMOS-3 also can be connected by the grid that the drain electrode of PMOS-1 is connected to PMOS-3 and PMOS-4 with grid
Together, and also the drain electrode of PMOS-4 and grid can be linked together so that PMOS-3 and PMOS-4 are used as diode.
If this diode arrangement does not have demand, cutting-POLY118 (not shown) can be formed in OD regions 104_2 and POLY lines
Around the infall of 102_3, so that the grid of grid of the drain insulation of PMOS-1 in PMOS-3 and PMOS-4, so that
In the grid of PMOS-1 and the grid of PMOS-4 in the case where its corresponding drain electrode is not connected to, the drain electrode connection of PMOS-1
To the drain electrode and the drain electrode of PMOS-4 of PMOS-3.Similarly, the drain electrode of PMOS-2 is formed at the fin-shaped intersected with POLY line 102_3
The lower half of OD regions 104_4.By the length for extending the OD regions 104_4 under POLY line 102_3, or replace
POLY line 102_3 are connected to POLY line 102_4 by providing a wire line segment (not shown) by ground, can cause the drain electrode of PMOS-2
The drain electrode of PMOS-3 and PMOS-4 can be connected to.Note, as shown in Figure 4 B, by around fin-shaped OD region 104_4 with
The drain insulation of the cut-POLY118 of the infall of POLY line 102_3, PMOS-2 is in the grid of PMOS-3 and PMOS-4.Such as
This, connect the drain electrode of PMOS-2 to PMOS-3's and PMOS-4's drain electrode will not by PMOS-3 with PMOS-4 drain electrodes accordingly with
And grid is connected in diode arrangement.Discussed above describes exemplary connection, and which can be according to various different replacements
Embodiment and change.What is be appreciated that is that various different embodiments are not restricted to specific connection as above or are not restricted to
Shown in Fig. 4 B.
Similarly, through the mode similar in appearance to PMOS device 120 discussed above, two or more NMOS devices 122
Can also parallel mode connect to form a larger NMOS device 134.In certain embodiments, POLY lines 102_4 connects
Meet fin-shaped OD region 104_1,104_3,104_6 and 104_8.The drain electrode of PMOS device 120 and the drain electrode of NMOS device 122
It is formed together by perforation 128 so that all PMOS devices 120 and all NMOS devices 122 all share identical drain electrode.
As a result, two larger PMOS devices 132 and NMOS device 134 can form a CMOS device 136, be connected in its drain electrode
There is in the case of together identical to be input into and export.
In addition to occupying the too many space of element lattice, the example of the element lattice layout being illustrated in Figure 1A～1B may meet with
Meet another problem.The cause of this problem is that fin-shaped OD region 104 is configured in the way of extreme is close to each other horizontally.Fin-shaped OD
The pitch in region 104 is too little so that elements different in element lattice can not be cut or separate.
Fig. 5 A～5B shows a kind of a kind of different expansion of example of the layout of the element lattice of the Figure 1A for solving the above problems
Figure.The width of element lattice is defined by pitch X of POLY lines 102.Fig. 5 A are that the element lattice are shown according to some embodiments
Layout.In this example, POLY lines 102_1 to 102_4 is vertically configured and is fifty-fifty spaced, and multiple fin-shaped OD regions
Matched somebody with somebody with two adjacent groups (104_1,104_3,104_5 and 104_7) and (104_2,104_4,104_6 and 104_8)
Put, its each stagger and flatly it is apart one distance (for example：Pitch 2Y), as shown in Figure 5A.Have in fin OD region 104
Have under this horizontal displacement, any two close fin-shaped OD regions are (for example：104_1 and 104_3, or 104_2 and 104_4)
Between along the gap/separation on the position in horizontal direction be at least 2Y rather than Y, as shown in Figure 5A.Due to fin-shaped OD
Region is (for example：104_1 and 104_3) between have more spaces, therefore by CPO118 be arranged at positioned at fin-shaped OD region it
Between this space with by POLY lines (for example：It is possible 102_2) to cut into multiple not connected fragments.POLY lines are (for example：
102_2) shared by multiple PMOS devices 120 or multiple NMOS devices 122.As shown in Figure 5A, fin-shaped OD region 104 is this
Horizontal displacement is not resulted in is increased with the width of element lattice defined in the pitch of POLY lines 102, and equal to as shown in Figure 5A
3X, which is same as the width of the layout in Figure 1A.
Fig. 5 B show PMOS/NMOS devices 120/122 and POLY lines 102 additionally as shown in Figure 5A, fin-shaped OD region
104 and Cut-POLY118.As shown in Figure 5 B, each PMOS device 120 and NMOS device 122 have its grid, source electrode and
Drain electrode.Grid is connected to wherein one POLY line (for example：Respectively 102_2 and 102_3).Source electrode is formed at wherein with drain electrode
One fin-shaped OD region 104_1 to 104_8.In certain embodiments, the OD regions formed by the drain electrode of PMOS and NMOS point
Tong Guo not POLY lines 102_1 and 102_4 connection.Cut-POLYs (CPOs) 118 will be shared by multiple PMOS or NMOS device
POLY line 102_1 cut into multiple line segments so that each PMOS device 120 or NMOS device 122 become self-contained unit.It is independent
Device has itself POLY line line segment for input signal.In certain embodiments, one or more PMOS devices 120
(for example：PMOS-3) and one or more NMOS devices 122 (for example：NMOS-1 one can be joined together to form)
CMOS device 130.For a nonrestrictive example, as shown in Figure 5 B, by passing through contact perforation 128 by two OD regions
104_3 and 104_5 are connected to POLY line 102_1, and PMOS device 120 is (for example：PMOS-3) be formed in corresponding OD regions
The drain electrode of 104_3 is connected to NMOS device 122 (for example：NMOS-1 the drain electrode for being formed in corresponding OD regions 104_5).In addition,
In certain embodiments, by fin-shaped OD region 104_1 is correspondingly connected to POLY line 102_1 with 104_7, in Fig. 5 B
The drain electrode of PMOS-1 and NMOS-3 is also connected to each other and is connected to the drain electrode of PMOS-3 and NMOS-1.
In certain embodiments, the line segment of POLY lines 102_2 correspondingly carries input signal to PMOS-3 and NMOS-1
Grid.The line segment of POLY line 102_2 can also connect through connecting line segment (figure position shows) so that two devices can share phase
With input.In this fashion, the drain electrode of PMOS-3 and NMOS-1 is made to link together, make through connecting line segment (not shown)
The grid input of PMOS-3 and NMOS-1 links together, make the source electrode of PMOS-3 and NMOS-1 be respectively connecting to VDD and
VSS, PMOS-3 and NMOS-1 can form a CMOS device 130.Extra CMOS device 130 can shape in a similar manner
Into the PMOS device 120 in other to (pair) with NMOS device 122 (for example：PMOS-4 and NMOS-2).As described above with regard to
The discussion of Fig. 3 B and Fig. 4 B, according to various substituted embodiments, two or more PMOS devices 120 can be connected to each other,
Two or more NMOS devices 122 can be connected to each other, or, one or more PMOS devices can be connected to one or
More NMOS devices 122, create the CMOS device and circuit of various types in a variety of ways.It is appreciated that, it is various
Instead embodiment is not limited to particular exemplary connection above-mentioned discussed or that diagram is depicted.
Fig. 6 A～6B shows the various expanded views of another embodiment of element lattice layout in Fig. 5 A～5B, its illustrate two or
How more PMOS devices are joined together to form a larger PMOS device in a parallel manner, and illustrate two or
How more NMOS devices are joined together to form a larger NMOS device in a parallel manner.POLY in Fig. 6 A～6B
The layout of line 102_1 to 102_4 and OD regions 104_1 to 104_8 is same as shown in Fig. 5 A～5B.Fig. 6 A are implemented according to one
Example shows the layout of element lattice.The layout of the example compared to Fig. 5 A, the layout depicted in Fig. 6 A also include vertical metal
Line 116_1 to 116_5, which is located at the metal level that is different from horizontal metal wire 124 and can be connected to by contact/perforation 126
Horizontal metal wire 124 and POLY lines 102.As shown in Figure 6A, metal wire 124_5 through perforation 126 connect POLY lines 102_2 with
And 102_3, the grid of these POLY lines carrying inputs to the grid and NMOS device 122 of PMOS device 120.Thus, PMOS
Device 120 and the shared identical inputs of NMOS122.Similarly, vertical metal line 116_5 is connected to horizontal metal wire (for example：
One or more in 124_2 to 124_4 and 124_6 to 124_8).These horizontal metal wires are carried from PMOS device 120
Drain electrode and NMOS device 122 drain electrode output.Thus, PMOS device 120 and NMOS device 122 can share identical
Output/drain electrode.Horizontal metal wire 124_1 to 124_9 is correspondingly connected to VDD vertical metal line 116_1/116_2 and VSS
Vertical metal line 116_3/116_4.Cut-POLYs118 be utilized to cut off the POLY lines 102_1 that shared by multiple devices or
102_2.Because multiple PMOS devices 120 and/or multiple NMOS devices 122 shared identical input now, compared to 5A～B
The example (8 CPOs) of figure, the example of Fig. 6 A～6B need lesser amount of CPOs118 (2 CPO).
Fig. 6 B show multiple PMOS/NMOS devices additionally plus the POLY lines 102 shown in Fig. 6 A, fin-shaped OD region 104, cut
Cut POLY118 and vertical metal line 116.In certain embodiments, corresponding fin-shaped OD region 104_1 and 104_3 are formed at
Two or more PMOS devices (for example：PMOS_1 and PMOS_3) drain electrode can be by POLY lines 102_1 through connecing
Touch the electric property coupling each other of perforation 128 so that the shared identical drain electrode of these PMOS devices.The discussion of Fig. 5 B is relevant to as described above,
Its source electrode is connected to VDD.As these PMOS devices 120 also share identical input/grid and output/drain electrode, as described above
The discussion of Fig. 6 A is relevant to, these PMOS devices 120 connect (that is, its shared identical source now in a parallel manner
Pole, drain electrode/output and grid/input), to form a larger PMOS device 132.The width of PMOS device 132 is single
The width manyfold of one PMOS device 120.These NMOS devices 122 also can pass through similar mode and connect in a parallel manner
Connect to form a larger NMOS device 134.In certain embodiments, POLY lines 102_1 connects fin-shaped OD region (for example：
104_1,104_3,104_5 are with 104_7), the wherein drain electrode of these PMOS devices is linked together by contacting perforation 128, is made
Obtain these devices and all share identical drain electrode.Thus, two larger PMOS devices 132 can form one with NMOS device 134
Individual CMOS device 136, has identical input and output in the case where its drain electrode links together.
Fig. 7 is the flow chart of the method 700 to form element lattice, and the width of element lattice is by the pitch in fin-shaped OD region
Rather than POLY lines are defined.Although the reference markss of the element being shown in Fig. 2A～2B and Fig. 3 A～3B are used in following
Nonrestrictive example is to describe the step in Fig. 7, but method 700 is not limited to these examples or is not only restricted to these steps
Rapid particular order.
In step 702, multiple polysilicon (POLY) lines 102 are formed at element lattice, and POLY lines 102 are horizontally formed and to save
Fifty-fifty it is spaced away from X.
In step 704, multiple fin-shaped oxide-diffused (OD) regions 104 are formed at element lattice, and fin-shaped OD region 104 is vertically
Formed and be fifty-fifty spaced with pitch Y.Pitch Y in fin-shaped OD region 104 defines the width of element lattice.
In step 706, a same position of at least part of fin-shaped OD region 104 being vertically formed along horizontal direction
Vertically stagger.
In step 708, multiple PMOS transistors 120 and nmos pass transistor 122 are formed at element lattice.PMOS transistor
120 and nmos pass transistor 122 have its source node, drain node and grid.PMOS120 transistors and NMOS crystal
The source node of pipe 122 is formed at fin-shaped OD region 104 with drain node.PMOS120 transistors and nmos pass transistor 122
Grid is connected to corresponding POLY lines 102.
In step 710, these PMOS transistors 120 and these nmos pass transistors 122 are joined together to form element
One or more CMOS devices in lattice.
In certain embodiments, a kind of element lattice structure includes a plurality of polysilicon (POLY) line in element lattice and many
Individual fin-shaped oxide-diffused (OD) region in element lattice.Polysilicon lines are configured with first direction and with first segment between fifty-fifty
Every.Fin-shaped oxide-diffused region is configured with second direction and with second section away from being fifty-fifty spaced.The of fin-shaped oxide-diffused region
Two pitches define the width of element lattice.Element lattice structure is also comprising multiple PMOS transistors in element lattice and NMOS crystal
Pipe.These PMOS transistors and nmos pass transistor have source node and the drain electrode being formed in fin-shaped oxide-diffused region
Node, and it is connected to the grid of corresponding polysilicon lines.These PMOS transistors are connected together with nmos pass transistor with shape
Into one or more CMOS devices in element lattice.
In certain embodiments, the second section in fin-shaped OD region away from less than POLY lines first segment away from.
In certain embodiments, the width of element lattice by the second section in fin-shaped OD region away from being multiplied by fin-shaped OD area in element lattice
The quantity in domain is determined.
In certain embodiments, the height of element lattice is predetermined.
In certain embodiments, at least part of fin-shaped OD region staggers identical on first direction in a second direction
Position.
In certain embodiments, each CMOS device drains and at least one by connect at least one PMOS device one
One drain electrode of NMOS device, and be input into and an at least NMOS device by connecting a grid of an at least PMOS device
One grid is input into and is formed.
In certain embodiments, element lattice structure also includes an at least POLY wire cutting elements.POLY wire cuttings element is used
To cut at least one in a plurality of POLY lines so that it is one only that at least one PMOS device or NMOS device become in element lattice
Vertical device.POLY lines are shared by multiple PMOS or NMOS device.
In certain embodiments, two or more PMOS devices abreast connect to form a larger PMOS dress
Put.Two or more NMOS devices abreast connect to form a larger NMOS device.
In certain embodiments, parallel connected PMOS device and NMOS device form a larger CMOS device.
In certain embodiments, a kind of element lattice structure includes a plurality of polysilicon (POLY) line in element lattice and many
Individual fin-shaped oxide-diffused (OD) region in element lattice.Polysilicon lines are configured with second direction and with first segment between fifty-fifty
Every.Fin-shaped oxide-diffused region is configured with first direction and with second section away from being fifty-fifty spaced.Adjacent fin-shaped oxide-diffused area
Stagger and a flatly distance apart in domain.Element lattice structure also includes multiple PMOS transistors and NMOS in element lattice
Transistor.These PMOS transistors and nmos pass transistor have the source node that is formed in fin-shaped oxide-diffused region and
Drain node, and it is connected to the grid of corresponding polysilicon lines.These PMOS transistors and nmos pass transistor are mutually connected in one
Rise to form one or more CMOS devices in element lattice.
In certain embodiments, the space between any two most close fin-shaped OD regions of any point is gone up in the first direction
Second section away from least twice.
In certain embodiments, one or more POLY wire cuttings elements are configured in two most close fin-shaped OD areas
Between domain and to cut the POLY shared by multiple PMOS devices or NMOS device so that these devices become and are kept completely separate
Device.
In certain embodiments, two or more PMOS devices are joined together to form a larger PMOS dress
Put.Two or more NMOS devices abreast connect to form a larger NMOS device.
In certain embodiments, parallel connected PMOS device and NMOS device form a larger CMOS device.
In certain embodiments, a kind of method is included：Form a plurality of polysilicon (POLY) line and shape in element lattice
Into multiple fin-shaped oxide-diffused (OD) regions in element lattice.Polysilicon lines are configured with first direction and equal with first segment anomaly
Ground interval.Fin-shaped oxide-diffused region is configured with second direction and with second section away from being fifty-fifty spaced.Fin-shaped oxide-diffused region
Second section away from the width for defining element lattice, and the second section in fin-shaped oxide-diffused region is away from the first segment less than POLY lines
Away from.Method is also comprising forming multiple PMOS transistors in element lattice and nmos pass transistor and be connected these PMOS transistors
With nmos pass transistor forming multiple CMOS devices detached in element lattice.These PMOS transistors and nmos pass transistor tool
There are the source node and drain node being formed in fin-shaped oxide-diffused region, and the grid for being connected to corresponding polysilicon lines
Pole.
In certain embodiments, method is also included：By by the second section in fin-shaped OD region away from being multiplied by fin-shaped in element lattice
The quantity in OD regions determines the width of element lattice.
In certain embodiments, method is also included：Stagger at least part of fin-shaped OD region in second direction in first
Same position on direction.
In certain embodiments, method is also included：By connect the corresponding grid input of an at least PMOS device with extremely
The corresponding grid input of a few NMOS device, and connect the corresponding drain node of an at least PMOS device with this at least
The corresponding grid drain electrode node of one NMOS device.
In certain embodiments, method is also included：Form an at least POLY wire cutting elements.POLY wire cuttings element to
At least one of cutting POLY lines.POLY lines are shared by multiple PMOS or NMOS device so that in PMOS or NMOS device
At least one becomes the self-contained unit in element lattice.
In certain embodiments, method is also included：Connect the input of these PMOS devices in a parallel manner and with flat
Capable mode connects the output of these PMOS devices, to form a larger PMOS device；Connect these in a parallel manner
The input of NMOS device and connect the output of these NMOS devices in a parallel manner, to form a larger NMOS dress
Put.
Although this announcement is described through exemplary embodiment, this announcement is not only restricted to this.More precisely,
Appended claims can by the usual skill of technical field the scope that discloses without prejudice to this and its equivalency range feelings
Largo explain under condition, with comprising other changes and this embodiments of the disclosure.
Claims (1)
1. a kind of element lattice structure, it is characterised in that include：
The a plurality of polysilicon lines in the element lattice, wherein a plurality of polysilicon lines are configured with a first direction and with one first
Pitch is fifty-fifty spaced；
Multiple fin-shaped oxide-diffused regions in the element lattice, wherein the plurality of fin-shaped oxide-diffused region is with a second party
To configuration and with a second section away from being fifty-fifty spaced, wherein the second section in the plurality of fin-shaped oxide-diffused region is away from defining
The width of the element lattice；And
Multiple P-type mos transistor AND gate N-type metal oxide semiconductor transistors in the element lattice, its
Described in the plurality of N-type metal oxide semiconductor transistor of multiple P-type mos transistor AND gates there is shape
Into source node and drain node in corresponding fin-shaped oxide-diffused region, and the grid for being connected to corresponding polysilicon lines
Pole,
The plurality of N-type metal oxide semiconductor transistor of wherein the plurality of P-type mos transistor AND gate
It is connected together to form one or more the CMOS devices in the element lattice.
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