CN102831254A - Batch design method of layout of MOS (metal oxide semiconductor) device - Google Patents
Batch design method of layout of MOS (metal oxide semiconductor) device Download PDFInfo
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Abstract
The invention provides a batch design method of a layout of an MOS (metal oxide semiconductor) device. The batch design method comprises the following steps; determining the shape and size of a grid layer; determining the shape and size of an active region layer by using the grid layer as a self-variable; determining the shapes and sizes of an injection layer and a trap layer by using the active region layer as the self-variable; determining the shape and size of a through hole by using the grid layer and the active region layer as the self-variable; and determining the shape and size of a metal layer by using the through hole as the self-variable. According to the batch design method of the structure of an MOS tube, the problem of efficiently designing a lot of layouts is solved under the condition of more requirements on size of the device and more variables on size of the device, so that the error rate in the process of designing the layout manually is reduced, and the designing time of layout is shortened.
Description
Technical field
The present invention relates to a kind of MOS element layout mass method for designing, particularly relate to a kind of use SMARTCELL software three kinds of MOS element layout mass methods for designing.
Background technology
The layout design of semiconductor devices is that chip prepares one of important step the most.Domain is corresponding to the geometric combination of semiconductor device structure, thereby the concrete structure of the chip of having confirmed to prepare; These geometric figures are made up of the different graphic layer of representing with the different patterns pattern; And the different graphic layer is corresponding to different process steps; Therefore domain has determined the technology manufacturing process of concrete device architecture, we can say that layout design is that internal connection with semiconductor devices itself converts the domain form to and representes.
In layout design; To observe the layout design rules that technology manufacturer provides; Layout design rules is according to handicraft product actual process level and yield rate requirement in normal working conditions, the restriction of physical dimension between one group of same process layer of setting itself and the process layer.The layout design of MOS device also will be observed certain layout design rules.
Current large scale integrated circuit is normally realized by metal-oxide semiconductor fieldeffect transistor (MOSFET); MOSFET roughly can comprise following several kinds of basic structures: buoyancy aid MOS device (Floating Body MOS; FBMOS), be the simplest MOS device, symmetry source electrode and drain electrode on the grid both sides; Utilize grid that source electrode and drain electrode are separated, grid, source electrode and drain electrode three ends are drawn; (Body Tied to Source MOS BTSMOS), is connected the source end body contact MOS device with the body end, end is drawn from the source jointly; Side lead body contact MOS device (Side Body Tied to Source MOS, SBTSMOS), the end both sides symmetric body end structure in the source is connected with the body end, and end is drawn from the source jointly.Though it is thus clear that be both the MOS structure, four electrode connection modes differences of source drain-gate body and each region area, the degree of depth be difference all, the domain that causes thus is also totally different.
Though existing layout design method can satisfy present device size designing requirement, under the many situation of device size, efficient can reduce, simultaneously because artificial manual operations can produce unnecessary mistake to designs.Therefore, device size is being required under the situation more, that the device size variable is more (like above-mentioned three kinds of MOS), traditional element layout design can not better meet the high-level efficiency of designs, the requirement of low error rate.
Summary of the invention
Therefore; The object of the present invention is to provide a kind of method of MOS element layout mass design; To solve under the situation that the device dimensional requirement is more, the device size variable is more; The efficient problem of accomplishing a large amount of layout design, thus the error rate that produces in the artificial design layout process reduced, and shorten the layout design time.
For this reason, the invention provides a kind of method of MOS element layout mass design, comprising: the shape and size of confirming grid layer; With the grid layer is independent variable, defines the shape and size of source region layer; With the active region layer is independent variable, confirms the shape and size of input horizon, trap layer; With grid layer and active region layer is independent variable, confirms the shape and size of through hole; And be independent variable with the through hole, confirm the shape and size of metal level.
Wherein, the length of through hole and width are all less than the length and the width of grid layer and/or active region layer.Wherein, the length of metal level and width be greater than the length and the width of through hole, and the length of metal level and width are less than the length and the width of grid layer and/or active region layer.
Wherein, active region layer is symmetrically distributed in the both sides of grid layer, and the width of active region layer is greater than the width of grid layer, and the length of active region layer is less than the length of grid layer.Wherein, the width of input horizon and length is all greater than the width and the length of active region layer, and the width of trap layer and length are all greater than the width and the length of input horizon.
Wherein, The active region layer asymmetric distribution is in the both sides of grid layer; The width of active region layer is greater than the width of grid layer; And the length of active region layer is less than the length of grid layer, and active region layer comprises source electrode active region layer and the body utmost point active region layer that is positioned at grid layer one side, and the drain electrode active region layer that is positioned at the grid layer opposite side.
Wherein, drain electrode active region layer, source electrode active region layer and body utmost point active region layer equal in length, the width of source electrode active region layer equal the to drain width of active region layer, the width of body utmost point active region layer is less than source electrode active region layer and/or drain electrode active region layer.Wherein, Input horizon comprises the first kind input horizon and the second type input horizon; The length of first kind input horizon, the second type input horizon is all greater than the length of active region layer; The first kind input horizon and the second type input horizon width sum are greater than the width of active region layer, and body utmost point active region layer is positioned at the second type input horizon, and the source electrode active region layer is positioned at first kind input horizon with the drain electrode active region layer; The width of trap layer is greater than the width sum of the first kind input horizon and the second type input horizon, and the length of trap layer is greater than the length of the first kind input horizon or the second type input horizon.
Wherein, drain electrode active region layer, source electrode active region layer and body utmost point active region layer width equate that the length of drain electrode active region layer equals source electrode active area length and body utmost point active region layer length sum.Wherein, Input horizon comprises source electrode first kind input horizon, drain electrode first kind input horizon and the second type input horizon; Drain electrode first kind input horizon width, source electrode first kind input horizon equates with the second type input horizon width and all greater than draining or source electrode active region layer width; Drain electrode first kind input horizon length equals the source electrode first kind input horizon length and the second type input horizon length sum; The length of trap layer is greater than drain electrode first kind input horizon length, and the width of trap layer is greater than drain electrode first kind input horizon width and source electrode first kind input horizon width sum.
According to metal-oxide-semiconductor structure mass method for designing of the present invention; With the grid being is that independent variable is confirmed input horizon and trap layer with the active area again after independent variable defines the source region; All can unify to import layout design rules and initial gate parameters can be accomplished multiple metal-oxide-semiconductor layout design automatically for different MOS structures; Solve under the situation that the device dimensional requirement is more, the device size variable is more; The efficient problem of accomplishing a large amount of layout design, thus the error rate that produces in the artificial design layout process reduced, and shorten the layout design time.
Purpose according to the invention, and in these other unlisted purposes, in the scope of the application's independent claims, be able to satisfy.Embodiments of the invention are limited in the independent claims, and concrete characteristic is limited in its dependent claims.
Description of drawings
Followingly specify technical scheme of the present invention with reference to accompanying drawing, wherein:
Fig. 1 has shown the top view of FBMOS;
Fig. 2 has shown the top view of BTSMOS;
Fig. 3 has shown the top view of SBTSMOS; And
Fig. 4 has shown the top view that MOS device three end through holes are drawn.
Reference numeral
101 grid layers
102 active areas
102S source electrode active area 102D drain electrode active area 102B body utmost point active area 103 first kind input horizons
103S source electrode first kind input horizon 103D drain electrode first kind input horizon 104 trap layers
105 second type input horizons
106 first through holes
107 second through holes
108 the first metal layers
109 second metal levels
Embodiment
Following with reference to accompanying drawing and combine schematic embodiment to specify the characteristic and the technique effect thereof of technical scheme of the present invention, method is disclosed.It is pointed out that structure like the similar Reference numeral representation class, used term " first " among the application, " second ", " on ", D score or the like can be used for modifying various device architectures or processing step.These are modified is not space, order or the hierarchical relationship of hint institute's modification device architecture or processing step unless stated otherwise.
Be depicted as the domain top view of three kinds of different MOS respectively like Fig. 1, Fig. 2, Fig. 3, Fig. 1 is buoyancy aid MOS device architecture figure, and Fig. 2 is body contact MOS device architecture figure, and Fig. 3 is side lead body contact MOS device architecture figure.Three kinds of metal-oxide-semiconductors all are produced on the trap layer 104 that is arranged in the substrate (not shown), comprise source electrode (source) 102S, drain electrode (drain) 102D and 101 3 electrodes of grid (gate), and the size in grid layer 101 zones can be represented the size of metal-oxide-semiconductor size in the domain.Grid is kept apart source electrode and drain electrode, correspondingly is shown as grid layer 101 in the drawings active region layer 102 is divided into two parts, and one of them is equivalent to source region 102S, and another then is equivalent to drain region 102D.
When forming these device architectures,, same process layer itself is carried out the minimum dimension restriction, to carrying out the minimum dimension restriction between the different process layer according to layout design rules.Different variablees according to variety classes MOS requirement on devices carry out parameter-definition, as giving initial value with active area width in grid width, gate length, the BTS, make it become the parameter amount in the later stage layout design.Carry out the basic engineering introduction in the face of three kinds of MOS devices down.
With reference to accompanying drawing 1, be the domain of FBMOS.Sequencing according to actual fabrication; Its common technology is made flow process and is comprised: form first kind input horizon 103 in the trap layer 104; According to PMOS and NMOS active area, the channel region type is different and be provided with, for example the trap layer 104 of PMOS is the n type, first kind input horizon 103 is the p type; The trap layer 104 of NMOS is the p type, and first kind input horizon 103 is the n type; In first kind input horizon 103, be formed with source region layer 102; On first kind input horizon 103, active region layer 102, form grid layer 101, grid layer 101 is divided into two zones symmetry, that area equates with active region layer 102, is respectively source region 102S and drain region 102D.
Yet these regional layout design orders also are that definite process of each regional shape, size but is different from above-mentioned actual manufacturing sequence.Particularly, the layout design method for these zoness of different comprises following each step:
At first, confirm the shape and size of grid layer.Need according to the MOS electric properties of devices; For example threshold voltage control, resistance, channel region length or the like; Confirm the geometric configuration and the dimensional parameters of grid layer 101, also promptly select the width and the length of suitable grid layer 101, the domain of the grid layer 101 of the rectangle that draws.Usually, the width of grid layer 101 has determined the characteristic of the large scale integrated circuit of device and formation thereof, therefore is also referred to as characteristic dimension.In the present invention, width refers to the distance on the horizontal direction in the accompanying drawing, and length refers to the distance on the vertical direction, below all similar, repeat no more.
Secondly, according to layout design rules, confirm with the grid layer to be the shape and size of the active region layer of independent variable.Also, confirm position, the shape and size of the active region layer 102 of variation along with the shape and size variation of grid layer 101 promptly according to the geometric relationship between active region layer 102 borders and grid layer 101 structures.Particularly, for FBMOS, the domain of active region layer 102 is a rectangle also, is symmetrically distributed in the both sides of grid layer 101, and the width of active region layer 102 is greater than the width of grid layer 101, and the length of active region layer 102 is less than the length of grid layer 101.Can use SMARTCELL software to come Aided Design; Also promptly import after the layout design rules; According to the position of grid layer, shape and size automatically adjustment be provided with source region layer 102, for example in SmartCell software among the Cell Design, to the device variable; Insert as required like active area width in grid width, gate length, the BTS, then system generates the MOS device architecture under the different variable condition groups automatically.Each following step design also all can adopt this software auxiliary, repeats no more.
Then, according to layout design rules, confirm with the active region layer to be the input horizon of independent variable, the shape and size of trap layer.Confirm that shape and size along with active region layer 102 change and the first kind input horizon 103 that changes and position, the shape and size of trap layer 104 also promptly respectively and the geometric relationship between active region layer 102 structures, according to first kind input horizon 103 borders and trap layer 104 border.Particularly; For FBMOS; First kind input horizon 103 is rectangle with trap layer 104; The width of first kind input horizon 103 and length is all greater than the width and the length of active region layer 102, trap layer 104 width and length all greater than the width and the length of first kind input horizon 103, the interval between interval between first kind input horizon 103 and the active region layer 102 and trap layer 104 and the first kind input horizon 103 needs according to MOS device electric property and decides.
Then, as shown in Figure 4, on grid layer 101 and source-drain area 102S/D, delimit the via regions that is used to contact according to the needs of contact resistance, be the shape and size that independent variable is confirmed first through hole 106 with active region layer 102 promptly also with grid layer 101.Wherein, first through hole 106 is a plurality of rectangles or square, and the length of first through hole 106 and width be all less than the length and the width of grid layer 101, and less than length and the width of source region 102S in the active region layer 102 or drain region 102D.
At last, with the through hole be the shape and size that independent variable is confirmed metal level.Particularly, the first metal layer 108 is a rectangle, and its length and width be greater than the length and the width of first through hole 106, and less than the length of grid layer 101 and width and less than length and the width of source region 102S in the active region layer 102 or drain region 102D.
So far, the layout design of the FBMOS of single layer of interconnects is accomplished.
The domain that has below only shown single layer of interconnects; For the MOS device that needs multilayer interconnection; Can also on the first metal layer 108, be formed with second through hole 107 on the layout design, and on second through hole 107, form second metal level 109, wherein; Second through hole 107 is rectangle and its length and width length and the width less than the first metal layer 108, and the length of second metal level 109 and width are greater than the length of second through hole 107 and width and less than the length and the width of the first metal layer 108.
Embodiment 2 BTSMOS
With reference to accompanying drawing 2, be the domain of BTSMOS.Sequencing according to actual fabrication; Its common technology is made flow process and is comprised: form first kind input horizon 103 in the trap layer 104; According to PMOS and NMOS active area, the channel region type is different and be provided with; For example the trap layer 104 of PMOS is that n type, first kind input horizon 103 are the p type, and the trap layer 104 of NMOS is that p type, first kind input horizon 103 are the n type; In trap layer 104, form the second type input horizon 105, it is opposite with the first kind to inject type, is used for the substrate biasing and is provided with; In the first kind input horizon 103 and the second type input horizon 105, be formed with source region layer 102; On first kind input horizon 103, active region layer 102, form grid layer 101, grid layer 101 is divided into asymmetrical, unequal two zones of area with active region layer 102, is respectively source region 102S and drain region 102D.
The operation of the domain method for making of BTMOS and the difference of embodiment 1 be the relation of the mutual alignment between active area 102 and first kind input horizon 103, the second type input horizon 105 only, and be specific as follows:
At first, confirm the shape and size of grid layer, similar with embodiment 1, repeat no more.
Secondly, according to layout design rules, confirm with the grid layer to be the shape and size of the active region layer of independent variable.Also, confirm position, the shape and size of the active region layer 102 of variation along with the shape and size variation of grid layer 101 promptly according to the geometric relationship between active region layer 102 borders and grid layer 101 structures.Particularly, for BTSMOS, the domain of active region layer 102 also is a rectangle, and asymmetric distribution is in the both sides of grid layer 101, and the width of active region layer 102 is greater than the width of grid layer 101, and the length of active region layer 102 is less than the length of grid layer 101.The part that active region layer 102 is positioned at grid layer 101 left sides is source region 102S; The right side is drain region 102D; The width of source region 102S is greater than the width of drain region 102D, and its part that exceeds drain region 102D width is body utmost point active area 102B, and its width may be defined as custom variable " active area width in the BTS "; This part will be positioned at the second type input horizon 105 in the tagma that forms after a while, rather than source region 102S all is positioned at first kind input horizon 103 shown in the embodiment 1.At this moment, the operation of the active area in drain region, source area, tagma is accomplished.
Then, according to layout design rules, confirm with the active region layer to be the input horizon of independent variable, the shape and size of trap layer.Confirm that shape and size along with active region layer 102 change and position, the shape and size of the first kind input horizon 103, the second type input horizon 105 and the trap layer 104 that change also promptly respectively and the geometric relationship between active region layer 102 structures, according to the border of first kind input horizon 103, the second type input horizon 105 and trap layer 104 border.Particularly; For BTSMOS; First kind input horizon 103, the second type input horizon 105 and trap layer 104 are rectangle; All greater than the length of active region layer 102, first kind input horizon 103 and the second type input horizon, 105 width sums are greater than the width of active region layer 102 for the length of first kind input horizon 103, the second type input horizon 105, and the width that source region 102S is positioned at the second type input horizon 105 is above-mentioned custom variable " BTS active area width ".The width of trap layer 104 is more than or equal to the width sum of the first kind input horizon 103 and the second type input horizon 105, and its length is more than or equal to the length of the first kind input horizon 103 or the second type input horizon 105.Interval between interval between first kind input horizon 103, the second type input horizon 105 and the active region layer 102 and trap layer 104 and first kind input horizon 103, the second type input horizon 105 needs according to MOS device electric property and decides.
After this with embodiment 1 similarly, on grid layer 101, source region 102S, drain region 102D, form the domain of through hole 106,107 and metal level 108,109 successively, repeat no more.
Embodiment 3 SBTSMOS
With reference to accompanying drawing 3, be the domain of SBTSMOS.Sequencing according to actual fabrication; Its common technology is made flow process and is comprised: form first kind input horizon 103 in the trap layer 104; According to PMOS and NMOS active area, the channel region type is different and be provided with; For example the trap layer 104 of PMOS is that n type, first kind input horizon 103 are the p type, and the trap layer 104 of NMOS is that p type, first kind input horizon 103 are the n type; In trap layer 104, form the second type input horizon 105, it is opposite with the first kind to inject type, is used for the substrate biasing and is provided with; In the first kind input horizon 103 and the second type input horizon 105, be formed with source region layer 102; On first kind input horizon 103, active region layer 102, form grid layer 101, grid layer 101 is divided into three zones with active region layer 102, is respectively source region 102S, tagma 102B and drain region 102D.
The operation of the domain method for making of SBTSMOS and the difference of embodiment 1 be the relation of the mutual alignment between active area 102 and first kind input horizon 103, the second type input horizon 105 only, and be specific as follows:
At first, confirm the shape and size of grid layer, similar with embodiment 1, repeat no more.
Secondly, according to layout design rules, confirm with the grid layer to be the shape and size of the active region layer of independent variable.Also, confirm position, the shape and size of the active region layer 102 of variation along with the shape and size variation of grid layer 101 promptly according to the geometric relationship between active region layer 102 borders and grid layer 101 structures.Particularly; For SBTSMOS, the domain of active region layer 102 is a rectangle also, is divided into the both sides that three parts asymmetricly are distributed in grid layer 101; The width of active region layer 102 is greater than the width of grid layer 101, and the length of active region layer 102 is less than the length of grid layer 101.The part that active region layer 102 is positioned at grid layer 101 left sides is drain region 102D, and the right side is source region 102S and tagma 102B, and wherein tagma 102B is different with embodiment 1, will be formed in the second type input horizon 105, is used for the substrate biasing.Drain electrode active area 102D and grid width parallel direction distance are followed requirement in the layout design rules; Drain electrode active area 102D keeps identical with gate length parallel direction and tagma active area 102B outermost edge; Tagma 102B width equates that with source region 102S tagma 102B and source region 102S length sum equal the length of drain region 102D.It should be noted that; Often need increase grid 101 width in the SBTSMOS domain; The minor increment of the grid width that increases satisfies that grid exceed in the layout design rules (along the vertical paper direction that makes progress) active area (in the real manufacture process, deposition grid or when on gate insulation layer, depositing etching again and forming grid, the height of grid has certain related with its width in the interlayer dielectric layer opening; If width is too narrow; Bad or the etching precision reduction of the step coverage of deposition cause the height of grid not reach designing requirement, so grid width must surpass the certain limit under the corresponding technology).
Then, according to layout design rules, confirm with the active region layer to be the input horizon of independent variable, the shape and size of trap layer.Confirm that shape and size along with active region layer 102 change and position, the shape and size of the first kind input horizon 103, the second type input horizon 105 and the trap layer 104 that change also promptly respectively and the geometric relationship between active region layer 102 each structures, according to the border of first kind input horizon 103, the second type input horizon 105 and trap layer 104 border.Particularly; For SBTSMOS; First kind input horizon 103, the second type input horizon 105 and trap layer 104 are rectangle; First kind input horizon 103 comprises two parts that are distributed in grid layer 101 both sides---source electrode first kind input horizon 103S and drain electrode first kind input horizon 103D; Drain electrode first kind input horizon 103D length and width be all greater than the active area 102D that drains, and less than source electrode active area 102S length, the second type input horizon, 105 width equal source electrode first kind input horizon 103S and the length first kind input horizon 103D that equals to drain to source electrode first kind input horizon 103S width greater than source electrode active area 102S and its length.The width of trap layer 104 is more than or equal to the width sum of the first kind input horizon 103 and the second type input horizon 105, and its length is more than or equal to the length of the first kind input horizon 103 or the second type input horizon 105.Interval between interval between first kind input horizon 103, the second type input horizon 105 and the active region layer 102 and trap layer 104 and first kind input horizon 103, the second type input horizon 105 needs according to MOS device electric property and decides.
After this with embodiment 1 similarly, on grid layer 101, source region 102S, drain region 102D, form the domain of through hole 106,107 and metal level 108,109 successively, repeat no more.
More than be provided by the present invention a kind of to three kinds of metal-oxide-semiconductor structure mass methods for designing.
According to metal-oxide-semiconductor structure mass method for designing of the present invention; With the grid being is that independent variable is confirmed input horizon and trap layer with the active area again after independent variable defines the source region; All can unify to import layout design rules and initial gate parameters can be accomplished multiple metal-oxide-semiconductor layout design automatically for different MOS structures; Solve under the situation that the device dimensional requirement is more, the device size variable is more; The efficient problem of accomplishing a large amount of layout design, thus the error rate that produces in the artificial design layout process reduced, and shorten the layout design time.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and various suitable changes and equivalents are made in technological process.In addition, can make by disclosed instruction and manyly possibly be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, the object of the invention does not lie in and is limited to as being used to realize preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacturing approach thereof will comprise all embodiment that fall in the scope of the invention.
Claims (10)
1. the method for MOS element layout mass design comprises:
Confirm the shape and size of grid layer;
With the grid layer is independent variable, defines the shape and size of source region layer;
With the active region layer is independent variable, confirms the shape and size of input horizon, trap layer;
With grid layer and active region layer is independent variable, confirms the shape and size of through hole; And
With the through hole is independent variable, confirms the shape and size of metal level.
2. method as claimed in claim 1, wherein, the length of through hole and width are all less than the length and the width of grid layer and/or active region layer.
3. method as claimed in claim 1, wherein, the length of metal level and width be greater than the length and the width of through hole, and the length of metal level and width are less than the length and the width of grid layer and/or active region layer.
4. method as claimed in claim 1, wherein, active region layer is symmetrically distributed in the both sides of grid layer, and the width of active region layer is greater than the width of grid layer, and the length of active region layer is less than the length of grid layer.
5. method as claimed in claim 4, wherein, the width of input horizon and length is all greater than the width and the length of active region layer, and the width of trap layer and length are all greater than the width and the length of input horizon.
6. method as claimed in claim 1; Wherein, The active region layer asymmetric distribution is in the both sides of grid layer, and the width of active region layer is greater than the width of grid layer, and the length of active region layer is less than the length of grid layer; Active region layer comprises source electrode active region layer and the body utmost point active region layer that is positioned at grid layer one side, and the drain electrode active region layer that is positioned at the grid layer opposite side.
7. method as claimed in claim 6; Wherein, Drain electrode active region layer, source electrode active region layer and body utmost point active region layer equal in length, the width of source electrode active region layer equal the to drain width of active region layer, the width of body utmost point active region layer is less than source electrode active region layer and/or drain electrode active region layer.
8. method as claimed in claim 6; Wherein, Input horizon comprises the first kind input horizon and the second type input horizon, and all greater than the length of active region layer, the first kind input horizon and the second type input horizon width sum are greater than the width of active region layer for the length of first kind input horizon, the second type input horizon; Body utmost point active region layer is positioned at the second type input horizon; The source electrode active region layer is positioned at first kind input horizon with the drain electrode active region layer, and the width of trap layer is greater than the width sum of the first kind input horizon and the second type input horizon, and the length of trap layer is greater than the length of the first kind input horizon or the second type input horizon.
9. method as claimed in claim 6, wherein, drain electrode active region layer, source electrode active region layer and body utmost point active region layer width equate that the length of drain electrode active region layer equals source electrode active area length and body utmost point active region layer length sum.
10. method as claimed in claim 9; Wherein, Input horizon comprises source electrode first kind input horizon, drain electrode first kind input horizon and the second type input horizon; Drain electrode first kind input horizon width, source electrode first kind input horizon equates with the second type input horizon width and all greater than draining or source electrode active region layer width; Drain electrode first kind input horizon length equals the source electrode first kind input horizon length and the second type input horizon length sum, and the length of trap layer is greater than drain electrode first kind input horizon length, and the width of trap layer is greater than drain electrode first kind input horizon width and source electrode first kind input horizon width sum.
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