CN101752417A

CN101752417A - Method of layout design of laterally diffused MOS transistor

Info

Publication number: CN101752417A
Application number: CN200810044076A
Authority: CN
Inventors: 过乾; 朱丽霞
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2008-12-09
Filing date: 2008-12-09
Publication date: 2010-06-23

Abstract

The invention discloses a method of a layout design of a laterally diffused MOS transistor, which adopts the grid-shaped layout design and designs wells of a source region and a drain region of the laterally diffused MOS transistor in square shape, each well as the source region is surrounded by the well as the drain region, and each well as the drain region is surrounded by the well as the source region at the same time, then a square region with a smaller side length is defined as an active region of the drain region in the square of the well as the drain region, the well as the source region and a thin oxide layer defining region of the drain region are acted as an active region, and the rest annular part of the well as the drain region is acted as a field oxide region, polycrystalline silicon is arranged at the connecting part of the square of the source region and the square of the drain region and covers whole channel region and partial field oxide region, and a buried layer ion implantation region is added below a silicon epitaxial layer of the whole region. The method of the layout design can realize the optimization of the array area.

Description

The method of the layout design of laterally diffused MOS transistor

Technical field

The present invention relates to the method for the transistorized layout design of a kind of horizontal proliferation.

Background technology

The layout design of semiconductor device is a chip preparation necessary operation before, is used for a plurality of identical transistorized various pieces reasonably are distributed in silicon substrate according to designed circuit.In layout design, the ultimate aim that is minimised as the designer of chip device area.Laterally diffused MOS transistor (LDMOS) is a kind of in the MOS transistor, Fig. 1 is a sectional view of going up the laterally diffused MOS transistor that forms the N type at N type epitaxial loayer (NEPI), the channel region of this device and source region are in low pressure P well region (LVPW), and drain region (Drain) is high pressure N trap (HVNW).Between the field oxide (Field) active area (Active), be divided into N type district (N+) and p type island region (P+), be that the N+ district is source region (Source) in low pressure P trap wherein, P+ district in low pressure P trap and the N+ district in high pressure N trap all are the draw-out areas (Pick up) of trap potential.Polysilicon (Poly) grid is positioned at the intersection of low pressure P trap and high pressure N trap, and a part is on low pressure P trap, and a part is on field oxide.The bottom of device is n type buried layer (NBL), is used to reduce resistance substrate.The domain of above-mentioned LDMOS structure (layout) structure as shown in Figures 2 and 3, this structure can form array according to the repeated arrangement of cross-wise direction, i.e. general interdigital (finger) array of structures now.

Because its polysilicon broad has field oxide simultaneously, be difficult to realize the array of fenestral fabric in the ldmos transistor.Existing technology is all used interdigital structure when realizing the LDMOS array.The transistor array sense of current with this structure Design is fixed, and generally has only the electric current along cross-wise direction, can not realize the optimization of array area.Because the drain terminal area of conventional LDMOS is big, junction depth comprises the drift region simultaneously, so drain terminal resistance is big, is difficult to improve its resistance by process means.The ldmos transistor of interdigital structure is arranged and can't be realized even wiring simultaneously,

Summary of the invention

The technical problem to be solved in the present invention provides a kind of layout design method of laterally diffused MOS transistor, and it can be designed to ldmos transistor network-like arrangement, improves the density of ldmos transistor in the unit are.

For solving the problems of the technologies described above, the layout design method of laterally diffused MOS transistor of the present invention, it is characterized in that: will be designed to square respectively as the source region of laterally diffused MOS transistor and the trap in drain region, there is trap to center on around each trap as the drain region as the source region, simultaneously have the trap as the source region to center on around each trap as the drain region, back less square area of definition one length of side in the square of described trap as the drain region is the active area in drain region; Described as the trap in source region on and definition thin oxide layer district on the active area in described drain region, residue is a field oxide region as the annulus of the trap in drain region; Polysilicon is positioned at source region square and square joint, drain region, and covers whole channel region and part field oxide region; Under the silicon substrate in whole zone, increase the buried regions ion; Design the draw-out area and the contact hole in source region and drain region at last in the thin oxide layer district.

The layout design method of ldmos transistor of the present invention, owing to adopted the network of square layout, so can evenly connect up.Add buried regions at the Drain end simultaneously, reduce its dead resistance, optimize array.Utilize latticed layout design method, make the area of LDMOS array dwindle 20%, increased the uniformity of electric current, make the performance of chip and area more competitive than interdigitated configuration.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the cross section structure schematic diagram of ldmos transistor;

Fig. 2 is the domain of existing ldmos transistor;

Fig. 3 is the domain that increases the polysilicon position on domain shown in Figure 2;

Fig. 4 is for adopting the quadrate array cell schematics of layout design method of the present invention;

Fig. 5 for the splicing a plurality of as shown in Figure 4 the square array column unit and structural representation;

Fig. 6 is the position view of thin oxide layer and field oxide in the layout design of the present invention;

Fig. 7 is the position view of polysilicon in the layout design of the present invention;

Fig. 8 is the buried regions schematic diagram in the layout design of the present invention.

Embodiment

In the layout design method of laterally diffused MOS transistor of the present invention, mainly contain following several region design:

1, the method for designing of trap is: the trap of ldmos transistor employing low pressure or high pressure is as source region and drain region, to improve puncture voltage usually.In method for designing of the present invention, latticed layout is adopted in the design of trap, guaranteeing all has the drain region to center on around each source region, also active centering on around each drain region, Fig. 3 is spliced by two ldmos transistors for the method for designing of the individual unit in source region and drain region in the employing method of the present invention, high pressure N well region is the drain region, the P well region is the source region, and source region and drain region are adjacent square, forms 3 * 3 square array column unit (see figure 4).Arrange by a plurality of square array column units being adopted the nested mode splicing, as with square array column unit as described in a plurality of by as described in four jiaos of the square array column units any as the square of the trap in source region and one jiao of square overlapping splicing in another square array column unit as the trap in source region, then form as shown in Figure 5 arrangement architecture through spliced pattern arrangement with two, guaranteeing all has the drain region to center on around each source region, also active centering on around each drain region reaches the effect that high density is arranged simultaneously.Above-mentioned square array column unit also can adopt other arrangement mode to form the effect that high density is arranged.

2, the method for designing of active area: LDMOS uses field oxide region to form the drift region usually, reduce pressure drop, so thin oxide layer is being designed to the latticed while, also to reserve the zone of growth field oxide, in as the square of the trap in drain region definition one length of side less than the square array column unit in the single foursquare square area active area that is the drain region, on as the trap in source region and on the active area in drain region, be defined as the thin oxide layer district, annulus in the overseas high pressure N trap of the remaining drain region little square region of active area is the field oxide region (see figure 6), and the zone of the thin oxide layer of wherein growing is the active area of device.

3, the method for designing of polysilicon: polysilicon also is designed to latticed, cover the junction of foursquare high pressure N well region and foursquare P well region, while cover part field oxide and channel region, it is exactly the channel region (see figure 7) that the thin oxide layer zone in the source region of polysilicon covering is wherein arranged.

4, in whole zone, add buried regions, to reduce drain terminal resistance (see figure 8).

5, on the thin oxide layer zone, define N+ district and P+ district at last, layout design structure of the present invention does not have the field oxide region that is positioned at low pressure P trap shown in 1 among the figure, so on low pressure P trap when design N+ district and P+ district, be the N+ district with most of zone design of active area, as the source electrode of device, the remaining P+ district that is designed to, as the tagma, draw the current potential in tagma, source region respectively, and on the active area of high pressure N trap, define the N+ district, as drain electrode, draw the current potential in drain region.

The arrangement of the designed ldmos transistor that goes out of the layout design method of ldmos transistor of the present invention has following characteristics:

A. each drain region all active area center on, simultaneously each source region all has the drain region to center on;

B. source region and channel region all are coated with active area, and the active area in drain region is for to isolate by field oxide region with source region and channel region active area;

C. polysilicon is designed to latticedly, covers whole raceway grooves and part field oxide region.The oxide in field that polysilicon is covered with is the transistorized drift region of horizontal proliferation.

Claims

1. the layout design method of a laterally diffused MOS transistor, it is characterized in that: will be designed to square respectively as the source region of laterally diffused MOS transistor and the trap in drain region, there is trap to center on around each trap, has trap to center on around each trap simultaneously as the source region as the drain region as the drain region as the source region; Back less square area of definition one length of side in the square of described trap as the drain region is the active area in drain region, described as the trap in source region on and definition thin oxide layer district, described drain region as active area, residue is a field oxide region as the annulus of the trap in drain region; Polysilicon is positioned at source region square and square joint, drain region, and covers whole channel region and part field oxide region; Under the silicon epitaxy layer in whole zone, increase the buried regions ion implanted region; At last at design current potential draw-out area, thin oxide layer district and contact hole.

2. according to the described layout design method of claim 1, it is characterized in that: define one 3 * 3 square array column unit earlier, the square as the trap in the source region of laterally diffused MOS transistor and drain region in the described quadrate array is alternately arranged; With a plurality of described square array column units by in four jiaos of the described square array column units any as the square of the trap in source region and one jiao of square overlapping splicing in another square array column unit as the trap in source region, form the network-like arrangement of a plurality of laterally diffused MOS transistors.

3. according to the described layout design method of claim 2, it is characterized in that: in described 3 * 3 square array column unit, the square of described trap as the source region is designed to be positioned in the single square of described 3 * 3 square array column unit, but its length of side is less than single foursquare square in described 3 * 3 the square array column unit, and the remainder in this single square is designed to the injection zone of described trap as the drain region.