CN106876385B - The method for extracting storage unit domain - Google Patents
The method for extracting storage unit domain Download PDFInfo
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- CN106876385B CN106876385B CN201710080030.1A CN201710080030A CN106876385B CN 106876385 B CN106876385 B CN 106876385B CN 201710080030 A CN201710080030 A CN 201710080030A CN 106876385 B CN106876385 B CN 106876385B
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 110
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 109
- 238000000605 extraction Methods 0.000 claims abstract description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 10
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The method and device of a kind of extraction storage unit domain of the invention, comprising: obtain the domain of storage unit, the domain includes active area, the first polysilicon intersected with the active area and the second polysilicon on first polysilicon of part；Two sides in the active area close to first polysilicon are defined as body area；Two sides in first polysilicon close to the active area are defined as floating gate, the second polysilicon definition in the floating gate is control grid；It is selection gate by part first polysilicon definition between the body area；The active area between the body area and the selection gate is defined as to the source/drain regions of selection gate transistor；The active area of first polysilicon two sides is defined as to the source/drain regions of control gate transistor.Source electrode, drain electrode, the grid of different crystal pipe are told in the present invention, directly convenient for the design of device architecture.
Description
Technical field
The present invention relates to memory cell technologies field more particularly to a kind of methods for extracting storage unit domain.
Background technique
Memory unit is provided in computer or other electronic devices usually as internal element, semiconductor integrated circuit
In.Storage unit is divided into many different types, such as Random Access Storage Unit (RAM), read-only memory unit (ROM), dynamic
State Random Access Storage Unit (DRAM), synchronous dynamic random-access storage unit (SDRAM) and non-volatile flash storage are single
Member.Flash memory cell device has evolved into the common source of the non-volatile memory cells for various electronic applications.Fastly
Flash memory cell device is single usually using allowing the single-transistor of high density of memory cells, high reliability and low power consumption to store
First unit.The common use of flash memory cell includes personal computer, personal digital assistant (PDA), digital camera and honeycomb
Formula phone.Multiple storage units are generally included in memory, still, are difficult to deposit in directly differentiation in memory in the prior art
The structures such as source electrode, grid, drain electrode in storage unit.
Summary of the invention
The object of the present invention is to provide a kind of method and devices for extracting storage unit domain, solve in the prior art
The structures such as source electrode, drain electrode, the drain electrode of storage unit be difficult to the technical issues of differentiating.
In order to solve the above technical problems, the present invention provides a kind of method for extracting storage unit domain, comprising:
Obtain storage unit domain, the domain include active area, the first polysilicon intersected with the active area and
The second polysilicon on first polysilicon of part；
Two sides in the active area close to first polysilicon are defined as body area；
Two sides in first polysilicon close to the active area are defined as floating gate, second in the floating gate
Polysilicon definition is control grid；
It is selection gate by part first polysilicon definition between the body area；
The active area between the body area and the selection gate is defined as to source region/leakage of selection gate transistor
Area；
The active area of first polysilicon two sides is defined as to the source/drain regions of control gate transistor.
Optionally, active area described in the first polysilicon covering part, and extend to the two sides away from the active area.
Optionally, second polysilicon covers the opposite two sides of the first polysilicon, and active area described in covering part.
Optionally, the domain of the storage unit further include: be located at the active area two sides, and be connected with the active area
Two bit lines.
Optionally, one of described two bit lines are connected with the source region of the control gate transistor, in two bit lines
Another bit line is connected with the drain region of the control gate transistor.
Optionally, the domain of the storage unit further include: the first plug on second polysilicon, described
One plug is located on the control grid.
Optionally, the domain of the storage unit further include: be used to pick out in the body area on the active area
The second plug.
Optionally, the domain of the storage unit further include: electric for connecting wordline on first polysilicon
The third plug of pressure.
Optionally, the floating gate also extends to the two sides of first polysilicon.
Correspondingly, the present invention also provides a kind of devices for extracting storage unit domain, comprising:
Domain acquiring unit, for obtaining the domain of the storage unit, the domain include active area, with it is described active
The first polysilicon and the second polysilicon on first polysilicon of part of area's intersection；
Parameter extraction unit, the parameter extraction unit include that active area parameter extraction unit, the first polysilicon parameter mention
Take unit and the second polysilicon parameter extraction unit；
Wherein, the active area parameter extraction unit will define in the active area close to the two sides of first polysilicon
For body area；Two sides in first polysilicon close to the active area are defined as by the first polysilicon parameter extraction unit
Floating gate, the second polysilicon definition in floating gate described in the second polysilicon parameter extraction unit is control grid；It is described
Part first polysilicon definition between the body area is selection gate by the first polysilicon parameter extraction unit；It is described to have
The active area between the body area and the selection gate is defined as selection gate transistor by source region parameter extraction unit
Source/drain regions；The active area of first polysilicon two sides is defined as control gate by the active area parameter extraction unit
The source/drain regions of transistor.
Compared with prior art, the method for extraction storage unit domain of the invention includes: the domain for obtaining storage unit,
The domain include active area, the first polysilicon intersected with the active area and on first polysilicon of part
Two polysilicons；Two sides in the active area close to first polysilicon are defined as body area；It will be in first polysilicon
Two sides close to the active area are defined as floating gate, and the second polysilicon definition in the floating gate is control grid；By institute
Part first polysilicon definition between the area Shu Ti is selection gate；By the institute between the body area and the selection gate
State the source/drain regions that active area is defined as selection gate transistor；The active area of first polysilicon two sides is defined as
Control the source/drain regions of gate transistor.Source electrode, drain electrode, the grid of different crystal pipe are directly told in the present invention, are convenient for device
The design of structure.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of storage unit extraction element in one embodiment of the invention；
Fig. 2 is the method flow diagram of the extraction storage unit domain in one embodiment of the invention；
Fig. 3 is the domain of the storage unit in one embodiment of the invention；
Fig. 4 is the structural schematic diagram that body area is extracted in one embodiment of the invention；
Fig. 5 is the structural schematic diagram that floating gate is extracted in one embodiment of the invention；
Fig. 6 is the structural schematic diagram that selection gate is extracted in one embodiment of the invention；
Fig. 7 is the structural schematic diagram that selection grid transistor source/drain regions are extracted in one embodiment of the invention；
Fig. 8 is the structural schematic diagram that control gate transistor source/drain regions are extracted in one embodiment of the invention；
Fig. 9 is the equivalent circuit diagram of storage unit in one embodiment of the invention.
Specific embodiment
It is retouched in more detail below in conjunction with method and device of the schematic diagram to extraction storage unit domain of the invention
It states, which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify described herein hair
It is bright, and still realize advantageous effects of the invention.Therefore, following description should be understood as the wide of those skilled in the art
It is general to know, and it is not intended as limitation of the present invention.
Core of the invention thought is that the method for the extraction storage unit domain provided includes: to obtain storage unit
Domain, the domain include active area, the first polysilicon intersected with the active area and be located at part first polysilicon
On the second polysilicon；Two sides in the active area close to first polysilicon are defined as body area；More than described first
Two sides in crystal silicon close to the active area are defined as floating gate, and the second polysilicon definition in the floating gate is control gate
Pole；It is selection gate by part first polysilicon definition between the body area；By the body area and the selection gate
Between the active area be defined as selection gate transistor source/drain regions；By the described active of first polysilicon two sides
Area definition is the source/drain regions for controlling gate transistor.Source electrode, drain electrode, the grid of different crystal pipe are directly told in the present invention,
Convenient for the design of device architecture.
It is specifically described below in conjunction with method and device of the attached drawing to extraction storage unit domain of the invention.
With reference to shown in Fig. 1, it is provided by the invention it is a kind of extract storage unit domain device include: domain acquiring unit
1, the domain acquiring unit is used to obtain the domain of the storage unit, and the domain includes active area and the active area
The first polysilicon and the second polysilicon on first polysilicon of part of intersection；Parameter extraction unit 2, the parameter
Extraction unit includes active area parameter extraction unit 21, the first polysilicon parameter extraction unit 22 and the second polysilicon parameter extraction
Unit 23, active area parameter extraction unit, the first polysilicon parameter extraction unit and the second polysilicon parameter extraction unit difference
The parameter of active area, the first polysilicon and the second polysilicon is extracted.
Specifically, extracting using above-mentioned apparatus to storage unit domain with reference to shown in Fig. 2, storage unit is extracted
The method of domain includes the following steps:
Step S1 is executed, refering to what is shown in Fig. 3, domain acquiring unit obtains the domain of storage unit, the domain packet first
It includes the active area 110 being located in semiconductor substrate 100, the first polysilicon 120 intersected with the active area 110 and is located at part
The second polysilicon 130 on first polysilicon 120,.Wherein, active area described in 120 covering part of the first polysilicon
110, and extend to the two sides away from the active area 110.It is opposite that second polysilicon 130 covers the first polysilicon 120
Two sides, and active area 110 described in covering part.
Execute step S2, refering to what is shown in Fig. 4, active area parameter extraction unit by the active area 110 close to described the
The two sides of one polysilicon 120 are defined as body area 150；
Step S3 is executed, refering to what is shown in Fig. 5, the first polysilicon parameter extraction unit will be leaned in first polysilicon 120
The two sides of the nearly active area 110 are defined as floating gate (FG) 160, and the floating gate 150 also extends to first polysilicon
120 two sides, so that the floating gate with a line is connected.Also, in floating gate 160 described in the second polysilicon parameter extraction unit
Second polysilicon 130 is defined as control grid (CG).
Step S4 is executed, refering to what is shown in Fig. 6, the first polysilicon parameter extraction unit is by the part between the body area 150
First polysilicon 120 is defined as selection gate (SG) 170.
Step S5 is executed, refering to what is shown in Fig. 7, active area parameter extraction unit is by the body area 150 and the selection gate
The active area 110 between 170 is defined as the source/drain regions 180 of selection gate transistor.
Step S6 is executed, refering to what is shown in Fig. 8, active area parameter extraction unit is by the institute of 120 two sides of the first polysilicon
State the source/drain regions 190 that active area 110 is defined as control gate transistor.In addition, the domain of the storage unit further include: position
In the active area two sides, and two bit lines BL1, BL2 being connected with the active area.Two bit lines BL1, BL2 difference
It is connected with the source/drain regions 190 of the control gate transistor.
Further, the domain of the storage unit further include: the first plug on second polysilicon 120
141, first plug 141 is located on the control grid.The domain of the storage unit further include: be located at the active area
The second plug (not shown) for picking out the body area 150 on 110: and it is located at first polysilicon 120
On for connecting the third plug (not shown) of wordline WL voltage.
The equivalent circuit diagram of storage unit of the invention is refering to what is shown in Fig. 9, selection gate transistor and control gate transistors
The area Guan Ti is connected, and selection gate connects wordline, and the source/drain regions of two control gridistors are separately connected two bit lines.
In conclusion the method provided by the invention for extracting storage unit domain includes: the domain for obtaining storage unit, institute
State domain include active area, the first polysilicon intersected with the active area and on first polysilicon of part second
Polysilicon；Two sides in the active area close to first polysilicon are defined as body area；It will be leaned in first polysilicon
The two sides of the nearly active area are defined as floating gate, and the second polysilicon definition in the floating gate is control grid；It will be described
Part first polysilicon definition between body area is selection gate；Described between the body area and the selection gate
Active area is defined as the source/drain regions of selection gate transistor；The active area of first polysilicon two sides is defined as controlling
The source/drain regions of gate transistor processed.Source electrode, drain electrode, the grid of different crystal pipe are directly told in the present invention, are convenient for device junction
The design of structure.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of method for extracting storage unit domain characterized by comprising
The domain of storage unit is obtained, the domain includes active area, the first polysilicon intersected with the active area and is located at
The second polysilicon on first polysilicon of part；
Two sides in the active area close to first polysilicon are defined as body area；
Two sides in first polysilicon close to the active area are defined as floating gate, the second polycrystalline in the floating gate
Silicon is defined as control grid；
It is selection gate by part first polysilicon definition between the body area；
The active area between the body area and the selection gate is defined as to the source/drain regions of selection gate transistor；
The active area of first polysilicon two sides is defined as to the source/drain regions of control gate transistor.
2. extracting the method for storage unit domain as described in claim 1, which is characterized in that the first polysilicon covering part
Divide the active area, and extends to the two sides away from the active area.
3. extracting the method for storage unit domain as described in claim 1, which is characterized in that second polysilicon covering the
The opposite two sides of one polysilicon, and active area described in covering part.
4. extracting the method for storage unit domain as described in claim 1, which is characterized in that the domain of the storage unit is also
It include: positioned at the active area two sides, and two bit lines being connected with the active area.
5. extracting the method for storage unit domain as claimed in claim 4, which is characterized in that one of described two bit lines and institute
The source region for stating control gate transistor is connected, the drain region phase of another bit line in two bit lines and the control gate transistor
Even.
6. extracting the method for storage unit domain as described in claim 1, which is characterized in that the domain of the storage unit is also
It include: the first plug on second polysilicon, first plug is located on the control grid.
7. extracting the method for storage unit domain as described in claim 1, which is characterized in that the domain of the storage unit is also
It include: the second plug for picking out the body area on the active area.
8. extracting the method for storage unit domain as described in claim 1, which is characterized in that the domain of the storage unit is also
It include: on first polysilicon for connecting the third plug of word line voltage.
9. extracting the method for storage unit domain as described in claim 1, which is characterized in that the floating gate also extends to institute
State the two sides of the first polysilicon.
10. a kind of device for extracting storage unit domain characterized by comprising
Domain acquiring unit, for obtaining the domain of the storage unit, the domain include active area, with the active area phase
The first polysilicon and the second polysilicon on first polysilicon of part handed over；
Parameter extraction unit, the parameter extraction unit include active area parameter extraction unit, the first polysilicon parameter extraction list
Member and the second polysilicon parameter extraction unit；
Wherein, the two sides in the active area close to first polysilicon are defined as body by the active area parameter extraction unit
Area；Two sides in first polysilicon close to the active area are defined as floating gate by the first polysilicon parameter extraction unit
Pole, the second polysilicon definition in floating gate described in the second polysilicon parameter extraction unit is control grid；Described first
Part first polysilicon definition between the body area is selection gate by polysilicon parameter extraction unit；The active area
Parameter extraction unit by the active area between the body area and the selection gate be defined as selection gate transistor source region/
Drain region；The active area of first polysilicon two sides is defined as control gate transistor by the active area parameter extraction unit
Source/drain regions.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752417A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹Nec电子有限公司 | Method of layout design of laterally diffused MOS transistor |
| CN103456359A (en) * | 2013-09-03 | 2013-12-18 | 苏州宽温电子科技有限公司 | Improved differential framework Nor flash storage unit based on serially-connected transistor type |
| CN103904082A (en) * | 2012-12-27 | 2014-07-02 | 力旺电子股份有限公司 | Nonvolatile memory structure and method for fabricating nonvolatile memory structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9406764B2 (en) * | 2013-06-27 | 2016-08-02 | Globalfoundries Singapore Pte. Ltd. | Simple and cost-free MTP structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752417A (en) * | 2008-12-09 | 2010-06-23 | 上海华虹Nec电子有限公司 | Method of layout design of laterally diffused MOS transistor |
| CN103904082A (en) * | 2012-12-27 | 2014-07-02 | 力旺电子股份有限公司 | Nonvolatile memory structure and method for fabricating nonvolatile memory structure |
| CN103456359A (en) * | 2013-09-03 | 2013-12-18 | 苏州宽温电子科技有限公司 | Improved differential framework Nor flash storage unit based on serially-connected transistor type |
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