CN106601728A - Three-dimensional laminated integrated device of three-dimensional laminated inductive element and wafer chip, and manufacturing method and application thereof - Google Patents
Three-dimensional laminated integrated device of three-dimensional laminated inductive element and wafer chip, and manufacturing method and application thereof Download PDFInfo
- Publication number
- CN106601728A CN106601728A CN201610960208.7A CN201610960208A CN106601728A CN 106601728 A CN106601728 A CN 106601728A CN 201610960208 A CN201610960208 A CN 201610960208A CN 106601728 A CN106601728 A CN 106601728A
- Authority
- CN
- China
- Prior art keywords
- layer
- inductive element
- integrated device
- copper material
- chip wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
The invention discloses a three-dimensional laminated integrated device of an inductive element and a wafer chip, and a manufacturing method and application of the three-dimensional laminated integrated device. The inductive element of the integrated device is formed by hot-pressing and laminating a magnetic sheet material layer, and a plurality of isolating layers and a plurality of copper material layers on two sides of a width direction of the magnetic sheet material layer. The wafer chip of the integrated device is bonded to an arbitrary side surface of the inductive element in a width direction, and is integrally packaged. Through providing the three-dimensional laminated integrated device, and the manufacturing method and the application technical schemes thereof, the space-occupying size and height of the integrated device are significantly reduced, the voltage ripple of the integrated device is improved, and the integrated device is endowed with a high-noise shielding immunity; and the integrated device can be widely applied to wearable equipment, smart phones, tablet computers, Ultrabooks, portable medical equipment and various industrial and living service equipment.
Description
Technical field
It is the present invention relates to a kind of semiconductor production device architecture and its production technology more particularly to a kind of space optimization, vertical
The new technology and its related device structures of the compound inductive element of body stacking and chip wafer.
Background technology
Magnetic or inductive component, such as inductor and transformer are generally used in semiconductor devices and electronic system.For example
Switching Power Supply, switching regulator, power supply changeover device, the power factor correcting converter of isolation, linear voltage regulator, simulation collection
Into circuit, radio frequency transmitter, MEMS etc..
Currently, inductance component is typically discrete component.In above-mentioned applied system design, they all have to pass through
Printed circuit board (PCB) is packaged in the modes such as the carrier of a device and is connected with semiconductor devices.Wherein the carrier of device can be
Circuit on the substrate of metal framework or isolated substrate.And the space occupied by those discrete components is adopted generally than larger.
Especially relatively project at projection breadth, thickness and the aspect of weight three.
The device that the group structure of above-mentioned discrete component is formed is of a relatively high, is not suitable for short and small frivolous application demand, for example
Wearable device, panel computer, smart mobile phone, Ultrabook, portable medical device etc..
In the integrated device that above-mentioned discrete component is constituted, wherein stray inductance can be in a wider frequency range
Hinder the frequency response of electronic system.Can be megahertz to the high-frequency range of Gigahertz.
For the inductance of winding type, when the frequency dynamic fluctuation range of its electric current is up to several hertz to 20 KHz,
The acoustic noise that it is generated by the mankind ear sensitivity perceive.
Discrete capacitor part is sometimes even exceeded hundreds of by the radio frequency for being mechanically connected or being introduced into stray inductance
Megahertz.So as to cause to reduce effective capacitance and the drawbacks of its impedance can be higher with frequency change.
As shown in figure 1, discrete inductance is welded on to be accessed on support plate or the printed circuit board (PCB) by circuit route partly leading
Body device.They form the integrated device of common packaging, can stay in open framework or use epoxy encapsulation.From above-mentioned
Analysis is visible, not only the integrated device space duty ratio shown in Fig. 1 is larger, and the noise in device, frequency response, effective capacitance etc.
It is unfavorable for commercial applications in aspect performance, perfect evolutionary approach need be proposed to the structure of the integrated device and technique, with
Meet configuration and the performance requirement of various commercial application.
The content of the invention
In view of above-mentioned the deficiencies in the prior art, the purpose of the present invention is directed to a kind of three-dimensional stacked inductive element and crystalline substance
The integrated device and its preparation method of round core piece and application, to solving the problems, such as that integrated device duty is big and performance advantage is poor.
The technical solution of above-mentioned solution first purpose of the present invention is：Three-dimensional stacked inductive element and chip wafer
Integrated device, it is characterised in that：If the inductive element of the integrated device is from magnetic sheet layer and its breadth to the dried layer of both sides
If separation layer, dried layer copper material layer hot pressing cladding are constituted, the chip wafer of the integrated device be bonded to inductive element breadth to
Arbitrary side surface, and overall package.
Further, the magnetic sheet layer of the inductive element is mixed uniformly magnetic and spacer medium by binding agent tree
The individual layer lamellar body of fat solidification, the magnetic only corresponds to a kind of electromagnetic frequency response characteristic.
Further, the magnetic sheet layer of the inductive element is mixed uniformly magnetic and spacer medium by binding agent tree
, with upper piece, the electromagnetic frequency response characteristic corresponding to each layer magnetic is different, and is provided between adjacent two layers for the two-layer of fat solidification
Separation layer.
Further, the magnetic sheet layer directly offer full thickness to two or more perforation, each perforation in note
Be provided with copper material, the copper material connect be provided between the copper material layer of magnetic sheet layer both side surface, and each perforation inwall and copper material every
Absciss layer.
Further, the magnetic sheet layer is set to bar-shaped lamellar body and is flush-mounted in separation layer pedestal to preset in the groove of shaping, institute
The thickness for stating magnetic sheet layer is identical with the depth of groove, the separation layer pedestal offer on the outside of magnetic sheet layer full thickness to
Two or more perforation, note is provided with copper material between each perforation, and the copper material connects the copper material layer of magnetic sheet layer both side surface.
Further, the copper material layer is the printed wiring pattern on magnetic sheet material layer surface separation layer, and copper
Material layer covers the copper material in all perforation of connection respective side.
Further, the magnetic sheet layer forms two or more and integrates perpendicular to breadth to being divided into more than two sections
Inductive element.
Further, the chip wafer is a chip with plural stitch, and each stitch bond is in inductive element
On the copper packing drawn outside top layer.
Further, the chip wafer is a chip without stitch, and the contact of chip is by lead connection perception
On the copper packing drawn outside element surface.
Further, the chip wafer is the chip with plural stitch and number of chips is two or more, two or more
Each stitch correspondence of chip wafer is bonded on the copper packing drawn outside inductive element top layer.
Further, the integrated device is provided with the compound cap of heat, the compound cap of heat be covered in the inductive element that completes to be bonded and
Chip wafer and packaging by hot pressing.
Further, the integrated device is filled with epoxy resin in the inductive element and chip wafer periphery for completing to be bonded
Encapsulation.
Further, the integrated device is provided with pin or sphere grid array, and draws at the correspondence perforation of self-induction element
Copper material layer
A kind of technical solution of above-mentioned solution second purpose of the present invention is：Three-dimensional stacked inductive element and chip wafer
Integrated device preparation method, it is characterised in that including step：
S1, magnetic sheet layer is made, from magnetic, magnetic sheet and spacer medium is uniformly blended into, using resin glue in prefabricated die cavity
Middle curing molding is individual layer or lamellar body more than two-layer；
S2, make inductive element, by top, the basal surface of the magnetic sheet layer obtained by step S1 uniformly be combined one layer of separation layer, and
Magnetic sheet material thickness degree to several perforation are drilled with, the then injection copper material in each perforation, and top, the separation layer of bottom side it is outer
Side surface electroplates copper material layer so that copper material layer is connected with the copper material in perforation, and then the outer surface in copper material layer is combined again one
Layer separation layer, and draw pin or sphere grid array from copper material layer；
S3, bonding chip wafer, if needing to be combined on the separation layer of bond wafer chip-side in the inductive element obtained by step S2
Dry discrete copper packing, the stitch of the chip wafer or contact packet and copper packing phase key and, and part stitch or contact pass through to wear
Copper material in hole accesses pin or sphere grid array；
S4, packaging, are packaged to the inductive element obtained by step S3 with the key and body of chip wafer.
Further, the method punched described in above-mentioned steps S2 is diplopore drilling process, from the point of view of any one is bored a hole,
First in magnetic sheet material thickness degree to the hole of drilling first, then fill up spacer medium in first hole and solidify, then this first
The second relatively small hole of coaxial drill diameter in hole so that form separation layer between injection copper material therein and magnetic sheet layer.
Further, in above-mentioned steps S2 inject copper material method be included in perforation in inject copper starch and solidify and perforation
Inwall electroplates copper material.
Further, when the copper material surface for completing to inject does not meet connection copper material layer, pass through on the copper material surface
Plating photoetching process mends copper to required level height.
Further, make described in step S1 in the raw material of magnetic sheet layer, magnetic is optional including iron nickel-molybdenum alloy
Magnetic, sendust magnetic, ferrum-silicon alloy magnetic powder, iron silicochromium magnetic, iron-nickel alloy magnetic, MnZn alloy magnetic powder, cobalt
The mixed ferromagnetic oxide powder of one of niobium kirsite magnetic or two or more magnetics；Magnetic sheet is optional including manganese-zinc ferrite, nickel zinc
Ferritic ferrite magnetic sheet.
Further, the material of the separation layer is optional including epoxy resin, fire-retardant prepreg, BMI three
One kind during piperazine blending resin and polyimides are vertical.
Further, a kind of method for packing of step S4 is directly to be combined cap using the heat of corresponding specification, and heat is combined
Cap aligns and the key and body of inductive element and chip wafer is completely covered, and then hot pressing completes encapsulation.
Further, a kind of method for packing of step S4 is that the key and body of inductive element and chip wafer are exposed to into air
In, and the outside filling epoxy resin in bonding body coats completely inductive element and chip wafer, cooling completes encapsulation.
Another kind of technical solution of above-mentioned solution second purpose of the present invention is：Three-dimensional stacked inductive element and crystalline substance
The preparation method of the integrated device of round core piece, it is characterised in that including step：
S5, magnetic sheet layer is made, from magnetic, magnetic sheet and spacer medium is uniformly blended into, using resin glue in prefabricated die cavity
Middle curing molding is individual layer or bar-shaped lamellar body more than two-layer；
S6, separation layer pedestal is made, make breadth, thickness from spacer medium and hybrid adhesive resin solidification and be all higher than magnetic sheet
The matrix of material layer, and by photoetching or etch process matrix breadth to one or both sides surface forming groove, the depth of the groove
Degree is identical with the thickness of the magnetic sheet layer obtained by S5,
S7, making inductive element, in the groove of the matrix that the magnetic sheet layer obtained by step S5 is embedded in obtained by step S6, in magnetic sheet
Top, the basal surface of material layer is uniformly combined one layer of separation layer, and is drilled with several on the outside of the relative magnetic sheet layer of separation layer pedestal
Full thickness to perforation, then each perforation in injection copper material, and top, the separation layer of bottom side outer surface electro-coppering
Material layer so that copper material layer with perforation in copper material connect, then copper material layer outer surface again be combined one layer of separation layer, and oneself
Copper material layer draws pin or sphere grid array；
S8, bonding chip wafer, if needing to be combined on the separation layer of bond wafer chip-side in the inductive element obtained by step S2
Dry discrete copper packing, the stitch of the chip wafer or contact packet and copper packing phase key and, and part stitch or contact pass through to wear
Copper material in hole accesses pin or sphere grid array；
S9, packaging, are packaged to the inductive element obtained by step S3 with the key and body of chip wafer.
Further, when making separation layer pedestal in step S6, the breadth correspondence 2 of the matrixnIndividual integrated device is implemented
Prepare with scale, synchronous forming groove, implementation steps S7, step S8 and step S9 on the matrix, and hold after packaging is accomplished
Row step S10, according to the specification of integrated device monomer is cut into, wherein the n is positive integer.
The technical solution of above-mentioned solution the 3rd purpose of the present invention is：. three-dimensional stacked inductive element and wafer core
The application of the integrated device of piece, it is characterised in that：The integrated device is at least applied to step down voltage redulator, linear voltage regulator, drop
Pressure PWM switching power supplies, integrated control chip, flash MOSFET chips, the voltage-regulation converter of low side MOSFET chips,
The step-down controller of integrated control chip and flash MOSFET chips, the boost converter of the direct-connected input voltage of inductance is integrated
The boost converter of MOSFET and diode, the boost converter of integrated two power transistors, inductor and power switch control
The type of voltage step-up/down converter that circuit chip processed is joined directly together, the buck of integrated four power transistors, inductance and control chips turns
Parallel operation and noise reduction controller.
The proposition of the three-dimensional stacked integrated device of the present invention and its preparation method and application technology scheme, compared to traditional such device
Part has a significant technique effect, summarize speech including the duty volume and height for greatly reducing the integrated device, and improvement
The ripple voltage of integrated device simultaneously imparts the shielding immunocompetence of strong noise；The integrated device can be widely used in wearable
Among all types of industries such as equipment, smart mobile phone, panel computer, ultrabook, portable medical device and lifestyle device.
Description of the drawings
Fig. 1 is the discrete cross-sectional view for connecting of current inductive element and chip wafer.
Fig. 2 is the cross-sectional view of inductive element of the present invention and the stacked connection of chip wafer.
Fig. 3 to Fig. 5 is a kind of process schematic of preparation method of the three-dimensional stacked integrated device of the present invention.
Fig. 6 to Fig. 8 is the process schematic of the three-dimensional stacked integrated device another kind preparation method of the present invention.
Fig. 9 to Figure 11 is the process schematic of three-dimensional stacked another preparation method of integrated device of the present invention.
Figure 12 is a kind of cross-sectional view for implementing framework of the three-dimensional stacked integrated device of the present invention.
Figure 13 is another kind of cross-sectional view for implementing framework of the three-dimensional stacked integrated device of the present invention.
Figure 14 is the cross-sectional view of another enforcement framework of the three-dimensional stacked integrated device of the present invention.
Figure 15 is the cross-sectional view of another enforcement framework of the three-dimensional stacked integrated device of the present invention.
Figure 16 is a kind of applicable circuit diagram of the three-dimensional stacked integrated device of the present invention.
Figure 17 is the applicable another kind of circuit diagram of the three-dimensional stacked integrated device of the present invention.
Figure 18 is applicable another circuit diagram of the three-dimensional stacked integrated device of the present invention.
Figure 19 is applicable another circuit diagram of the three-dimensional stacked integrated device of the present invention.
Figure 20 is the applicable not a kind of circuit diagram of the three-dimensional stacked integrated device of the present invention.
Figure 21 is a kind of applicable other circuit diagrams of the three-dimensional stacked integrated device of the present invention.
Specific embodiment
Technical solution of the present invention is described further below in conjunction with the accompanying drawings：So that the technology design of subject application is able to entirely
Face shows and should be readily appreciated that by those skilled in the art.
First, from the architectural feature of the three-dimensional stacked inductive element and the integrated device of chip wafer carry out by summarize to
Deep description：If as shown in Fig. 2 the inductive element of the integrated device is isolated from magnetic sheet layer and its breadth to the dried layer of both sides
If layer, dried layer copper material layer hot pressing cladding are constituted, the chip wafer of the integrated device be bonded to inductive element breadth to it is arbitrary
Side surface, and overall package forms.
Specifically, the magnetic sheet layer of above-mentioned inductive element is mixed uniformly magnetic, magnetic sheet and spacer medium by bonding
The individual layer lamellar body of agent resin solidification, magnetic only corresponds to a kind of electromagnetic frequency response characteristic.Or inductive element as shown in figure 13
The two-layer that magnetic sheet layer is mixed uniformly magnetic, magnetic sheet and spacer medium to be solidified by resin glue with upper piece, each layer
Electromagnetic frequency response characteristic corresponding to magnetic is different, and separation layer is provided between adjacent two layers.Here soft magnetic powder can be with
Selection includes iron nickel-molybdenum alloy magnetic, sendust magnetic, ferrum-silicon alloy magnetic powder, iron silicochromium magnetic, iron-nickel alloy magnetic
The mixed ferromagnetic oxide powder of one of powder, MnZn alloy magnetic powder, cobalt niobium kirsite magnetic or two or more magnetics.And magnetic sheet is optional
Including manganese-zinc ferrite, the ferrite magnetic sheet of nickel-zinc ferrite.The magnetic sheet layer for being formed need with sufficient tensile strength,
Bending strength, and possess the thermal coefficient of expansion of certain upper limit.The surface of the magnetic sheet layer is typically dielectric, but actual work
Reliable and stable insulation is difficult to realize in skill, it is therefore desirable to which magnetic sheet material layer surface after shaping does insulation processing.
In embodiment as shown in Figures 3 to 5, the magnetic sheet layer directly offer full thickness to two or more wear
Hole, note is provided with copper material in each perforation, and the copper material connects the copper material layer of magnetic sheet layer both side surface, and each perforation inwall with
Separation layer is provided between copper material.
Again in embodiment please as shown in Figure 6 to 8, the magnetic sheet layer is set to bar-shaped lamellar body and is flush-mounted in separation layer pedestal
In the groove of default shaping, the thickness of magnetic sheet layer is identical with the depth of groove, and the separation layer pedestal is opened on the outside of magnetic sheet layer
Be provided with full thickness to two or more perforation, note is provided with copper material between each perforation, the copper material connection magnetic sheet layer both sides
The copper material layer on surface.
As shown in Figure 5 and Figure 8, above-mentioned copper material layer is the printed wiring pattern on magnetic sheet material layer surface separation layer,
And copper material layer covers the copper material in all perforation of connection respective side.
Embodiment as shown in figure 14, above-mentioned magnetic sheet layer is asked, to being divided into more than two sections, to form two perpendicular to breadth again
The inductive element integrated more than individual.The technique of the embodiment realizes that simply the circuit design needed for can coordinating is selected
Property is used.
As shown in Fig. 2 and Figure 12, the chip wafer in the embodiment is a chip with plural stitch, and each stitch
It is bonded on the copper packing drawn outside inductive element top layer, Fig. 2 show chip wafer positioned at inductive element upper surface, and Figure 12 institutes
Chip wafer is shown as positioned at inductive element lower surface, except that, the mode of the next integrated chip wafer shown in Figure 12 is needed
Want whole device that there is higher pin or sphere grid array, so that chip wafer is in hanging shape.Above-mentioned pin or sphere grid array draw
Come from the copper material layer at inductive element correspondence perforation.
Additionally, as shown in figure 13, for same inductive element can be while the integrated wafer core for being connected with more than two pieces
Piece, to reach default circuit requirement is met.
As shown in figure 15, the chip wafer in the embodiment is a chip without stitch, and the contact of chip is by drawing
On the copper packing drawn outside line connection inductive element surface.
Such devices need to tolerate the environmental factors such as certain high temperature, dust when specific equipment is applied in the later stage, because
This needs to carry out certain encapsulation, for this purpose, the integrated device is provided with the compound cap of heat, the compound cap of heat is covered in the perception for completing to be bonded
Element and chip wafer and packaging by hot pressing.Or, in the case where process conditions meet, by integrated device in the sense for completing to be bonded
Property element and chip wafer periphery be filled with epoxy encapsulation.
Then, by several slightly differentiated concrete technology descriptions, the preparation method of the integrated device is further understood.It is three-dimensional
The one preparation method of the integrated device of stacked inductive element and chip wafer, as in Figure 3-5, it is characterised in that including step：
S1, magnetic sheet layer is made, from magnetic, magnetic sheet and spacer medium is uniformly blended into, using resin glue in prefabricated die cavity
Middle curing molding is individual layer or lamellar body more than two-layer；
S2, make inductive element, by top, the basal surface of the magnetic sheet layer obtained by step S1 uniformly be combined one layer of separation layer, and
Magnetic sheet material thickness degree to several perforation are drilled with, the then injection copper material in each perforation, and top, the separation layer of bottom side it is outer
Side surface electroplates copper material layer so that copper material layer is connected with the copper material in perforation, and then the outer surface in copper material layer is combined again one
Layer separation layer, and draw pin or sphere grid array from copper material layer；
S3, bonding chip wafer, if needing to be combined on the separation layer of bond wafer chip-side in the inductive element obtained by step S2
Dry discrete copper packing, the stitch of the chip wafer or contact packet and copper packing phase key and, and part stitch or contact pass through to wear
Copper material in hole accesses pin or sphere grid array；
S4, packaging, are packaged to the inductive element obtained by step S3 with the key and body of chip wafer.
Further, the method punched described in above-mentioned steps S2 is diplopore drilling process, from the point of view of any one is bored a hole,
First in magnetic sheet material thickness degree to the hole of drilling first, then fill up spacer medium in first hole and solidify, then this first
The second relatively small hole of coaxial drill diameter in hole so that form separation layer between injection copper material therein and magnetic sheet layer.
Further, in above-mentioned steps S2 inject copper material method be included in perforation in inject copper starch and solidify and perforation
Inwall electroplates copper material.
Further, when the copper material surface for completing to inject does not meet connection copper material layer, pass through on the copper material surface
Plating photoetching process mends copper to required level height.
Further, make described in step S1 in the raw material of magnetic sheet layer, magnetic is optional including iron nickel-molybdenum alloy
Magnetic, sendust magnetic, ferrum-silicon alloy magnetic powder, iron silicochromium magnetic, iron-nickel alloy magnetic, MnZn alloy magnetic powder, cobalt
The mixed ferromagnetic oxide powder of one of niobium kirsite magnetic or two or more magnetics；Magnetic sheet is optional including manganese-zinc ferrite, nickel zinc
Ferritic ferrite magnetic sheet.
Further, the material of the separation layer is optional including epoxy resin, fire-retardant prepreg, BMI three
One kind during piperazine blending resin and polyimides are vertical.
Further, a kind of method for packing of step S4 is directly to be combined cap using the heat of corresponding specification, and heat is combined
Cap aligns and the key and body of inductive element and chip wafer is completely covered, and then hot pressing completes encapsulation.
Further, a kind of method for packing of step S4 is that the key and body of inductive element and chip wafer are exposed to into air
In, and the outside filling epoxy resin in bonding body coats completely inductive element and chip wafer, cooling completes encapsulation.
Its two preparation method of the integrated device of three-dimensional stacked inductive element and chip wafer, as shown in figs 6-8, its feature exists
In including step：
S5, magnetic sheet layer is made, from magnetic, magnetic sheet and spacer medium is uniformly blended into, using resin glue in prefabricated die cavity
Middle curing molding is individual layer or bar-shaped lamellar body more than two-layer；
S6, separation layer pedestal is made, make breadth, thickness from spacer medium and hybrid adhesive resin solidification and be all higher than magnetic sheet
The matrix of material layer, and by photoetching or etch process matrix breadth to one or both sides surface forming groove, the depth of the groove
Degree is identical with the thickness of the magnetic sheet layer obtained by S5,
S7, making inductive element, in the groove of the matrix that the magnetic sheet layer obtained by step S5 is embedded in obtained by step S6, in magnetic sheet
Top, the basal surface of material layer is uniformly combined one layer of separation layer, and is drilled with several on the outside of the relative magnetic sheet layer of separation layer pedestal
Full thickness to perforation, then each perforation in injection copper material, and top, the separation layer of bottom side outer surface electro-coppering
Material layer so that copper material layer with perforation in copper material connect, then copper material layer outer surface again be combined one layer of separation layer, and oneself
Copper material layer draws pin or sphere grid array；
S8, bonding chip wafer, if needing to be combined on the separation layer of bond wafer chip-side in the inductive element obtained by step S2
Dry discrete copper packing, the stitch of the chip wafer or contact packet and copper packing phase key and, and part stitch or contact pass through to wear
Copper material in hole accesses pin or sphere grid array；
S9, packaging, are packaged to the inductive element obtained by step S3 with the key and body of chip wafer.
Further, as shown in figs. 9-11, when making separation layer pedestal in step S6, the breadth correspondence 2 of the matrixnIt is individual
Prepared by integrated device implement scaleization, synchronous forming groove, implementation steps S7, step S8 and step S9 on the matrix, and
Execution step S10 after the completion of encapsulation, according to the specification of integrated device monomer is cut into, wherein the n is positive integer.
Finally：The integrated device of three-dimensional stacked inductive element and chip wafer has relatively broad application feasibility,
The integrated device is at least applied to step down voltage redulator, and linear voltage regulator is depressured PWM switching power supplies, integrated control chip, height
While MOSFET chips, it is low while MOSFET chips voltage-regulation converter, the drop of integrated control chip and flash MOSFET chips
The boost converter of pressure converter, the boost converter of the direct-connected input voltage of inductance, integrated MOSFET and diode, integrated two
The boost converter of power transistor, the type of voltage step-up/down converter that inductor is joined directly together with power on-off control circuit chip, collection
Into the type of voltage step-up/down converter and noise reduction controller of four power transistors, inductance and control chips.As shown in Figure 16 to Figure 21, this
The three-dimensional stacked inductive element of invention and the integrated device of chip wafer, can be by control arbitrarily related in those circuit diagrams
Coremaking piece and inductance carry out the integrated PROCESS FOR TREATMENT of vertical stacking, to realize being greatly optimized for device volume and performance.
The proposition of the three-dimensional stacked integrated device of the present invention and its preparation method and application technology scheme, compared to traditional such device
Part has a significant technique effect, summarize speech including the duty volume and height for greatly reducing the integrated device, and improvement
The ripple voltage of integrated device simultaneously imparts the shielding immunocompetence of strong noise；The integrated device can be widely used in wearable
Among all types of industries such as equipment, smart mobile phone, panel computer, ultrabook, portable medical device and lifestyle device.
It is to be understood that：The above is only the preferred embodiment of the present invention, common for the art
For technical staff, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improve and moisten
Decorations also should be regarded as protection scope of the present invention.
Claims (24)
1. the integrated device of three-dimensional stacked inductive element and chip wafer, it is characterised in that：The perception unit of the integrated device
If if part is made up of magnetic sheet layer and its breadth to the dried layer separation layer of both sides, dried layer copper material layer hot pressing cladding, the integrator
The chip wafer of part be bonded to inductive element breadth to arbitrary side surface, and overall package.
2. the integrated device of three-dimensional stacked inductive element and chip wafer according to claim 1, it is characterised in that：It is described
The magnetic sheet layer of inductive element is the individual layer lamellar body that mixed uniformly magnetic is solidified with spacer medium by resin glue, described
Magnetic only corresponds to a kind of electromagnetic frequency response characteristic.
3. the integrated device of three-dimensional stacked inductive element and chip wafer according to claim 1, it is characterised in that：It is described
The two-layer that the magnetic sheet layer of inductive element is mixed uniformly magnetic to be solidified by resin glue with spacer medium with upper piece,
Electromagnetic frequency response characteristic corresponding to each layer magnetic is different, and separation layer is provided between adjacent two layers.
4. the integrated device of three-dimensional stacked inductive element and chip wafer according to claim 1, it is characterised in that：It is described
Magnetic sheet layer directly offer full thickness to two or more perforation, note is provided with copper material in each perforation, the copper material connection
Separation layer is provided between the copper material layer of magnetic sheet layer both side surface, and each perforation inwall and copper material.
5. the integrated device of three-dimensional stacked inductive element and chip wafer according to claim 1, it is characterised in that：It is described
Magnetic sheet layer is set to bar-shaped lamellar body and is flush-mounted in separation layer pedestal to preset in the groove of shaping, thickness and the groove of the magnetic sheet layer
Depth is identical, the separation layer pedestal offer on the outside of magnetic sheet layer full thickness to two or more perforation, each is worn
Note is provided with copper material between hole, and the copper material connects the copper material layer of magnetic sheet layer both side surface.
6. according to claim 4 or 5 three-dimensional stacked inductive element and chip wafer integrated device, it is characterised in that：
The copper material layer is the printed wiring pattern on magnetic sheet material layer surface separation layer, and copper material layer covers connection respective side institute
There is the copper material in perforation.
7. the integrated device of three-dimensional stacked inductive element and chip wafer according to claim 1, it is characterised in that：It is described
Magnetic sheet layer, to being divided into more than two sections, forms the inductive element that two or more is integrated perpendicular to breadth.
8. the integrated device of three-dimensional stacked inductive element and chip wafer according to claim 1, it is characterised in that：It is described
Chip wafer is a chip with plural stitch, and on the copper packing that draws outside inductive element top layer of each stitch bond.
9. the integrated device of three-dimensional stacked inductive element and chip wafer according to claim 1, it is characterised in that：It is described
Chip wafer is a chip without stitch, and the contact of chip by lead connect the copper packing drawn outside inductive element surface it
On.
10. the integrated device of three-dimensional stacked inductive element and chip wafer according to claim 1, it is characterised in that：Institute
State that chip wafer is the chip with plural stitch and number of chips is two or more, each stitch pair of two or more chip wafer
Should be bonded on the copper packing drawn outside inductive element top layer.
The integrated device of 11. three-dimensional stacked inductive element and chip wafers according to claim 1, it is characterised in that：Institute
State integrated device and be provided with the compound cap of heat, the compound cap of heat is covered in the inductive element and chip wafer and packaging by hot pressing for completing to be bonded.
The integrated device of 12. three-dimensional stacked inductive element and chip wafers according to claim 1, it is characterised in that：Institute
Integrated device is stated in the inductive element and chip wafer periphery for completing to be bonded filled with epoxy encapsulation.
13. according to claim 1,11 or 12 three-dimensional stacked inductive element and chip wafer integrated device, its feature
It is：The integrated device is provided with pin or sphere grid array, and draws the copper material layer at the correspondence perforation of self-induction element.
The preparation method of the integrated device of 14. three-dimensional stacked inductive elements and chip wafer, it is characterised in that including step：
S1, magnetic sheet layer is made, from magnetic, magnetic sheet and spacer medium is uniformly blended into, using resin glue in prefabricated die cavity
Middle curing molding is individual layer or lamellar body more than two-layer；
S2, make inductive element, by top, the basal surface of the magnetic sheet layer obtained by step S1 uniformly be combined one layer of separation layer, and
Magnetic sheet material thickness degree to several perforation are drilled with, the then injection copper material in each perforation, and top, the separation layer of bottom side it is outer
Side surface electroplates copper material layer so that copper material layer is connected with the copper material in perforation, and then the outer surface in copper material layer is combined again one
Layer separation layer, and draw pin or sphere grid array from copper material layer；
S3, bonding chip wafer, if needing to be combined on the separation layer of bond wafer chip-side in the inductive element obtained by step S2
Dry discrete copper packing, the stitch of the chip wafer or contact packet and copper packing phase key and, and part stitch or contact pass through to wear
Copper material in hole accesses pin or sphere grid array；
S4, packaging, are packaged to the inductive element obtained by step S3 with the key and body of chip wafer.
15. according to claim 14 integrated device of three-dimensional stacked inductive element and chip wafer preparation method, its feature
It is：The method punched described in step S2 is diplopore drilling process, from the point of view of boring a hole for any one, first in magnetic sheet material thickness degree
To the hole of drilling first, then fill up spacer medium in first hole and solidify, then the coaxial drill diameter in first hole
The second relatively small hole so that form separation layer between injection copper material therein and magnetic sheet layer.
16. according to claim 14 integrated device of three-dimensional stacked inductive element and chip wafer preparation method, its feature
It is：The method of injection copper material is included in injection copper in perforation and starches and solidify and in perforation inwall plating copper material in step S2.
17. according to claim 16 integrated device of three-dimensional stacked inductive element and chip wafer preparation method, its feature
It is：When the copper material surface for completing to inject does not meet connection copper material layer, mended by plating photoetching process on the copper material surface
Copper is to required level height.
18. according to claim 14 integrated device of three-dimensional stacked inductive element and chip wafer preparation method, its feature
It is：Make described in step S1 in the raw material of magnetic sheet layer, magnetic is optional including iron nickel-molybdenum alloy magnetic, sendust
One of magnetic, ferrum-silicon alloy magnetic powder, iron silicochromium magnetic, iron-nickel alloy magnetic, MnZn alloy magnetic powder, cobalt niobium kirsite magnetic
Or the ferromagnetic oxide powder that two or more magnetics are mixed；Magnetic sheet is optional including manganese-zinc ferrite, the ferrite magnetic of nickel-zinc ferrite
Piece.
19. according to claim 14 integrated device of three-dimensional stacked inductive element and chip wafer preparation method, its feature
It is：The material of the separation layer it is optional including epoxy resin, fire-retardant prepreg, Bismaleimide Triazine blending resin and
One kind during polyimides is vertical.
20. according to claim 14 integrated device of three-dimensional stacked inductive element and chip wafer preparation method, its feature
It is：A kind of method for packing of step S4 is directly to be combined cap using the heat of corresponding specification, and by the compound cap alignment of heat and complete
The key and body of inductive element and chip wafer are covered, then hot pressing completes encapsulation.
21. according to claim 14 integrated device of three-dimensional stacked inductive element and chip wafer preparation method, its feature
It is：A kind of method for packing of step S4 is that the key and body of inductive element and chip wafer are exposed in air, and in bonding
The outside filling epoxy resin of body coats completely inductive element and chip wafer, and cooling completes encapsulation.
The preparation method of the integrated device of 22. three-dimensional stacked inductive elements and chip wafer, it is characterised in that including step：
S5, magnetic sheet layer is made, from magnetic, magnetic sheet and spacer medium is uniformly blended into, using resin glue in prefabricated die cavity
Middle curing molding is individual layer or bar-shaped lamellar body more than two-layer；
S6, separation layer pedestal is made, make breadth, thickness from spacer medium and hybrid adhesive resin solidification and be all higher than magnetic sheet
The matrix of material layer, and by photoetching or etch process matrix breadth to one or both sides surface forming groove, the depth of the groove
Degree is identical with the thickness of the magnetic sheet layer obtained by S5,
S7, making inductive element, in the groove of the matrix that the magnetic sheet layer obtained by step S5 is embedded in obtained by step S6, in magnetic sheet
Top, the basal surface of material layer is uniformly combined one layer of separation layer, and is drilled with several on the outside of the relative magnetic sheet layer of separation layer pedestal
Full thickness to perforation, then each perforation in injection copper material, and top, the separation layer of bottom side outer surface electro-coppering
Material layer so that copper material layer with perforation in copper material connect, then copper material layer outer surface again be combined one layer of separation layer, and oneself
Copper material layer draws pin or sphere grid array；
S8, bonding chip wafer, if needing to be combined on the separation layer of bond wafer chip-side in the inductive element obtained by step S2
Dry discrete copper packing, the stitch of the chip wafer or contact packet and copper packing phase key and, and part stitch or contact pass through to wear
Copper material in hole accesses pin or sphere grid array；
S9, packaging, are packaged to the inductive element obtained by step S3 with the key and body of chip wafer.
23. according to claim 22 integrated device of three-dimensional stacked inductive element and chip wafer preparation method, its feature
It is：When making separation layer pedestal in step S6, the breadth correspondence 2 of the matrixnIt is prepared by individual integrated device implement scaleization,
Synchronous forming groove, implementation steps S7, step S8 and step S9 on the matrix, and execution step S10 after packaging is accomplished, according to
The specification of integrated device cuts into monomer, wherein the n is positive integer.
The application of the integrated device of 24. three-dimensional stacked inductive elements and chip wafer, it is characterised in that：The integrated device is extremely
It is applied to step down voltage redulator less, linear voltage regulator is depressured PWM switching power supplies, integrated control chip, flash MOSFET cores
The step-down controller of the voltage-regulation converter of piece, low side MOSFET chips, integrated control chip and flash MOSFET chips, electricity
Feel the boost converter of the boost converter of direct-connected input voltage, integrated MOSFET and diode, integrated two power transistors
Boost converter, the type of voltage step-up/down converter that inductor and power on-off control circuit chip are joined directly together, integrated four power
The type of voltage step-up/down converter and noise reduction controller of transistor, inductance and control chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610960208.7A CN106601728A (en) | 2016-11-04 | 2016-11-04 | Three-dimensional laminated integrated device of three-dimensional laminated inductive element and wafer chip, and manufacturing method and application thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610960208.7A CN106601728A (en) | 2016-11-04 | 2016-11-04 | Three-dimensional laminated integrated device of three-dimensional laminated inductive element and wafer chip, and manufacturing method and application thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106601728A true CN106601728A (en) | 2017-04-26 |
Family
ID=58589731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610960208.7A Pending CN106601728A (en) | 2016-11-04 | 2016-11-04 | Three-dimensional laminated integrated device of three-dimensional laminated inductive element and wafer chip, and manufacturing method and application thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106601728A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1525631A (en) * | 2003-01-16 | 2004-09-01 | 富士电机电子设备技术株式会社 | Microminiature power converter |
| US20080003408A1 (en) * | 2006-06-30 | 2008-01-03 | Tdk Corporation | Thin film device |
| CN101266868A (en) * | 2007-01-11 | 2008-09-17 | 富士电机电子设备技术株式会社 | Ultra-small electric power conversion device |
| CN104160513A (en) * | 2011-09-06 | 2014-11-19 | 美国亚德诺半导体公司 | Small size and fully integrated power converter with magnetics on chip |
| CN204375745U (en) * | 2015-02-05 | 2015-06-03 | 中国科学院金属研究所 | A kind of miniature thin-film inductance based on iron nickel multicomponent alloy magnetic core |
| US20160172310A1 (en) * | 2014-12-10 | 2016-06-16 | Grenotek Integrated, Inc. | Methods and devices of laminated integrations of semiconductor chips, magnetics, and capacitance |
-
2016
- 2016-11-04 CN CN201610960208.7A patent/CN106601728A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1525631A (en) * | 2003-01-16 | 2004-09-01 | 富士电机电子设备技术株式会社 | Microminiature power converter |
| US20080003408A1 (en) * | 2006-06-30 | 2008-01-03 | Tdk Corporation | Thin film device |
| CN101266868A (en) * | 2007-01-11 | 2008-09-17 | 富士电机电子设备技术株式会社 | Ultra-small electric power conversion device |
| CN104160513A (en) * | 2011-09-06 | 2014-11-19 | 美国亚德诺半导体公司 | Small size and fully integrated power converter with magnetics on chip |
| US20160172310A1 (en) * | 2014-12-10 | 2016-06-16 | Grenotek Integrated, Inc. | Methods and devices of laminated integrations of semiconductor chips, magnetics, and capacitance |
| CN204375745U (en) * | 2015-02-05 | 2015-06-03 | 中国科学院金属研究所 | A kind of miniature thin-film inductance based on iron nickel multicomponent alloy magnetic core |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107046366B (en) | Supply convertor and preparation method thereof | |
| US11094449B2 (en) | Methods and apparatus for isolation barrier with integrated magnetics for high power modules | |
| CN106373709B (en) | Module substrate | |
| US20140266546A1 (en) | High Density Packaging for Efficient Power Processing with a Magnetic Part | |
| US20120217614A1 (en) | Power convertor device and construction methods | |
| WO2014187057A1 (en) | Circuit board and power conversion device with same | |
| JPWO2007129526A1 (en) | Inductor and power supply circuit using the same | |
| Su et al. | High frequency integrated Point of Load (POL) module with PCB embedded inductor substrate | |
| CN107171532B (en) | Power module | |
| US8416047B2 (en) | Inductive components for DC/DC converters and methods of manufacture thereof | |
| CN109003779B (en) | Power module and method for manufacturing the same | |
| CN101483381B (en) | Combined structure | |
| CN105142329B (en) | The suspended substrate stripline circuit and its implementation of multilayer circuit board riveted structure and its composition | |
| KR101338139B1 (en) | Power inductor | |
| CN202695101U (en) | Assembled planar transformer | |
| CN106531716B (en) | Integrated circuit substrate | |
| CN116682799B (en) | High-frequency high-power density module power supply, parallel combination, manufacturing method and soft and hard combination assembly | |
| TWM406265U (en) | Inductance IC chip packaging multi-layer substrate | |
| CN116525244A (en) | Magnetic element, manufacturing method and power circuit using same | |
| CN104934188B (en) | Electron package structure and its method for packing | |
| CN106601728A (en) | Three-dimensional laminated integrated device of three-dimensional laminated inductive element and wafer chip, and manufacturing method and application thereof | |
| CN206471205U (en) | A kind of adjustable flat surface transformer | |
| CN106373733B (en) | A kind of adjustable flat surface transformer and its manufacture method | |
| CN208580741U (en) | Power module | |
| CN204795853U (en) | LTCC -LTCF compound circuit base plate structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170426 |
|
| RJ01 | Rejection of invention patent application after publication |