CN106601725A - Composite sapphire substrate epitaxial LED display module manufacturing method - Google Patents
Composite sapphire substrate epitaxial LED display module manufacturing method Download PDFInfo
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- CN106601725A CN106601725A CN201611079502.3A CN201611079502A CN106601725A CN 106601725 A CN106601725 A CN 106601725A CN 201611079502 A CN201611079502 A CN 201611079502A CN 106601725 A CN106601725 A CN 106601725A
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- 239000000758 substrate Substances 0.000 title claims abstract description 93
- 229910052594 sapphire Inorganic materials 0.000 title claims abstract description 60
- 239000010980 sapphire Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 47
- 239000002131 composite material Substances 0.000 title claims abstract description 38
- 238000000407 epitaxy Methods 0.000 claims abstract description 107
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 238000012360 testing method Methods 0.000 claims abstract description 17
- 230000005496 eutectics Effects 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 9
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 6
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 6
- 238000003801 milling Methods 0.000 claims abstract description 5
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 60
- 230000000873 masking effect Effects 0.000 claims description 50
- 230000012010 growth Effects 0.000 claims description 24
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000002360 preparation method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 13
- 238000011049 filling Methods 0.000 claims description 12
- 238000013461 design Methods 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 3
- 238000001883 metal evaporation Methods 0.000 claims description 3
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 238000000137 annealing Methods 0.000 abstract description 4
- 238000003466 welding Methods 0.000 abstract description 2
- 230000004927 fusion Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
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- 238000003860 storage Methods 0.000 description 2
- 206010052804 Drug tolerance Diseases 0.000 description 1
- 206010068052 Mosaicism Diseases 0.000 description 1
- 208000034699 Vitreous floaters Diseases 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 210000003765 sex chromosome Anatomy 0.000 description 1
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- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
The invention relates to a composite sapphire substrate epitaxial LED display module manufacturing method. The manufacturing method includes that one side surface of a sapphire substrate is patterned and grooved to form a plurality of equally spaced grooves; a groove to be filled is formed between the (3m-2)th groove and the (3m-1)th groove in the plurality of grooves; the silicate solder quantitatively fills the groove to be filled and is heated in a high-temperature furnace device, and after the secondary fusion, a red light epitaxial substrate square sheet is implanted into the filled groove; after the annealing, SiO2 is deposited in the grooves to form an insulation layer; the surface is subjected to milling polishing to obtain an epitaxial composite sapphire substrate; the molecular beam epitaxial MEB epitaxy is carried out to form an LED light-emitting unit array; an epitaxial electrode and a metal wiring layer are prepared on the LED light-emitting unit array; the other side surface of the sapphire substrate is subjected to raster recording; and after the optical testing, the control circuit components and the metal wiring layer are in eutectic welding to form a composite sapphire substrate epitaxial LED display module.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of manufacture of composite sapphire substrate epitaxy LED display module
Method.
Background technology
In traditional semiconductor display production development to today, high density field we habituation be defined as picture
Element is smaller than the display of 1.0mm.But has there is bottleneck in high density field in traditional LED display technique.
Because being limited by the traditional structure of LED/light source, while the material knot after being limited by involved by the module of integrated processing
Structure, driving capacity and structure that for example traditional constant-current source is encapsulated, what the loose material of traditional FR4PCB plates was brought is integrated into
The thermally labile sex chromosome mosaicism of product, and flatness strength problem, and to install the injection mask being spliced into required for giant-screen
With plastic housing etc., all seriously limit breakthrough and application of the LED display technique in high density field.
The content of the invention
The purpose of the present invention is the defect for prior art, there is provided a kind of composite sapphire substrate epitaxy LED shows mould
The manufacture method of group, low cost of manufacture, and also manufacture method is simple and easy to do, is adapted to be applied in Small Distance high density field.
A kind of manufacture method of the epitaxy composite sapphire substrate of LED display modules is embodiments provided, it is described
Method includes：
Fluting is patterned in a side surface of sapphire substrate, multiple equidistant grooves are formed；
Groove to be filled is made between (3m-2) the individual groove and (3m-1) individual groove in the plurality of groove；M is certainly
So count；
Silicate solder is quantitatively inserted in the groove to be filled, and melting is heated in high temperature furnace apparatus；
After second melting, in the filling slot ruddiness epitaxy substrate square piece, and the ruddiness epitaxy substrate are implanted into
Square piece is in same plane with a side surface of the sapphire substrate；
Temperature curve according to the silicate solder is annealed；
SiO is deposited in the groove2, form separation layer；
Polishing of milling is carried out to a side surface, the epitaxy composite sapphire substrate is obtained；
Molecular beam epitaxy MBE epitaxies are carried out on the epitaxy composite sapphire substrate, LED array of light emitting cells is formed；
Epitaxy electrode and metal wiring layer are prepared on the LED array of light emitting cells；
Grating imprinting is carried out to another side surface of the sapphire substrate；
After optic test, control circuit element is welded with the metal wiring layer eutectic, form described compound blue precious
Ground mass plate epitaxy LED display module.
Preferably, described before the filling slot is implanted into ruddiness epitaxy substrate square piece, methods described also includes：
Ruddiness epitaxy disk is carried out thinning；
Cutting scribing is carried out to the ruddiness epitaxy disk after thinning, the ruddiness epitaxy substrate square piece is obtained；Wherein, it is described
Ruddiness epitaxy substrate square piece is GaAs liners.
Preferably, the ruddiness epitaxy substrate square piece has telltale mark；It is described the filling slot be implanted into ruddiness build
Brilliant substrate square piece is specially：
According to the telltale mark, the ruddiness epitaxy substrate square piece and the filling slot are carried out to bit alignment, and will
The ruddiness epitaxy substrate square piece is implanted in the filling slot.
Preferably, it is described that molecular beam epitaxy MBE epitaxies are carried out on the epitaxy composite sapphire substrate, form LED and send out
Light unit array is specifically included：
The first masking layer is prepared on epitaxy composite sapphire substrate, first masking layer is used to shelter except the first color
Other regions outside LED growth districts；The first color LED growth district for correspondence 3m to (3m+1) individual groove it
Between sapphire substrate region；
The first color epitaxial layer is deposited on the first color LED vitellarium and the first masking layer, the first color is formed
LED；The first color epitaxial layer includes the first color N-type epitaxy layer and the first color p-type epitaxial layer of MBE growths；
Remove the first color epitaxial layer on first masking layer and first masking layer；
The second masking layer is prepared, second masking layer is used to shelter other in addition to the second color LED growth district
Region；The second color LED growth district is correspondence (3m-1) to the sapphire substrate region between the 3m groove；
The second color epitaxial layer is deposited on the second color LED vitellarium and the second masking layer, the second color is formed
LED；The second color epitaxial layer includes the second color N-type epitaxy layer and the second color p-type epitaxial layer of MBE growths；
Remove the second color epitaxial layer on second masking layer and second masking layer；
The 3rd masking layer is prepared, the 3rd masking layer is used to shelter other in addition to the 3rd color LED growth district
Region；The second color LED growth district is correspondence (3m-2) to the ruddiness epitaxy substrate between (3m-1) individual groove
The region of square piece；
The 3rd color epitaxial layer is deposited on the 3rd color LED vitellarium and the 3rd masking layer, the 3rd color is formed
LED；The 3rd color epitaxial layer includes the 3rd color N-type epitaxy layer and the 3rd color p-type epitaxial layer；
Remove the 3rd masking layer and the 3rd color epitaxial layer on the 3rd masking layer；
The surface of the epitaxy composite sapphire substrate is ground, is cleaned and electrical testing.
It is further preferred that the preparation method of the masking layer includes：
The physical vapour deposition (PVD) SiO on the epitaxy composite sapphire substrate2；
To SiO2Step Mesa photoetching is carried out, exposes the SiO of designated color LED vitellariums2；
To the SiO for exposing2Perform etching, to expose the epitaxy liner in the designated color LED vitellariums.
Preferably, the epitaxy electrode for preparing on the LED array of light emitting cells is specifically included：
Mesa photoetching and etching are carried out on the LED array of light emitting cells of the epitaxy composite sapphire substrate so that N-type
Epitaxial layer exposes；
Deposit current barrier layer CBL, and carry out CBL photoetching and etching；
Deposit ITO current-diffusion layers, and carry out ITO photoetching and etching；
Anneal the photoetching of laggard row metal layer and surface ashing；
Carry out metal evaporation；
Using stripping technology by the metal removal in addition to electrode；
Deposit passivation layer and after being annealed, is simulated weldability test.
Preferably, it is described to prepare metal wiring layer on the LED array of light emitting cells and specifically include：
The first insulating barrier is deposited in the side surface graphics of the sapphire substrate, and exposes institute in patterned area
State the first electrode and second electrode of LED array of light emitting cells；
Graphically prepare tin indium oxide ITO top layer conductive layers；Wherein, the ITO top layer conductives layer and the first electrode
It is connected；
It is graphical to prepare the second insulating barrier, and expose the second electrode of the LED wafer group in patterned area；
It is graphical to prepare ITO bottom conductive layers；Wherein, the ITO bottoms conductive layer is connected with the second electrode；
Graphical to prepare the 3rd insulating barrier, the ITO top layers according to design exposed portion in patterned area are led
The electric layer and part ITO bottoms conductive layer；
It is graphical to prepare ITO drive control conductive layers；Wherein, the ITO drive controls conductive layer is led including multiple ITO
Line, is connected respectively according to design with the ITO top layer conductives layer or the ITO bottoms conductive layer；
The 4th insulating barrier of graphical deposit；
Make ball-like pins grid array BGA eutectics soldered ball and data cascade terminal.
Preferably, after the making ball-like pins grid array BGA eutectics soldered ball and data cascade terminal, the side
Method also includes：
Terminal is cascaded by the data, electrical testing is carried out to the display module.
The manufacture method of the epitaxy composite sapphire substrate of LED display modules provided in an embodiment of the present invention, manufacturing cost
It is low, and manufacture method is simple and easy to do, is adapted to be applied in Small Distance high density field.
Description of the drawings
Fig. 1 is the manufacture method flow process of the epitaxy composite sapphire substrate of LED display modules provided in an embodiment of the present invention
Figure；
Fig. 2 is one of manufacture process schematic diagram provided in an embodiment of the present invention；
Fig. 3 is the two of manufacture process schematic diagram provided in an embodiment of the present invention；
Fig. 4 is the three of manufacture process schematic diagram provided in an embodiment of the present invention；
Fig. 5 is the four of manufacture process schematic diagram provided in an embodiment of the present invention；
Fig. 6 is the five of manufacture process schematic diagram provided in an embodiment of the present invention；
Fig. 7 is the six of manufacture process schematic diagram provided in an embodiment of the present invention；
Fig. 8 forms LED for the molecular beam epitaxy that carries out on epitaxy composite sapphire substrate provided in an embodiment of the present invention
The method flow diagram of light unit array；
Fig. 9 is the seven of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 10 is the eight of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 11 is the nine of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 12 is the ten of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 13 is the 11 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 14 is the 12 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 15 is the preparation process flow chart of epitaxy electrode provided in an embodiment of the present invention；
Figure 16 is the 13 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 17 is the 14 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 18 is the 15 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 19 is the 16 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 20 is the 17 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 21 is the 18 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 22 is the method flow diagram in the enterprising row metal wiring of epitaxy electrode provided in an embodiment of the present invention；
Figure 23 is the 19 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 24 is the 20 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 25 is the 21 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 26 is the 22 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 27 is the 23 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 28 is the 24 of manufacture process schematic diagram provided in an embodiment of the present invention；
Figure 29 is the 25 of manufacture process schematic diagram provided in an embodiment of the present invention.
Specific embodiment
Below by drawings and Examples, technical scheme is described in further detail.
The present invention composite sapphire substrate epitaxy LED display module manufacture method, be mainly used in 3D LED displays,
Ultra fine pitch 3D LED displays, VHD 3D LED display, 3D LED televisions, 3D LED video walls, 3D LED indicate,
The manufacture of the display floaters in field such as 3D LED special lightings.
Fig. 1 is the manufacture method of composite sapphire substrate epitaxy LED display module provided in an embodiment of the present invention, Fig. 2-figure
29 is the flow chart and schematic diagram of involved idiographic flow in preparation process, below such as Fig. 1 and enter with reference to shown in Fig. 2-Figure 29
Row explanation, being related to step includes：
Step 101, in a side surface of sapphire substrate fluting is patterned, and forms multiple equidistant grooves；
Specifically, before sapphire substrate is patterned fluting, first have to carry out surface to sapphire substrate pre-
Process, the process by milling, cleaning, dry obtains smooth surface to be treated.
During graphical fluting, groove width can determine according to actual needs.Spacing phase between multiple grooves after fluting
Deng.It is concrete as shown in Figure 2.
Step 102, between (3m-2) the individual groove and (3m-1) individual groove in multiple grooves groove to be filled is made；
Specifically, groove to be filled is made between the two of which groove in per adjacent 3 grooves.Any two grooves to be filled it
Between be spaced a complete groove.M is natural number in above-mentioned expression formula.
The depth of groove to be filled is more than the depth of groove, and two side walls of groove to be filled are respectively in a groove
Between.It is concrete as shown in Figure 3.
Step 103, quantitatively inserts silicate solder in groove to be filled, and melting is heated in high temperature furnace apparatus；
Wherein silicate (Soldering Glass, SG) fill solder is quantitatively follow-up to meet in the bottom of groove to be filled
Ruddiness epitaxy substrate square piece is cohered needs and is defined.It is concrete as shown in Figure 4.
Heating melting process is preferably melted twice.
Step 104, after second melting, in filling slot ruddiness epitaxy substrate square piece, and ruddiness epitaxy substrate is implanted into
Square piece is in same plane with a side surface of sapphire substrate；
Certainly, before filling slot is implanted into ruddiness epitaxy substrate square piece, previously prepared ruddiness epitaxy substrate square piece is needed.
Ruddiness epitaxy substrate square piece can carry out thinning obtaining by ruddiness epitaxy disk.Ruddiness epitaxy disk after will be thinning
Cutting scribing is carried out, preferred thickness thinning is 50um, that is, obtain ruddiness epitaxy substrate square piece.Specifically, ruddiness epitaxy substrate
Square piece is the liner of GaAs materials.
The ruddiness epitaxy substrate square piece for preparing has telltale mark.Therefore in implantation, according to telltale mark to red
Light epitaxy substrate square piece and groove to be filled are carried out to bit alignment, and ruddiness epitaxy substrate square piece is implanted in groove to be filled.Such as Fig. 5 institutes
Show.
Step 105, is annealed according to the temperature curve of silicate solder；
Specifically can in the lehr carry out technique.
Step 106, deposits SiO in groove2, form separation layer；
Specifically, as shown in Figure 6.In deposition SiO2After isolated protective layer, SiO2The surface of isolated protective layer can be because deposition
Technique and protrude from substrate surface place plane.
Step 107, to a side surface polishing of milling is carried out, and obtains epitaxy composite sapphire substrate.
Specifically, it is in plane to mill and polish the one side that ruddiness epitaxy substrate square piece is embedded on metacoxal plate.Cleaning, be dried,
After test, it is ready to use in the follow-up LED display modules that prepare and uses.
Resulting epitaxy composite sapphire substrate is as shown in Figure 7.
Step 108, carries out molecular beam epitaxy (MBE) epitaxy on epitaxy composite sapphire substrate, forms LED luminescence units
Array；
As shown in figure 8, the detailed process of this step includes：
Step 201, prepares the first masking layer on epitaxy composite sapphire substrate, and the first masking layer is used to shelter except first
Other regions outside color LED growth district；
Wherein, the first color LED growth district is correspondence 3m to the sapphire substrate area between (3m+1) individual groove
Domain；
The preparation method of masking layer specifically can include：The physical vapour deposition (PVD) SiO on epitaxy composite sapphire substrate2；
To SiO2Step Mesa photoetching is carried out, exposes the SiO of designated color LED vitellariums2；To the SiO for exposing2Perform etching, to
Designated color LED exposes epitaxy liner in vitellarium.As shown in Figure 9.
Following the second masking layer, the preparation of the 3rd masking layer can in this way be performed, therefore subsequently no longer gone to live in the household of one's in-laws on getting married
State.
Step 202, deposits the first color epitaxial layer on the first color LED vitellarium and the first masking layer, forms first
Color LED；
Wherein, the first color epitaxial layer includes the first color N-type epitaxy layer and the first color p-type epitaxial layer of MBE growths.
Step 203, removes the first masking layer and the first color epitaxial layer on the first masking layer；As shown in Figure 10.In figure
Shown first color is blueness, therefore identifies p-type epitaxial layer and N-type epitaxy layer respectively with B-P, B-N.
Step 204, prepares the second masking layer, and the second masking layer is used to shelter in addition to the second color LED growth district
Other regions；
Wherein, the second color LED growth district is correspondence (3m-1) to the sapphire substrate area between the 3m groove
Domain；As shown in figure 11.
Step 205, deposits the second color epitaxial layer on the second color LED vitellarium and the second masking layer, forms second
Color LED；
Wherein, the second color epitaxial layer includes the second color N-type epitaxy layer and the second color p-type epitaxial layer of MBE growths；
Step 206, removes the second masking layer and the second color epitaxial layer on the second masking layer；As shown in figure 12.In figure
Shown second color is blueness, therefore identifies p-type epitaxial layer and N-type epitaxy layer respectively with G-P, G-N.
Step 207, prepares the 3rd masking layer, and the 3rd masking layer is used to shelter in addition to the 3rd color LED growth district
Other regions；
Wherein, the second color LED growth district is correspondence (3m-2) to the ruddiness epitaxy between (3m-1) individual groove
The region of substrate square piece；As shown in figure 13.
Step 208, deposits the 3rd color epitaxial layer on the 3rd color LED vitellarium and the 3rd masking layer, forms the 3rd
Color LED；
Wherein, the 3rd color epitaxial layer includes the 3rd color N-type epitaxy layer and the 3rd color p-type epitaxial layer；
Step 209, removes the 3rd masking layer and the 3rd color epitaxial layer on the 3rd masking layer；As shown in figure 14.In figure
Shown 3rd color is blueness, therefore identifies p-type epitaxial layer and N-type epitaxy layer respectively with R-P, R-N.
Step 210, is ground to the surface of epitaxy composite sapphire substrate, cleans and electrical testing.
After electrical testing is qualified, that is, the preparation of LED array of light emitting cells is completed, continue subsequent step.
Step 109, prepares epitaxy electrode and metal wiring layer on LED array of light emitting cells；
Specifically, the preparation process of epitaxy electrode can specifically as shown in figure 15 comprise the steps：
Step 301, on the LED array of light emitting cells of epitaxy composite sapphire substrate mesa photoetching and etching are carried out, and are made
Obtain N-type epitaxy layer to expose；
Specifically, it is possible to use photoresist (PR) carries out selectively sheltering, and realizes mesa photoetching and etching.The N-type exposed
Epitaxial layer is used as N electrode.There is line of cut between the LED of epitaxy array.Resulting figure is as shown in figure 16.
Step 302, deposits current barrier layer CBL, and carries out CBL photoetching and etching；
Without SiO in figure2Where be it is exposed, as shown in figure 17.
Step 303, deposits ITO current-diffusion layers, and carries out ITO photoetching and etching；As shown in the generalized section of Figure 18.
Then removed photoresist.
Step 304, annealing laggard row metal layer photoetching and surface ashing；
Specifically, by the high-temperature heat treatment of annealing process, forward voltage is advantageously reduced so that current spread layer surface
Contact is formed.
By metal layer lithography, eutectic electrode pattern is formed with photoresist.
Podzolic process is then to use the removing of photoresist by plasma, using oxygen, nitrogen cleaning wafer surface so that wafer surface is more flat
It is whole, and the raising electrode adhesiveness of the negative glue at electrode can be removed.
Structure as shown in figure 19 is obtained after as above step.
Step 305, carries out metal evaporation；
Evaporation metal can include Cr, Ni, Au, Ti, Sn, Al, Cu, AuSn.
Step 306, using stripping technology by the metal removal in addition to electrode, as shown in figure 20.
Step 307, deposits passivation layer and after being annealed, and is simulated weldability test.Resulting structures are as shown in figure 21.
Rta technique is adopted in this step, high-temperature heat treatment is carried out by short annealing, simulate client's use environment
Primary screening is carried out to chip.Weldability test can also be simulated afterwards, to test adhesiveness.
After the completion of prepared by epitaxy electrode, in the enterprising row metal wiring of epitaxy electrode, the solder joint of external connection is formed.Specifically such as
Shown in Figure 22, its detailed process includes：
Step 401, in the side surface graphics of sapphire substrate the first insulating barrier is deposited, and is revealed in patterned area
Go out the first electrode and second electrode of LED array of light emitting cells；As shown in border circular areas in Figure 23.
Step 402, graphically prepares tin indium oxide ITO top layer conductive layers；Wherein, ITO top layer conductives layer and first electrode
It is connected；As shown in figure 24.
Step 403, it is graphical to prepare the second insulating barrier, and expose the second electrode of LED wafer group in patterned area；
Step 404, it is graphical to prepare ITO bottom conductive layers；Wherein, ITO bottoms conductive layer is connected with second electrode；Such as
Shown in Figure 25.
Step 405, graphical to prepare the 3rd insulating barrier, according to design, exposed portion ITO is pushed up in patterned area
Layer conductive layer and part ITO bottom conductive layers；
Step 406, it is graphical to prepare ITO drive control conductive layers；Wherein, ITO drive controls conductive layer includes multiple ITO
Wire, is connected respectively according to design with ITO top layer conductives layer or ITO bottom conductive layers；As shown in figure 26.
Step 407, the 4th insulating barrier of graphical deposit；
Step 408, makes ball-like pins grid array (BGA) eutectic soldered ball and data cascade terminal.
Step 409, by data terminal is cascaded, and to display module electrical testing is carried out.
When surveying by the rear preparation process for completing electrical connections, also need to, into line raster imprinting, going out light afterwards
Grating is formed on face.
Step 110, to another side surface of sapphire substrate grating imprinting is carried out；As shown in figure 28.
Step 111, after optic test, control circuit element and metal wiring layer eutectic is welded, and forms compound blue precious
Ground mass plate epitaxy LED display module.
In the composite sapphire substrate epitaxy LED display module as shown in 29, the control circuit element of eutectic welding is
Drive control IC, and add radiator structure.
In other specific embodiments, can also be substituted using the control board that the discrete devices such as FPGA are built
Control circuit element.
The manufacture method of composite sapphire substrate epitaxy LED display module provided in an embodiment of the present invention, low cost of manufacture,
And manufacture method is simple and easy to do, it is particularly suited for high density LED display field, disclosure satisfy that high density, small pixel pitch neck
The display demand in domain.
Professional should further appreciate that, with reference to each example of the embodiments described herein description
Unit and algorithm steps, can with electronic hardware, computer software or the two be implemented in combination in, it is hard in order to clearly demonstrate
The interchangeability of part and software, according to function has generally described the composition and step of each example in the above description.
These functions are performed with hardware or software mode actually, depending on the application-specific and design constraint of technical scheme.
Professional and technical personnel can use different methods to realize described function to each specific application, but this realization
It is not considered that beyond the scope of this invention.
Can be with hardware, computing device with reference to the method for the embodiments described herein description or the step of algorithm
Software module, or the combination of the two is implementing.Software module can be placed in random access memory (RAM), internal memory, read-only storage
(ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of storage medium well known to interior.
Above-described specific embodiment, has been carried out further to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail, should be understood that the specific embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, done etc. all should include
Within protection scope of the present invention.
Claims (8)
1. a kind of manufacture method of composite sapphire substrate epitaxy LED display module, it is characterised in that methods described includes：
Fluting is patterned in a side surface of sapphire substrate, multiple equidistant grooves are formed；
Groove to be filled is made between (3m-2) the individual groove and (3m-1) individual groove in the plurality of groove；M is natural number；
Silicate solder is quantitatively inserted in the groove to be filled, and melting is heated in high temperature furnace apparatus；
After second melting, in the filling slot ruddiness epitaxy substrate square piece, and the ruddiness epitaxy substrate square piece are implanted into
Same plane is in a side surface of the sapphire substrate；
Temperature curve according to the silicate solder is annealed；
SiO is deposited in the groove2, form separation layer；
Polishing of milling is carried out to a side surface, the epitaxy composite sapphire substrate is obtained；
Molecular beam epitaxy MBE epitaxies are carried out on the epitaxy composite sapphire substrate, LED array of light emitting cells is formed；
Epitaxy electrode and metal wiring layer are prepared on the LED array of light emitting cells；
Grating imprinting is carried out to another side surface of the sapphire substrate；
After optic test, control circuit element is welded with the metal wiring layer eutectic, form the composite sapphire base
Plate epitaxy LED display module.
2. manufacture method according to claim 1, it is characterised in that described to be implanted into ruddiness epitaxy lining in the filling slot
Before the square piece of bottom, methods described also includes：
Ruddiness epitaxy disk is carried out thinning；
Cutting scribing is carried out to the ruddiness epitaxy disk after thinning, the ruddiness epitaxy substrate square piece is obtained；Wherein, the ruddiness
Epitaxy substrate square piece is GaAs liners.
3. preparation method according to claim 1, it is characterised in that the ruddiness epitaxy substrate square piece has positioning mark
Note；It is described to be implanted into ruddiness epitaxy substrate square piece in the filling slot and be specially：
According to the telltale mark, the ruddiness epitaxy substrate square piece and the filling slot are carried out to bit alignment, and will be described
Ruddiness epitaxy substrate square piece is implanted in the filling slot.
4. preparation method according to claim 1, it is characterised in that described enterprising in the epitaxy composite sapphire substrate
Row molecular beam epitaxy MBE epitaxies, form LED array of light emitting cells and specifically include：
The first masking layer is prepared on epitaxy composite sapphire substrate, first masking layer is used to shelter except the first color LED
Other regions outside growth district；The first color LED growth district is correspondence 3m between (3m+1) individual groove
Sapphire substrate region；
The first color epitaxial layer is deposited on the first color LED vitellarium and the first masking layer, the first color LED is formed；
The first color epitaxial layer includes the first color N-type epitaxy layer and the first color p-type epitaxial layer of MBE growths；
Remove the first color epitaxial layer on first masking layer and first masking layer；
The second masking layer is prepared, second masking layer is used to shelter other regions in addition to the second color LED growth district；
The second color LED growth district is correspondence (3m-1) to the sapphire substrate region between the 3m groove；
The second color epitaxial layer is deposited on the second color LED vitellarium and the second masking layer, the second color LED is formed；
The second color epitaxial layer includes the second color N-type epitaxy layer and the second color p-type epitaxial layer of MBE growths；
Remove the second color epitaxial layer on second masking layer and second masking layer；
The 3rd masking layer is prepared, the 3rd masking layer is used to shelter other regions in addition to the 3rd color LED growth district；
The second color LED growth district is correspondence (3m-2) to the ruddiness epitaxy substrate square piece between (3m-1) individual groove
Region；
The 3rd color epitaxial layer is deposited on the 3rd color LED vitellarium and the 3rd masking layer, the 3rd color LED is formed；
The 3rd color epitaxial layer includes the 3rd color N-type epitaxy layer and the 3rd color p-type epitaxial layer；
Remove the 3rd masking layer and the 3rd color epitaxial layer on the 3rd masking layer；
The surface of the epitaxy composite sapphire substrate is ground, is cleaned and electrical testing.
5. preparation method according to claim 4, it is characterised in that the preparation method of the masking layer includes：
The physical vapour deposition (PVD) SiO on the epitaxy composite sapphire substrate2；
To SiO2Step Mesa photoetching is carried out, exposes the SiO of designated color LED vitellariums2；
To the SiO for exposing2Perform etching, to expose the epitaxy liner in the designated color LED vitellariums.
6. preparation method according to claim 1, it is characterised in that described to prepare on the LED array of light emitting cells
Epitaxy electrode is specifically included：
Mesa photoetching and etching are carried out on the LED array of light emitting cells of the epitaxy composite sapphire substrate so that N-type extension
Layer exposes；
Deposit current barrier layer CBL, and carry out CBL photoetching and etching；
Deposit ITO current-diffusion layers, and carry out ITO photoetching and etching；
Anneal the photoetching of laggard row metal layer and surface ashing；
Carry out metal evaporation；
Using stripping technology by the metal removal in addition to electrode；
Deposit passivation layer and after being annealed, is simulated weldability test.
7. preparation method according to claim 1, it is characterised in that described to prepare on the LED array of light emitting cells
Metal wiring layer is specifically included：
The first insulating barrier is deposited in the side surface graphics of the sapphire substrate, and is exposed in patterned area described
The first electrode and second electrode of LED array of light emitting cells；
Graphically prepare tin indium oxide ITO top layer conductive layers；Wherein, the ITO top layer conductives layer is connected with the first electrode
Connect；
It is graphical to prepare the second insulating barrier, and expose the second electrode of the LED wafer group in patterned area；
It is graphical to prepare ITO bottom conductive layers；Wherein, the ITO bottoms conductive layer is connected with the second electrode；
It is graphical to prepare the 3rd insulating barrier, the ITO top layer conductive layers according to design exposed portion in patterned area
ITO bottoms conductive layer described with part；
It is graphical to prepare ITO drive control conductive layers；Wherein, the ITO drive controls conductive layer includes multiple ITO wires, point
It is not connected with the ITO top layer conductives layer or the ITO bottoms conductive layer according to design；
The 4th insulating barrier of graphical deposit；
Make ball-like pins grid array BGA eutectics soldered ball and data cascade terminal.
8. preparation method according to claim 1, it is characterised in that be total in the making ball-like pins grid array BGA
After brilliant soldered ball and data cascade terminal, methods described also includes：
Terminal is cascaded by the data, electrical testing is carried out to the display module.
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| CN110853516A (en) * | 2019-11-21 | 2020-02-28 | 青岛歌尔智能传感器有限公司 | Display assembly, manufacturing method thereof and electronic equipment |
| CN113696524A (en) * | 2021-08-11 | 2021-11-26 | 苏州易锐光电科技有限公司 | Micro-nano processing method of optical device |
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