CN106601479A - Three-dimensional silicon chip type thin-film capacitor and manufacturing method thereof - Google Patents
Three-dimensional silicon chip type thin-film capacitor and manufacturing method thereof Download PDFInfo
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- CN106601479A CN106601479A CN201710103351.9A CN201710103351A CN106601479A CN 106601479 A CN106601479 A CN 106601479A CN 201710103351 A CN201710103351 A CN 201710103351A CN 106601479 A CN106601479 A CN 106601479A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 101
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 101
- 239000010703 silicon Substances 0.000 title claims abstract description 101
- 239000003990 capacitor Substances 0.000 title claims abstract description 48
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000010931 gold Substances 0.000 claims abstract description 37
- 229910052737 gold Inorganic materials 0.000 claims abstract description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 20
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 25
- 239000001301 oxygen Substances 0.000 claims description 24
- 229910052760 oxygen Inorganic materials 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 21
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 18
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 18
- 238000004544 sputter deposition Methods 0.000 claims description 17
- 238000004140 cleaning Methods 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- 239000010408 film Substances 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 239000002346 layers by function Substances 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 230000008719 thickening Effects 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 239000003643 water by type Substances 0.000 claims description 2
- 238000013019 agitation Methods 0.000 claims 1
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 239000011247 coating layer Substances 0.000 abstract 2
- 238000004891 communication Methods 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 208000035985 Body Odor Diseases 0.000 description 1
- 206010055000 Bromhidrosis Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001588 bifunctional effect Effects 0.000 description 1
- 238000002242 deionisation method Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a three-dimensional silicon chip type thin-film capacitor and a manufacturing method thereof. The three-dimensional silicon chip type thin-film capacitor comprises a silicon substrate, micro holes manufactured on the silicon substrate, a thin-film capacitor function layer and a top electrode layer formed in the holes, and a bottom electrode layer at the backside of the silicon substrate, the silicon substrate is a silicon substrate with low resistivity, the lattice orientation is 100, the function layer is a double-layer structure of silicon dioxide and silicon nitride, the top electrode layer comprises a titanium-tungsten bottom-coating layer and a gold layer, and the bottom electrode layer comprises a titanium-tungsten bottom-coating layer and a gold layer. According to the three-dimensional silicon chip type thin-film capacitor, the size is small, the loss is low, the insulation resistance is high, the temperature coefficient is small, and the equivalent series resistance and the equivalent series inductance are low; besides, the manufacturing process of the thin-film capacitor is compatible with the semiconductor technology, the performance is stable, the thin-film capacitor can be widely applied to the fields of aerospace, military radar, computer communication, portable electronic equipment, automobile energy, and household electronics etc., the market prospect is very wide, and the business value is huge.
Description
Technical field
The present invention relates to field of capacitor manufacture, specifically relates to a kind of three-dimensional silicon chip formula thin film capacitor and its manufacturer
Method.
Background technology
With the development of electronic technology, electronics and information industry enters rear mole of epoch.It is shared in passive device assist side
Volume ratio is also increasing, outstanding day by day with the contradiction of the development trend of electronic circuit " miniaturization, integrated, intellectuality ".For
Solve this outstanding day by day contradiction, capacitor as most basic passive device, its can not exempt from will towards small volume,
Capacity is big, and low in energy consumption, the direction of stable performance is developed.
In the case where volume is not changed, the increase of the capacitance of capacitor can be by using high K dielectric material, increase
Electrode area is realized with the mode for reducing electrode spacing；Being existed on the temperature characterisitic of capacitor using meeting for high K dielectric is affected；
Reducing electrode spacing necessarily causes the resistance to electricity of the medium of capacitor to reduce.Therefore, only electronics is met by increasing electrode area
The demand of circuit " miniaturization, integrated, intellectuality ".
Silicon materials are prepared convenient and are widely used in semiconductor industry because of its function admirable, low price.
Three-dimensional silicon chip formula thin film capacitor is mainly used in Aero-Space, military radar, compunication, portable electric
The fields such as sub- equipment, energy source of car, domestic electronic.With the continuous progress of the manufacturing technology of silica-base film capacitor, its performance
Lifting will be continuously available, range of application will constantly expand, and then promote the development of silicon substrate class device technology, improve first device of China
Part technical merit, makes the electronic component products quality and gear time of China to higher development, with important social benefit.
The content of the invention
Goal of the invention：The present invention provides a kind of small volume, is lost and low, resistance to stings high pressure, insulation resistance are high, temperature coefficient is little etc.
The three-dimensional silicon chip formula thin film capacitor and its manufacture method of effect series resistance and the low feature of equivalent series inductance.
Technical scheme：A kind of three-dimensional silicon chip formula thin film capacitor, including silicon substrate, miniature hole, silicon oxide layer, nitridation
Silicon layer, top prime coat, top-gold layer, back prime coat and back layer gold, the silicon substrate side be burnishing surface, the burnishing surface
It is provided with several micro- shape holes；Micro- shape hole inwall of the silicon substrate and bottom are provided with silicon oxide layer, on silicon oxide layer
It is provided with silicon nitride layer；The top prime coat is arranged on silicon nitride layer, and top-gold layer, the back of the body are arranged on the prime coat of top
Portion's prime coat is arranged on the opposite side of silicon substrate, and back layer gold is provided with the prime coat of back.
Specifically, the silicon silicon substrate be silicon materials, single-sided polishing, roughness requirements 0.05～0.1, crystal orientation 100, the silicon
Material is low-resistance rate silicon substrate, and resistivity requires to be less than 0.01 Ω cm, and silicon substrate body thickness is not less than 400 μm.
Specifically, 2-10 μm of the aperture of micro- shape hole, hole depth 5-80 μm.
Specifically, the top prime coat and back prime coat are titanium-tungsten, 150～200nm of thickness；Top-gold thickness
Spend for 2～4 μm, thickeied using plating mode.
Specifically, the back layer gold adopts sputter coating mode, 0.8～1.5 μm of thickness.
A kind of manufacture method of three-dimensional silicon chip formula thin film capacitor, comprises the following steps：
Step 1, cleaning：Choose low-resistivity silicon substrate, i.e. resistivity and be less than 0.01 Ω cm, thickness is not less than 400 μm,
Single-sided polishing, 100 crystal orientation silicon substrates；With No. 1 silicon chip cleaning liquid of standard, No. 2 silicon chip cleaning liquids, acetone, ethanol and deionizations
Water cleaning is dried, standby to treat；
Step 2, thermal oxide：Silicon substrate is sent into and carry out in oxidation furnace dry-oxygen oxidation, 780 DEG C of temperature, nitrogen 10L/min,
Oxygen 6L/min, 20～60min of time；
Step 3, photoetching：Spin coating；Toast 90 ± 10 seconds on 95～110 DEG C of hot plate；Selection appropriate mask version, 15
The exposure of ± 5 second time；Development；Etching window is formed with 8% HF solution corrosions silicon dioxide layer；Finally at 120 ± 10 DEG C
Hot plate on dry 5～10 minutes；
Step 4, hole etching：Using Bosch lithographic technique, hole etching is carried out in ICP etching machines；2-10 μm of aperture,
Hole depth 5-80 μm, etching parameters：Coil power 500W, pole plate power 20W, cavity air pressure 3.5Pa, SF6Flow 135mL/min,
C4F8Flow 8mL/min, oxygen flow 8mL/min, etch period 7 seconds；Passivation parameter：Coil power 500W, pole plate power 0, chamber
Bromhidrosis press 2.5Pa, SF6Flow 0, C4F8Flow 80mL/min, oxygen flow 0, passivation time 3 seconds；
Step 5, cleaning, with the silicon substrate of 8% HF solution rinsing Jing holes etching, then with acetone, ethanol and go from
Sub- water cleaning is dried, in case thermal oxide；
Step 6, thermal oxide：Silicon substrate is sent into and carry out in oxidation furnace dry-oxygen oxidation formation silicon dioxide layer, temperature 780
DEG C, nitrogen 10L/min, oxygen 6L/min, 20～60min of time；
Step 7, passivation layer lamination：Deposit silicon nitride film 3 is carried out in silicon substrate feeding PECVD stoves, deposition parameter：Pole
350 DEG C of plate temperature, operating air pressure 25Pa, power 400W, ammonia flow 25sccm, silane 50sccm, nitrogen 150sccm, time 5
～15min；
Step 8, annealing：Silicon substrate is sent in annealing furnace carries out nitrogen atmosphere annealing, and 780 DEG C of annealing temperature is moved back
30 minutes fiery time；
Step 9, top electrode sputtering：With the method for magnetron sputtering, successively titanium tungsten is beaten at the top of sputtering in the functional layer of silicon substrate
Bottom and top-gold layer；
Step 10, plating：Gold-plated thickening, 2～4 μm of layer gold thickness are carried out to top-gold layer；
Step 11, photoetching：Carry out gluing；Toast 90 ± 10 seconds on 95～110 DEG C of hot plate；Time of exposure 10 ± 3 seconds；
Development；Etching top-gold layer and top titanium tungsten prime coat；Remove photoresist；It is last to dry 5～10 minutes on 120 ± 10 DEG C of hot plate；
Step 12, back is thinning：Using the thinning machine of silicon substrate, silicon substrate 1 is carried out using the method for mechanical reduction it is thinning,
100～120 μm of thickness requirement；
Step 13, cleaning：Clean silicon substrate with acetone, ethanol and deionized water successively and dry, it is stand-by；
Step 14, hearth electrode sputtering：With the method for magnetron sputtering successively in the back spatter back titanium tungsten bottoming of silicon substrate
Layer and back layer gold；
Step 15, scribing cutting：Using the method for machine cuts, scribing cutting is carried out to silicon substrate, prepared size meets
The capacitor of requirement.
More specifically, the step 9, in 14, titanium tungsten prime coat thickness is 150 ± 10nm；Sputtering power 400W, silicon substrate
200～400 DEG C of temperature, 100 ± 1sccm of argon flow amount, background vacuum 7 × 10-4Pa。
More specifically, the dry carrier of oxygen of the step 6 is oxygen and the mixed gas of nitrogen institute, being passed through for nitrogen is stirred in cavity
Oxygen.
More specifically, the thickness after silicon substrate is thinning in the step 9 is 100～120 μm.
More specifically, hearth electrode layer gold sputtering time is 20 ± 2min in the step 14.
Beneficial effect：Compared with prior art, it is an advantage of the current invention that：The three-dimensional silicon chip formula thin-film capacitor of the present invention
Device increases the electrode area of capacitor using the method that hole is carved on silicon substrate surface, realizes under identical capacitance, maximum limit
The volume of capacitor is reduced degree, improves the performance of capacitor；With small volume, low, high pressure, insulation resistance is lost
Height, temperature coefficient little (50ppm/ DEG C), equivalent series resistance (400m Ω) and the low feature of equivalent series inductance (400pH)；By
Simple in the manufacturing process of three-dimensional silicon chip formula thin film capacitor, stable performance is compatible with semiconductor technology, can make on a large scale
Make.
Description of the drawings
Fig. 1 is the structural representation of the present invention.
Specific embodiment
With reference to the accompanying drawings and detailed description, the present invention is further elucidated.
As shown in figure 1, a kind of three-dimensional silicon chip formula thin film capacitor, including silicon substrate 1, miniature hole 8, silicon oxide layer 2,
Silicon nitride layer 3, top prime coat 4, top-gold layer 5, back prime coat 6 and back layer gold 7, on the burnishing surface of the silicon substrate 1
Etching forms micro- shape hole 8, on the burnishing surface of the silicon substrate and micro- shape hole inwall and bottom formation silicon oxide layer 2,
Silicon nitride layer 3 is formed on silicon oxide layer 2, the top prime coat 4 is arranged on silicon nitride layer 3, is arranged on top prime coat 4
Top-gold layer 5, the back prime coat 6 is arranged on the back side of silicon substrate 1, and sputter coating forms back on back prime coat 6
Layer gold 7.
Wherein, matrix is silicon materials, and matrix is low-resistance rate silicon substrate 1, and resistivity requires to be less than 0.01 Ω cm, low resistance
Rate silicon base 1 can further reduce the loss of capacitor；In capacitor internal, electric current flows to back electrode by miniature hole, respectively
Resistance between individual hole forms parallel connection, and hole count is more, and the ESR and ESL of capacitor is less, and loss is lower, and matrix
For single-sided polishing, roughness requirements 0.05～0.1, such roughness ensure that metal film is good and be attached on matrix 1.
2-10 μm of the aperture of micro- shape hole, hole depth 5-80 μm；Under identical volume, the bottom of miniature hole and side wall
Product causes the electrode pad gross area of capacitor to increase, and correspondingly, the pressure voltage of capacitor is also increased, using miniature hole
Method, can cause capacitor pressure voltage improve 5～10 times.
Silicon oxide layer 2 and silicon nitride layer collectively form the functional layer of thin film capacitor, and bifunctional layer cooperates, effectively drop
The probability that low particle runs through in capacitor, improves the stability and pressure voltage of capacitor.
Top prime coat and back prime coat be titanium-tungsten, 150～200nm of thickness.
Top-gold layer thickness is 2～4 μm, is thickeied using plating mode.
Back layer gold realized using sputter coating mode, 0.8～1.5 μm of thickness.
The three-dimensional silicon chip formula thin film capacitor is manufactured by following steps：
A. clean：Low-resistivity silicon substrate 1 (resistivity is less than 0.01 Ω cm) is chosen, thickness is not less than 400 μm, one side
Polishing, 100 crystal orientation silicon substrates 1；It is clear with No. 1 silicon chip cleaning liquid of standard, No. 2 silicon chip cleaning liquids, acetone, ethanol and deionized waters
Drying is washed, it is standby to treat；
B. thermal oxide：Silicon substrate 1 is sent into and carry out in oxidation furnace dry-oxygen oxidation, 780 DEG C of temperature, nitrogen 10L/min, oxygen
6L/min, 20～60min of time；
C. photoetching：Spin coating；Toast 90 ± 10 seconds on 95～110 DEG C of hot plate；Selection appropriate mask version, 15 ± 5
The exposure of time second；Development；Etching window is formed with 8% HF solution corrosions silicon dioxide layer；The last heat at 120 ± 10 DEG C
Dry 5～10 minutes on plate；
D. hole is etched：Using Bosch lithographic technique, hole etching is carried out in ICP etching machines；2-10 μm of aperture, hole depth
5-80μm.Etching parameters：Coil power 500W, pole plate power 20W, cavity air pressure 3.5Pa, SF6Flow 135mL/min, C4F8Stream
Amount 8mL/min, oxygen flow 8mL/min, etch period 7 seconds；Passivation parameter：Coil power 500W, pole plate power 0, cavity gas
Pressure 2.5Pa, SF6Flow 0, C4F8Flow 80mL/min, oxygen flow 0, passivation time 3 seconds；
E. clean, with the silicon substrate of 8% HF solution rinsing Jing hole etchings, then with acetone, ethanol and deionized water
Cleaning is dried, in case thermal oxide；
F. thermal oxide：Silicon substrate 1 is sent into and carry out in oxidation furnace dry-oxygen oxidation formation silicon dioxide layer 2,780 DEG C of temperature,
Nitrogen 10L/min, oxygen 6L/min, oxidization time, 20～60min of ordinary circumstance are determined according to the thickness of theoretical simulation；
G. passivation layer deposition：Silicon substrate 1 is sent into and carry out in PECVD stoves silicon nitride film 3 and deposit, deposition parameter：Pole plate
350 DEG C of temperature, operating air pressure 25Pa, power 400W, ammonia flow 25sccm, silane 50sccm, nitrogen 150sccm, the time 5～
15min；
H. make annealing treatment：Silicon substrate is sent in annealing furnace carries out nitrogen atmosphere annealing, 780 DEG C of annealing temperature, during annealing
Between 30 minutes；
I. top electrode sputtering：With the method titanium tungsten bottoming at the top of sputtering on the functional plane of silicon substrate successively of magnetron sputtering
Layer and top-gold layer；
J. electroplate：Gold-plated thickening, 2～4 μm of layer gold thickness are carried out to top electrode layer gold 5；
K. photoetching：Carry out gluing；Toast 90 ± 10 seconds on 95～110 DEG C of hot plate；Time of exposure 10 ± 3 seconds；Development；
Etching top-gold layer and top titanium tungsten layer；Remove photoresist；It is last to dry 5～10 minutes on 120 ± 10 DEG C of hot plate；
L. back is thinning：Using the thinning machine of silicon substrate, silicon substrate is carried out using the method for mechanical reduction it is thinning, thickness will
Ask 100～120 μm；
M. clean：Clean silicon substrate with acetone, ethanol and deionized water successively and dry, it is stand-by；
N. hearth electrode sputtering：With the method for magnetron sputtering successively in the back spatter back titanium tungsten prime coat and the back of the body of silicon substrate
Portion's layer gold；
O. scribing cutting：Using the method for machine cuts, scribing cutting is carried out to silicon substrate 1, be obtained and be of the required size
Capacitor.
Claims (10)
1. a kind of three-dimensional silicon chip formula thin film capacitor, it is characterised in that：Including silicon substrate, miniature hole, silicon oxide layer, nitridation
Silicon layer, top prime coat, top-gold layer, back prime coat and back layer gold, the silicon substrate side be burnishing surface, the burnishing surface
It is provided with several micro- shape holes；Micro- shape hole inwall of the silicon substrate and bottom are provided with silicon oxide layer, on silicon oxide layer
It is provided with silicon nitride layer；The top prime coat is arranged on silicon nitride layer, and top-gold layer, the back of the body are arranged on the prime coat of top
Portion's prime coat is arranged on the opposite side of silicon substrate, and back layer gold is provided with the prime coat of back.
2. a kind of three-dimensional silicon chip formula thin film capacitor according to claim 1, it is characterised in that：The silicon substrate is silicon
Material, single-sided polishing, roughness requirements 0.05～0.1, crystal orientation 100, the silicon materials are low-resistance rate silicon substrate, and resistivity requires little
In 0.01 Ω cm, silicon substrate body thickness is not less than 400 μm.
3. a kind of three-dimensional silicon chip formula thin film capacitor according to claim 1, it is characterised in that：Micro- shape hole
2-10 μm of aperture, hole depth 5-80 μm.
4. a kind of three-dimensional silicon chip formula thin film capacitor according to claim 1, it is characterised in that：The top prime coat
With back prime coat be titanium-tungsten, 150～200nm of thickness；Top-gold layer thickness is 2～4 μm, is thickeied using plating mode.
5. a kind of three-dimensional silicon chip formula thin film capacitor according to claim 1, it is characterised in that：The back layer gold is adopted
Realized with sputter coating mode, 0.8～1.5 μm of thickness.
6. the manufacture method of a kind of three-dimensional silicon chip formula thin film capacitor according to claim 1-5 any one, it is special
Levy and be, comprise the following steps：
Step 1, cleaning：Choose low-resistivity silicon substrate, i.e. resistivity and be less than 0.01 Ω cm, thickness is not less than 400 μm, one side
Polishing, 100 crystal orientation silicon substrates；It is clear with No. 1 silicon chip cleaning liquid of standard, No. 2 silicon chip cleaning liquids, acetone, ethanol and deionized waters
Drying is washed, it is standby to treat；
Step 2, thermal oxide：Silicon substrate is sent in oxidation furnace carries out dry-oxygen oxidation, 780 DEG C of temperature, nitrogen 10L/min, oxygen
6L/min, 20～60min of time；
Step 3, photoetching：Spin coating；Toast 90 ± 10 seconds on 95～110 DEG C of hot plate；Selection appropriate mask version, 15 ± 5
The exposure of time second；Development；Etching window is formed with 8% HF solution corrosions silicon dioxide layer；The last heat at 120 ± 10 DEG C
Dry 5～10 minutes on plate；
Step 4, hole etching：Using Bosch lithographic technique, hole etching is carried out in ICP etching machines；2-10 μm of aperture, hole depth
5-80 μm, etching parameters：Coil power 500W, pole plate power 20W, cavity air pressure 3.5Pa, SF6Flow 135mL/min, C4F8Stream
Amount 8mL/min, oxygen flow 8mL/min, etch period 7 seconds；Passivation parameter：Coil power 500W, pole plate power 0, cavity gas
Pressure 2.5Pa, SF6Flow 0, C4F8Flow 80mL/min, oxygen flow 0, passivation time 3 seconds；
Step 5, cleaning, with the silicon substrate of 8% HF solution rinsing Jing hole etchings, then with acetone, ethanol and deionized water
Cleaning is dried, in case thermal oxide；
Step 6, thermal oxide：Silicon substrate is sent into and carry out in oxidation furnace dry-oxygen oxidation formation silicon dioxide layer, 780 DEG C of temperature, nitrogen
Gas 10L/min, oxygen 6L/min, 20～60min of time；
Step 7, passivation layer lamination：Deposit silicon nitride film 3 is carried out in silicon substrate feeding PECVD stoves, deposition parameter：Pole plate temperature
350 DEG C of degree, operating air pressure 25Pa, power 400W, ammonia flow 25sccm, silane 50sccm, nitrogen 150sccm, the time 5～
15min；
Step 8, annealing：Silicon substrate is sent in annealing furnace carries out nitrogen atmosphere annealing, 780 DEG C of annealing temperature, during annealing
Between 30 minutes；
Step 9, top electrode sputtering：With the method for the magnetron sputtering successively titanium tungsten prime coat at the top of sputtering in the functional layer of silicon substrate
And top-gold layer；
Step 10, plating：Gold-plated thickening, 2～4 μm of layer gold thickness are carried out to top-gold layer；
Step 11, photoetching：Carry out gluing；Toast 90 ± 10 seconds on 95～110 DEG C of hot plate；Time of exposure 10 ± 3 seconds；It is aobvious
Shadow；Etching top-gold layer and top titanium tungsten prime coat；Remove photoresist；It is last to dry 5～10 minutes on 120 ± 10 DEG C of hot plate；
Step 12, back is thinning：Using the thinning machine of silicon substrate, thinning, thickness is carried out to silicon substrate 1 using the method for mechanical reduction
Require 100～120 μm；
Step 13, cleaning：Clean silicon substrate with acetone, ethanol and deionized water successively and dry, it is stand-by；
Step 14, hearth electrode sputtering：With the method for magnetron sputtering successively silicon substrate back spatter back titanium tungsten prime coat and
Back layer gold；
Step 15, scribing cutting：Using the method for machine cuts, scribing cutting is carried out to silicon substrate, be obtained and be of the required size
Capacitor.
7. the manufacture method of a kind of three-dimensional silicon chip formula thin film capacitor according to claim 6, it is characterised in that：It is described
Step 9, in 14, titanium tungsten prime coat thickness is 150 ± 10nm；Sputtering power 400W, 200～400 DEG C of silicon substrate temperature, argon stream
100 ± 1sccm of amount, background vacuum 7 × 10-4Pa。
8. the manufacture method of a kind of three-dimensional silicon chip formula thin film capacitor according to claim 6, it is characterised in that：It is described
The dry carrier of oxygen of step 6 is oxygen and the mixed gas of nitrogen, the oxygen being passed through in agitation cavity of nitrogen.
9. the manufacture method of a kind of three-dimensional silicon chip formula thin film capacitor according to claim 6, it is characterised in that：It is described
Thickness after silicon substrate is thinning in step 9 is 100～120 μm.
10. the manufacture method of a kind of three-dimensional silicon chip formula thin film capacitor according to claim 6, it is characterised in that：Institute
It is 20 ± 2min to state hearth electrode layer gold sputtering time in step 14.
Priority Applications (1)
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| CN111902899A (en) * | 2018-06-15 | 2020-11-06 | 株式会社村田制作所 | Capacitor and method for manufacturing the same |
| CN112490001A (en) * | 2020-11-23 | 2021-03-12 | 桂林电子科技大学 | Preparation method of chip capacitor |
| CN113012939A (en) * | 2021-02-22 | 2021-06-22 | 四川大学 | High-voltage-resistant low-loss silicon-based film capacitor and preparation method thereof |
| CN115295726A (en) * | 2022-10-08 | 2022-11-04 | 成都宏科电子科技有限公司 | 3D silicon-based capacitor and preparation method thereof |
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