CN101996775B - Method for preparing solid-state ultracapacitor - Google Patents

Method for preparing solid-state ultracapacitor Download PDF

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Publication number
CN101996775B
CN101996775B CN2010105455166A CN201010545516A CN101996775B CN 101996775 B CN101996775 B CN 101996775B CN 2010105455166 A CN2010105455166 A CN 2010105455166A CN 201010545516 A CN201010545516 A CN 201010545516A CN 101996775 B CN101996775 B CN 101996775B
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preparation
metal
layer
array
thermal annealing
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CN101996775A (en
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丁士进
朱宝
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Fudan University
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Fudan University
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13—Energy storage using capacitors

Abstract

The invention belongs to the technical field of capacitor preparation, and particularly discloses a method for preparing a solid-state ultracapacitor. In the method, a high-density and sequential deep notch structure is formed on a high-doping monocrystalline silicon wafer by metal auxiliary etching process, and then the deep notch structure serving as a template is used for preparing the solid-state ultracapacitor. The method comprises the following steps of: forming a quite thin layer of silicon dioxide on the silicon wafer by thermal oxidation; depositing a metal film on the silicon dioxide; carrying out rapid thermal annealing on the metal film to form a metal nanocrystalline array; etching the silicon wafer by taking the metal nanocrystalline array as a catalyst to form a deep notch array; depositing an insulating medium layer on the surface of the deep notch; and then depositing a seed metal layer; and taking an electroplating metal as a positive electrode. Because a high-cost photoetching process is eliminated, the process is simple, the cost is low, the solid-state ultracapacitor prepared by the process is difficult to damage, and the method is applicable for mass production.

Description

A kind of preparation method of solid-state super capacitor
Technical field
The invention belongs to the capacitor preparing technical field, be specifically related to be used for the preparation method of the solid-state super capacitor of power storage.
Background technology
At the electronic device that is used for the energy storage, nanometer super capacitor has obtained paying close attention to widely because have high energy and power density simultaneously.The basic thought of nanometer super capacitor is at first to form the loose structure with large surface area, utilizes this loose structure to form metal/insulator/metal (MIM) type electric capacity as the preparation template then.Based on this thought, the researcher successively adopts anodised aluminium and silicon trench structure to prepare nanometer super capacitor during the last ten years.The principle of anodised aluminium is that highly purified aluminium flake can form high density (10 at alumina surface through anodic oxidation 10Cm -2) loose structure orderly, the hexagon array, and through control of process condition can obtain different-diameter (30～80nm) with the hole of the degree of depth.This anodised aluminium preparation technology prepares to get up more complicated because be a kind of electrochemical process, and repeatability is relatively poor, and template itself is relatively more fragile, and damage easily is so be unfavorable for producing in enormous quantities [1].About the preparation of silicon trench structure, at first adopt photoetching and lithographic technique to form the metal nano array, on silicon chip, form deep-groove array by the metal assisted etch process then, prepare MIM electric capacity with these deep-groove arrays as template at last.The nanostructure deep-groove array that goes out through this prepared has controllability, and silicon materials have good mechanical strength in addition, and is not fragile.Because this method is to form the metal nano array through photoetching technique; Therefore the density of its nano-array is determined by the lithographic equipment characteristic; And common lithography tool is difficult to obtain the high-density metal nano-array, so desire acquisition high desnity metal nano-array, will be faced with high cost investment [2].
List of references:
[1]Parag?Banerjee,?Israel?Perez,?Laurent?Henn-Lecordier,?Sang?Bok?Lee?and?Gary?W.?Rubloff.?Nanotubular?metal–insulator–metal?capacitor?arrays?for?energy?storage[J].Nature?nanotechnology?4(2009).
[2]?Shih-wei?Chang,?Jihun?Oh,?Steven?T.?Boles,?and?Carl?V.?Thompson.?Fabrication?of?silicon?nanopillar-based?nanocapacitor?arrays[J].?Appl.?Phys.?Lett.?96,?153108?(2010)。
Summary of the invention
It is not simple to the objective of the invention is to propose a kind of technology, with low cost, fragile and the method for preparing the nano solid ultracapacitor that can be mass-produced arranged.
The method for preparing the nano solid ultracapacitor that the present invention proposes, be adopt metallic nano crystal as catalyst etching single crystal silicon make nanometer super capacitor, concrete steps are:
(1) thermal oxidation forms the layer of silicon dioxide film on heavily doped monocrystalline silicon piece;
(2) deposit one deck has the metallic film of catalytic action on silica membrane;
(3) metallic film is carried out quick thermal annealing process, form the metallic nano crystal array;
(4) with metallic nano crystal as catalyst, use the mixed solution of hydrofluoric acid and hydrogen peroxide solution that silicon chip is carried out etching, thereby on silicon chip, form deep-groove array;
(5) at surface deposition one deck dielectric of deep trouth, like the high-k zirconia media;
(6) in surface deposition one deck seed metal layer of dielectric;
(7) at the electroplating surface layer of metal of seed metal layer positive electrode as electric capacity.
Among the present invention, described silicon dioxide thickness is 2～6 nanometers.
Among the present invention, described metallic nano crystal can be gold, silver, platinum or palladium.The diameter of this metallic nano crystal is 30～50 nanometers.The controllable density of metallic nano crystal array is built in 10 10～10 11Cm -2
Among the present invention, used corrosive liquid is the mixed solution of hydrofluoric acid (volume fraction 49%) and hydrogen peroxide solution (volume fraction 30%), and the volume ratio scope of 2 kinds of components is 5:1-15:1.
Among the present invention, said ultracapacitor adopts heavily doped silicon as negative electrode.
Among the present invention, said dielectric adopts Al 2O 3, HfO 2, Ta 2O 5Or ZrO 2Its thickness can be 10～20 nanometers.
Among the present invention, said seed metal layer adopts TiN, TaN or W.Its thickness can be 5～10 nanometers.
Among the present invention, said positive electrode adopts Ni or Cu.Its thickness can be 200～500 nanometers.
Among the present invention, said quick thermal annealing process, thermal annealing temperature are 700～800 ℃, and the thermal annealing time is 10-30 second.
The present invention adopts the after annealing of super thin metal layer to handle, and self-organizing forms high desnity metal nano crystal array (10 10～10 11Cm -2).The size of the metallic nano crystal through the preparation of this technology can be controlled in the ideal range of 30～50 nanometers.Therefore, removed expensive photoetching process from.
Description of drawings
Fig. 1: thermal oxidation forms the very thin silicon dioxide of one deck on heavily doped low resistance silicon chip.
Fig. 2: electron beam evaporation or the ultra-thin platinum of sputter one deck on silicon dioxide.
Fig. 3: the platinum nano crystal array that platinum forms behind rapid thermal annealing.
Fig. 4: nanocrystalline with platinum is catalyst, after the etching of the mixed solution of hydrofluoric acid and hydrogen peroxide solution in silicon chip formed deep-groove array.
Fig. 5: at surface atom layer deposit one deck zirconia of deep trouth.
Fig. 6: at zirconic surface magnetic control sputtering one deck titanium nitride.
Fig. 7: in the electroplating surface layer of copper of titanium nitride.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is carried out detailed explanation.
Step 1: please with reference to Fig. 1, put in the thermal oxidation furnace substrate 200 into oxidation 20～60 seconds, form 201 on 200 surfaces, wherein 200 is heavily doped low resistance silicon chip; The 201st, silicon dioxide, thickness are 2～6 nanometers.
Step 2: please with reference to Fig. 2, at 201 surface sputtering one decks 202, wherein 202 is metal platinum, and thickness is 3～5 nanometers.
Step 3: please with reference to Fig. 3, form 203 second to 202 at 700～800 ℃ of rapid thermal annealing 10-30, wherein 203 is that platinum is nanocrystalline, and diameter is 30～50 nanometers.
Step 4:,, use the mixed solution of hydrofluoric acid and hydrogen peroxide solution to carry out etching, thereby on 200, form deep-groove array to 200 and 201 with 203 as catalyst please with reference to Fig. 4.The volume ratio scope of 2 kinds of components is 5:1-15:1 in the mixed solution.
Step 5: please with reference to Fig. 5, at surface atom layer deposit one deck 204 of 200 deep trouths, wherein 204 is zirconias, and thickness is 10～20 nanometers.
Step 6: please with reference to Fig. 6, at surface reaction magnetron sputtering one deck 205 of 204, wherein 205 is titanium nitrides, and thickness is 5～10 nanometers.204 and 205 thickness sum should be no more than the diameter of 200 deep trouths.
Step 7: please with reference to Fig. 7, the electroplating surface one deck 206 205, wherein 206 is copper, thickness is 200～500 nanometers.
The nanometer super capacitor preparation technology that the present invention proposes is not simple, with low cost, and is fragile and might produce in enormous quantities.

Claims (7)

1. the preparation method of a solid-state super capacitor is characterized in that, concrete steps are:
(1) thermal oxidation forms the layer of silicon dioxide film on heavily doped monocrystalline silicon piece;
(2) deposit one deck has the metal level of catalytic action on silica membrane;
(3) metal level is carried out quick thermal annealing process, form the metallic nano crystal array;
(4) with metallic nano crystal as catalyst, use the mixed solution of hydrofluoric acid and hydrogen peroxide solution that silicon chip is carried out etching, on silicon chip, form deep-groove array;
(5) at surface deposition one insulating medium layer of deep trouth;
(6) in surface deposition one deck seed metal layer of insulating medium layer;
(7) at the electroplating surface layer of metal of seed metal layer positive electrode as electric capacity.
Wherein, said metallic nano crystal is gold, silver, platinum or palladium.
2. preparation method according to claim 1 is characterized in that said insulating medium layer adopts Al 2O 3, HfO 2, Ta 2O 5Or ZrO 2
3. preparation method according to claim 1 is characterized in that said seed metal layer adopts TiN, TaN or W.
4. preparation method according to claim 1, the diameter that it is characterized in that said metallic nano crystal is 30～50 nanometers.
5. preparation method according to claim 2 is characterized in that said dielectric layer thickness is 10～20 nanometers.
6. preparation method according to claim 3 is characterized in that said seed metal layer thickness is 5～10 nanometers.
7. preparation method according to claim 1 is characterized in that said quick thermal annealing process, and the thermal annealing temperature is 700～800 ℃, and the thermal annealing time is 10-30 second.
CN2010105455166A 2010-11-16 2010-11-16 Method for preparing solid-state ultracapacitor Expired - Fee Related CN101996775B (en)

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WO2013048465A1 (en) * 2011-09-30 2013-04-04 Intel Corporation Method of increasing an energy density and an achievable power output of an energy storage device
US9093226B2 (en) * 2012-09-17 2015-07-28 Intel Corporation Energy storage device, method of manufacturing same, and mobile electronic device containing same
CN105225835B (en) * 2014-07-04 2018-06-22 上海金沛电子有限公司 A kind of preparation method of crystal silicon chip capacitor
CN108538821B (en) * 2018-05-14 2021-03-23 复旦大学 All-solid-state super capacitor integrated with silicon-based integrated circuit and preparation method thereof
CN108793065B (en) * 2018-06-25 2020-09-15 太原理工大学 Preparation method of MEMS (micro-electromechanical systems) supercapacitor with controllable dielectric film thickness
CN110092346B (en) * 2019-04-17 2022-06-07 西安交通大学 Silicon-based MEMS super capacitor and preparation method thereof

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