CN102074378A

CN102074378A - Preparation method for solid state super capacitor

Info

Publication number: CN102074378A
Application number: CN2011100495068A
Authority: CN
Inventors: 丁士进; 朱宝
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2011-03-02
Filing date: 2011-03-02
Publication date: 2011-05-25

Abstract

The invention relates to the technical field of solid state capacitors, in particular to a preparation method for a solid state super capacitor. The preparation method comprises the following steps of: firstly, preparing a high density metal silver nanometer crystal array by a chemical plating method; secondly, forming a quiet ordered deep groove structure with high density and high depth width ratio on a heavily doped low resistance silicon slice by taking the silver nanometer crystal as a catalyst through a metal assistant etching process; and finally, sequentially preparing an insulation medium layer, a seed metal layer and an upper electrode on the surface of the quirk by taking the quirk structure as a template to obtain the solid state super capacitor. The preparation method is simple in process and low in cost. The prepared super capacitor is not easy to be damaged and can be produced on a large scale.

Description

A kind of preparation method of solid-state super electric capacity

Technical field

The invention belongs to the solid capacitor technical field, be specifically related to a kind of preparation method of solid-state super electric capacity.

Background technology

At the electronic device that is used for the energy storage, solid-state super electric capacity has obtained concern widely owing to have high energy and power density simultaneously.The basic thought of solid-state super electric capacity is at first to form the loose structure with large surface area, utilizes this loose structure to form metal/insulator/metal (MIM) type electric capacity as the preparation template then.Based on this thought, the researcher successively adopts anodised aluminium and silicon trench structure to prepare nanometer super capacitor during the last ten years.The principle of anodised aluminium is that highly purified aluminium flake can form high density (10 at alumina surface through anodic oxidation ¹⁰Cm ^-2) loose structure orderly, the hexagon array, and can obtain different-diameter (30～80nm) and the hole of the degree of depth by control of process condition.This anodised aluminium preparation technology prepares to get up more complicated because be a kind of electrochemical process, and repeatability is relatively poor, and template itself is relatively more fragile, and damage easily is so be unfavorable for producing in enormous quantities [1].And have good mechanical strength based on the deep groove structure of silicon, not fragile.Usually, can adopt photoetching and lithographic technique directly on monocrystalline silicon piece, to form deep-groove array, perhaps at first on silicon chip, form the metal nano array, on silicon chip, form deep-groove array by the metal assisted etch process then, prepare MIM electric capacity with these deep-groove arrays as template at last.Though the nanostructure deep-groove array that goes out by above-mentioned prepared has controllability, the metal nano array that forms by photoetching method is subject to mask aligner equipment, be difficult to obtain the high-density metal nano-array, and cost height [2].

List of references:

[1]P.?Banerjee,?I.?Perez,?L.?Henn-Lecordier,?S.?B.?Lee?and?G.?W.?Rubloff.?Nanotubular?metal–insulator–metal?capacitor?arrays?for?energy?storage[J].Nature?Nanotechnology?4(2009).

[2]?S.-W.?Chang,?J.?Oh,?S.?T.?Boles,?and?C.?V.?Thompson.?Fabrication?of?silicon?nanopillar-based?nanocapacitor?arrays[J].?Appl.?Phys.?Lett.?96,?153108?(2010).。

Summary of the invention

The object of the present invention is to provide a kind of technology simple, with low cost, the method for the not fragile and making solid-state super electric capacity that can produce in enormous quantities.

The method of making solid-state super electric capacity provided by the invention, its step is as follows:

At first, with chemical deposit prepared silver nano crystal array, specifically be that heavily doped low resistance silicon chip is dipped in the mixed solution of hydrofluoric acid and silver nitrate, make silver ion form silver-colored simple substance and silica by silicon atom exchange electronics, the silica of Xing Chenging is eroded by hydrofluoric acid simultaneously, and silver-colored subsequently simple substance forms separate silver-colored nanocrystalline by self assembly on silicon chip;

Then, be catalyst with this silver nano crystal array, in the mixed solution of hydrofluoric acid and hydrogen peroxide, heavily doped low resistance silicon chip is carried out the metal auxiliary etch, form density height, depth-to-width ratio greatly and very orderly deep-groove array structure;

At last, as template, prepare insulating medium layer, seed metal layer and top electrode successively, be prepared into solid-state super electric capacity on the deep trouth surface with this deep groove structure.

Among the present invention, the material of described insulating medium layer can be Al ₂O ₃, HfO ₂, Ta ₂O ₅Or ZrO ₂Deng.The preparation method is the atomic layer deposition method.

Among the present invention, the material of the described seed metal layer on the insulating medium layer can be TiN, TaN or W etc.The preparation method can be magnetically controlled sputter method.

Among the present invention, the upper electrode material of seed metal laminar surface is Ni or Cu, and the preparation method can be for electroplating.

The present invention adopts chemical deposit technology, and (density is 10 to prepare high desnity metal silver nano crystal array on silicon substrate ¹⁰～10 ¹¹Cm ^-2), the nanocrystalline size of argent can be controlled in the ideal range of 30～60 nanometers.Avoided expensive photoetching process.

Description of drawings

Fig. 1: heavily doped low resistance silicon chip is dipped in hydrofluoric acid and the silver nitrate mixed solution carries out chemical plating, make silver-colored nano crystal array.

Fig. 2: nanocrystalline with silver is catalyst, and etching in the mixed solution of hydrofluoric acid and hydrogen peroxide forms deep-groove array in silicon chip.

Fig. 3: at the surface atom layer deposit insulating medium layer (as zirconia) of deep trouth.

Fig. 4: in the surface magnetic control sputtering seed metal layer (as titanium nitride) of insulating medium layer.

Fig. 5: at the electroplating surface top electrode (as copper) of seed metal layer.

Embodiment

Below in conjunction with the drawings and specific embodiments the present invention is carried out detailed explanation.

Step 1: please refer to Fig. 1, substrate 200 is dipped into chemical plating forms 201 in the mixed solution of hydrofluoric acid and silver nitrate, wherein 200 is heavily doped low resistance silicon chip; The 201st, silver, diameter is 30～60 nanometers.

Step 2: please refer to Fig. 2, nanocrystalline with silver as catalyst, use the mixed solution of hydrofluoric acid and hydrogen peroxide to carry out etching, thereby on 200, form deep-groove array 200.

Step 3: please refer to Fig. 3, at surface atom layer deposit one deck 202 of 200 deep trouths, insulating medium layer.Wherein 202 is zirconias, and thickness is 10～15 nanometers.

Step 4: please refer to Fig. 4, the surface reaction magnetron sputtering one deck 203 202 is as seed metal layer.Wherein 203 is titanium nitrides, and thickness is 5～10 nanometers.202 and 203 thickness sum should be no more than the diameter of 200 deep trouths.

Step 5: please refer to Fig. 5, the electroplating surface one deck 204 203 is as top electrode.Wherein 204 is copper, and thickness is 200～500 nanometers.

The solid-state super capacitor fabrication method that the present invention proposes, technology is simple, and is not with low cost, fragile and might produce in enormous quantities.

Claims

1. the preparation method of a solid-state super electric capacity is characterized in that concrete steps are:

At first, with chemical deposit prepared silver nano crystal array, specifically be that heavily doped low resistance silicon chip is dipped in the mixed solution of hydrofluoric acid and silver nitrate, make silver ion and silicon atom exchange electronics form silver-colored simple substance and silica, the silica of Xing Chenging is eroded by hydrofluoric acid simultaneously, and silver-colored subsequently simple substance forms separate silver-colored nanocrystalline by self assembly on silicon chip;

Then, nanocrystalline with this silver is catalyst, in the mixed solution of hydrofluoric acid and hydrogen peroxide heavily doped low resistance silicon chip is carried out the metal auxiliary etch, forms density height, the big and orderly deep-groove array structure of depth-to-width ratio;

At last, as template, prepare insulating medium layer, seed metal layer and top electrode successively, be prepared into solid-state super electric capacity on the deep trouth surface with this deep-groove array structure.

2. the preparation method of solid-state super electric capacity according to claim 1, the material that it is characterized in that described insulating medium layer is Al ₂O ₃, HfO ₂, Ta ₂O ₅Or ZrO ₂The preparation method is the atomic layer deposition method.

3. the preparation method of solid-state super electric capacity according to claim 1 and 2, the material that it is characterized in that the described seed metal layer on the described insulating medium layer is TiN, TaN or W; The preparation method is a magnetron sputtering method.

4. the preparation method of solid-state super electric capacity according to claim 1 and 2, the material that it is characterized in that the top electrode of described seed metal laminar surface is Ni or Cu, the preparation method is for electroplating.

5. the preparation method of solid-state super electric capacity according to claim 1 is characterized in that the density of the silver-colored nano crystal array for preparing on the described silicon substrate is (10 ¹⁰～10 ¹¹) cm ^-2, silver-colored nanocrystalline size Control is in 30 nanometers～60 nanometers.