CN106598901A - System and chip for converting Local Bus into USB based on FPGA - Google Patents
System and chip for converting Local Bus into USB based on FPGA Download PDFInfo
- Publication number
- CN106598901A CN106598901A CN201611123546.1A CN201611123546A CN106598901A CN 106598901 A CN106598901 A CN 106598901A CN 201611123546 A CN201611123546 A CN 201611123546A CN 106598901 A CN106598901 A CN 106598901A
- Authority
- CN
- China
- Prior art keywords
- fpga
- usb
- data
- module
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
- Bus Control (AREA)
Abstract
The invention provides a system for converting Local Bus into USB based on FPGA. The system comprises an FPGA module used for performing data transmission with an FPGA chip through a Local Bus protocol; a processing module used for performing data transmission with the FPGA module through a custom data transmission protocol; and a USB communication module used for connecting the processing module and a USB communication device to perform data transmission through a USB protocol. The system is provided with the FPGA module to perform the data transmission with the FPGA chip through the Local Bus protocol, the transmitted data are transmitted to the USB communication device through the USB communication module via the USB protocol, the conversion of a Local Bus signal and a USB signal is realized in a convenient and fast manner, and the safety and the stability are high. The invention further provides a chip applying the system.
Description
Technical field
The present invention relates to signal conversion art, more particularly to a kind of Local Bus based on FPGA turn the system and core of USB
Piece.
Background technology
With the development of science and technology, computer application is more and more extensive.Wherein, because FPGA is the important portion of computer
Part, the attention rate more and more higher to FPGA researchs.It is by signal FPGA itself based on an important technology of the research of FPGA
Signal transmission form be converted to usb signal mode, with realize with external equipment carry out high-speed communication.
At present using it is more be that the PCIE signal of FPGA is converted to by usb signal by asic chip, but on condition that
FPGA has PCIE EBIs.And when FPGA does not have PCIE EBIs, need just to be completed by complicated design
The conversion of signal.
The content of the invention
For drawbacks described above, the present invention is necessary to provide system and core that a kind of Local BUS based on FPGA turn USB
Piece, the simple and convenient conversion for realizing signal is safe, and motility is high, using less-restrictive.
A kind of Local Bus based on FPGA turn USB system, including：
FPGA module, for being carried out data transmission by Local Bus agreements with fpga chip；
Processing module, for being carried out data transmission by self-defining data host-host protocol with the FPGA module；And,
Usb communication module, is carried out data transmission with USB communication device for connecting processing module by usb protocol.
Preferably, processing module includes：
Query unit, for inquiring about FPGA data flag bit and usb data complement mark position；
Processing unit, for when FPGA data flag bit is inquired, calling self-defining data host-host protocol to read FPGA
The data of module are cached, then are sent to USB communication device by usb communication module, and remove FPGA data flag bit；With
And, when usb data complement mark position is inquired, self-defining data host-host protocol is called by the number of the usb communication module for caching
According to FPGA module is sent to, fpga chip is resent to, and removes usb data complement mark position；And,
Buffer unit, for caching the data of FPGA module and the data of usb communication module.
Preferably, processing module also includes interrupt location, and interrupt location includes：
Interrupt generating subunit, for there are data that interruption is produced when transmitting when FPGA module；When usb communication module has number
Interrupt according to producing when transmitting；
Judgment sub-unit, for judging interrupt source；And,
Subelement on mark position, for when being judged as that FPGA module has data whne the interruption that transmission is produced, putting
FPGA data flag bit；When being judged as that usb communication module has data whne the interruption that transmission is produced, buffer unit receives USB and leads to
The data of letter module, put usb data complement mark position.
Preferably, interrupt location also includes searching subelement, for searching whether FPGA module and communication module have data
Wait to transmit.
Preferably, interrupt generating subunit to be additionally operable to produce interruption when USB communication device is connected to usb communication module；
Processing module also includes dispensing unit, when judgment sub-unit is judged as that USB communication device is connected in the generation of usb communication module
When disconnected, configuration of described dispensing unit USB communication device.
Preferably, configuration of described dispensing unit USB communication device is including reset usb bus and carries out USB device enumeration process, with
Identification USB communication device and the corresponding driver of installation.
Preferably, the processing module also includes order performance element, and buffer unit is stored in by FPGA module for replicating
Data, and be sent to usb communication module；And/or, the data that reception is transmitted by usb communication module are simultaneously stored in buffer unit.
Preferably, the FPGA module can also be carried out data transmission with other types chip by Local Bus agreements.
A kind of chip, chip includes turning USB system, FPGA based on the Local Bus of FPGA described in as above any one
Outward on chip, FPGA is carried out data transmission with the fpga chip or other chips of outside by Local Bus agreements, chip
Processor carried out data transmission by self-defining data host-host protocol with FPGA, then by USB device interface and PERCOM peripheral communication
Equipment is transmitted.
Preferably, chip includes：
Bottom storehouse, for system hardware platform is provided；
Hardware abstraction layer, is connected, there is provided standard interface with bottom storehouse, and hardware abstraction layer includes GPIO interface；
Flaggy, by calling hardware abstraction layer, there is provided general standard functions component, realizes that functional module drives and connects
Mouthful, simple clearly unified call interface is provided for upper strata, flaggy includes USB module and FPGA module；And, application layer is led to
Cross the interface for calling flaggy, there is provided based on the application program that flaggy is developed, realize conversion of the chip to Local Bus and USB.
Preferably, model CME-M7 of chip；And/or, model Cortex-M3 of chip processor.
The present invention turns USB system based on the Local Bus of FPGA, arrange FPGA module by Local Bus agreements with
Fpga chip carries out data transmission, and the data of transmission are entered again by usb communication module and USB communication device by usb protocol
Row transmission, realizes the conversion of Local Bus signals and usb signal, convenient and swift, and safety and stability are high.
Description of the drawings
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, below will be to needed for embodiment of the present invention description
The accompanying drawing to be used is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention,
For those of ordinary skill in the art, without having to pay creative labor, can be being obtained according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is that a kind of Local Bus based on FPGA that first embodiment of the invention is provided turn USB system in application state
Structure chart；
Fig. 2 is that the another kind that second embodiment of the invention is provided turns USB system in applying shape based on the Local Bus of FPGA
The structure chart of state；
Fig. 3 is that the another kind that third embodiment of the invention is provided is turned in USB system based on the Local Bus of FPGA, is processed
The structure chart of module；
Fig. 4 is the structure chart of the interrupt location in Fig. 3；
Fig. 5 is that the another kind that Fig. 3 fourth embodiments are provided is turned in USB system based on the Local Bus of FPGA, interrupt location
Structure chart；
Fig. 6 is that the another kind that fifth embodiment of the invention is provided is turned in USB system based on the Local Bus of FPGA, is processed
The structure chart of module；
Fig. 7 is that the another kind that sixth embodiment of the invention is provided turns USB system in applying shape based on the Local Bus of FPGA
The structure chart of state；
Fig. 8 is a kind of structure chart of chip that seventh embodiment of the invention is provided；
Fig. 9 is the Organization Chart of another kind of chip that eighth embodiment of the invention is provided.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is a part of embodiment of the invention, rather than the embodiment of whole.Based on this
Embodiment in bright, the every other enforcement that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example, belongs to the scope of protection of the invention.
Fig. 1 is refer to, the first embodiment of the present invention provides a kind of Local Bus based on FPGA and turns USB system 100,
Including：
FPGA module 10, for being carried out data transmission by Local Bus agreements with fpga chip 200；
Processing module 20, for being carried out data transmission by self-defining data host-host protocol with the FPGA module 10；With
And,
Usb communication module 30, data biography is carried out for connecting processing module 20 with USB communication device 300 by usb protocol
It is defeated.
In other embodiments, the FPGA module 10 can also be entered with other types chip by Local Bus agreements
Row data transfer.
A kind of Local Bus based on FPGA of the present embodiment turn USB system 100, arrange FPGA module 10 and pass through Local
Bus agreements carry out data transmission with fpga chip 200, by the data of transmission again by usb communication module 30 and USB communication device
300 are transmitted by usb protocol, realize the conversion of Local Bus signals and usb signal, convenient and swift, safety and steady
Qualitative height.
Fig. 2 is refer to, further, based on the second embodiment of first embodiment of the invention, processing module 20 includes：
Query unit 21, for inquiring about FPGA data flag bit and usb data complement mark position；
Processing unit 22, for when FPGA data flag bit is inquired, calling self-defining data host-host protocol to read
The data of FPGA module 10 are cached, then are sent to USB communication device 300 by usb communication module 30, and remove FPGA numbers
According to flag bit；And, when usb data complement mark position is inquired, call self-defining data host-host protocol to lead to the USB of caching
The data of letter module 30 are sent to FPGA module 10, are resent to fpga chip 200, and remove usb data complement mark position；With
And,
Buffer unit 23, for caching the data of FPGA module 10 and the data of usb communication module 30.
The present embodiment inquired about by query unit 21 whether have data by FPGA module 10 be sent to usb communication module 30 or
Person is sent to FPGA module 10 by usb communication module 30, and processing unit 22 accordingly calls self-defining data host-host protocol to carry out
Data are transmitted, and transfer is carried out to data by buffer unit 23, be furthermore achieved that rapid translating transmission signal and are carried out data
Transmission.
Fig. 3 and Fig. 4 is refer to, further, based on the 3rd embodiment of second embodiment of the invention, processing module is also wrapped
Interrupt location 24 is included, interrupt location 24 includes：
Interrupt generating subunit 241, for there are data that interruption is produced when transmitting when FPGA module 10；When usb communication mould
Block 30 has data that interruption is produced when transmitting；
Judgment sub-unit 242, for judging interrupt source；And,
Subelement 243 on mark position, for when being judged as that FPGA module 10 has data whne the interruption that transmission is produced, putting
Upper FPGA data flag bit；When being judged as that usb communication module 30 has data whne the interruption that transmission is produced, buffer unit 23 is received
The data of usb communication module 30, put usb data complement mark position.
The interrupt location 24 of the present embodiment, in FPGA module 10 and usb communication module 30 have data to produce when transmitting
Disconnected, accordingly to put upper flag bit, there is provided carry out flag bit inquiry to query unit 21, accuracy and stability are high.
Fig. 5 is refer to, further, based on the fourth embodiment of third embodiment of the invention, interrupt location 24 also includes
Subelement 244 is searched, for searching whether FPGA module 10 and usb communication module 30 there are data to wait to transmit.
The present embodiment searches subelement 244 by arranging in interrupt location 24, quick to confirm to need to produce the opportunity interrupted,
Improve the accuracy of system.
Fig. 6 is refer to, further, based on the 5th embodiment of third embodiment of the invention, interrupts generating subunit 241
It is additionally operable to produce interruption when USB communication device 300 is connected to usb communication module 30；Processing module 20 also includes dispensing unit
25, when judgment sub-unit 242 is judged as that USB communication device 300 is connected to the interruption of the generation of usb communication module 30, configuration is single
Unit 25 configures USB communication device 300.
Wherein, the configuration of dispensing unit 25 USB communication device 300 includes reset usb bus and carries out USB device enumeration mistake
Journey, to recognize USB communication device 300 and install corresponding driver.
The present embodiment passes through to judge the interruption that USN communication equipments 300 connect, and dispensing unit 25 carries out device configuration,
Improve safety.
Fig. 7 is refer to, further, based on the sixth embodiment of second embodiment, the processing module 20 also includes suitable
Sequence performance element 26, the data of buffer unit 23 are stored in for replicating by FPGA module 10, and are sent to usb communication module 30；
And/or, the data that reception is transmitted by usb communication module 30 are simultaneously stored in buffer unit 23.
The present embodiment is carried out data transmission by order performance element with usb communication module 30, further increases transmission
Stability.
Fig. 8 is refer to, further, a kind of the 7th embodiment based on above-mentioned any one embodiment, there is provided chip,
Outside FPGA on chip, FPGA is carried out data transmission with the fpga chip or other chips of outside by Local Bus agreements,
The processor of chip is carried out data transmission with FPGA by self-defining data host-host protocol, then by USB device interface and outside
Communication equipment is transmitted.
Wherein, model CME-M7 of chip；And/or, model Cortex-M3 of chip processor.
The present embodiment arranges FPGA to be carried out data transmission by Local Bus agreements with fpga chip or external chip, is located
Reason device is carried out data transmission with FPGA by custom protocol, then is transmitted with external communication device by USB interface, is realized
The conversion of Local Bus signals and usb signal, it is convenient and swift, safety and stability it is high.
Fig. 9 is refer to, further, based on the 8th embodiment of the 7th embodiment, chip includes：
Bottom storehouse, for system hardware platform is provided；
Hardware abstraction layer, is connected, there is provided standard interface with bottom storehouse, and hardware abstraction layer includes GPIO interface；
Flaggy, by calling hardware abstraction layer, there is provided general standard functions component, realizes that functional module drives and connects
Mouthful, simple clearly unified call interface is provided for upper strata, USB module and FPGA module are located at flaggy；And,
Application layer, by the interface for calling flaggy, there is provided based on the application program that flaggy is developed, realize chip to Local
The conversion of Bus and USB.
The software of the present embodiment is processed using layering, convenient subsequently to change or extend, and also strengthens program entirety
Readability and module portability.
Those of ordinary skill in the art are it is to be appreciated that the list of each example with reference to the embodiments described herein description
Unit and algorithm steps, being capable of being implemented in combination in electronic hardware or computer software and electronic hardware.These functions are actually
Performed with hardware or software mode, depending on the application-specific and design constraint of technical scheme.Professional and technical personnel
Each specific application can be used different methods to realize described function, but this realization it is not considered that exceeding
The scope of the present invention.
Those skilled in the art can be understood that, for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, may be referred to the corresponding process in preceding method embodiment, will not be described here.
In embodiment provided herein, it should be understood that disclosed apparatus and method, can pass through other
Mode is realized.For example, device embodiment described above is only schematic, and for example, the division of the unit is only
A kind of division of logic function, can there is an other dividing mode when actually realizing, such as multiple units or component can with reference to or
Person is desirably integrated into another system, or some features can be ignored, or does not perform.Another, shown or discussed is mutual
Between coupling or direct-coupling or communication connection can be INDIRECT COUPLING or communication link by some interfaces, device or unit
Connect, can be electrical, mechanical or other forms.
The unit as separating component explanation can be or may not be it is physically separate, it is aobvious as unit
The part for showing can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple
On NE.Some or all of unit therein can be according to the actual needs selected to realize embodiment of the present invention scheme
Purpose.
In addition, each functional unit in each embodiment of the invention can be integrated in a processing unit, it is also possible to
It is that unit is individually physically present, it is also possible to which two or more units are integrated in a unit.
If the function is realized and as independent production marketing or when using using in the form of SFU software functional unit, can be with
In being stored in a computer read/write memory medium.Based on such understanding, technical scheme is substantially in other words
The part contributed to prior art or the part of the technical scheme can be embodied in the form of software product, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be individual
People's computer, server, or network equipment etc.) perform all or part of step of each embodiment methods described of the invention.
And aforesaid storage medium includes：USB flash disk, portable hard drive, ROM, RAM, magnetic disc or CD etc. are various can be with store program codes
Medium.
The above, the only specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, all should contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by scope of the claims.
Claims (11)
1. a kind of Local Bus based on FPGA turn USB system, it is characterised in that include：
FPGA module, for being carried out data transmission by Local Bus agreements with fpga chip；
Processing module, for being carried out data transmission by self-defining data host-host protocol with the FPGA module；And,
Usb communication module, is carried out data transmission with USB communication device for connecting processing module by usb protocol.
2. the Local Bus based on FPGA as claimed in claim 1 turn USB system, it is characterised in that processing module includes：
Query unit, for inquiring about FPGA data flag bit and usb data complement mark position；
Processing unit, for when FPGA data flag bit is inquired, calling self-defining data host-host protocol to read FPGA module
Data cached, then USB communication device is sent to by usb communication module, and remove FPGA data flag bit；And,
When usb data complement mark position is inquired, self-defining data host-host protocol is called to pass the data of the usb communication module for caching
FPGA module is delivered to, fpga chip is resent to, and removes usb data complement mark position；And,
Buffer unit, for caching the data of FPGA module and the data of usb communication module.
3. the Local Bus based on FPGA as claimed in claim 2 turn USB system, it is characterised in that processing module also includes
Interrupt location, interrupt location includes：
Interrupt generating subunit, for there are data that interruption is produced when transmitting when FPGA module；When usb communication module has data to treat
Interruption is produced during transmission；
Judgment sub-unit, for judging interrupt source；And,
Subelement on mark position, for when being judged as that FPGA module has data whne the interruption that transmission is produced, putting FPGA numbers
According to flag bit；When being judged as that usb communication module has data whne the interruption that transmission is produced, buffer unit receives usb communication module
Data, put usb data complement mark position.
4. the Local Bus based on FPGA as claimed in claim 3 turn USB system, it is characterised in that interrupt location also includes
Subelement is searched, for searching whether FPGA module and communication module there are data to wait to transmit.
5. the Local Bus based on FPGA as claimed in claim 3 turn USB system, it is characterised in that interrupt generating subunit
It is additionally operable to produce interruption when USB communication device is connected to usb communication module；Processing module also includes dispensing unit, works as judgement
When subelement is judged as that USB communication device is connected to the interruption of usb communication module generation, configuration of described dispensing unit USB communication device.
6. the Local Bus based on FPGA as claimed in claim 5 turn USB system, it is characterised in that configuration of described dispensing unit
USB communication device includes reset usb bus and carries out USB device enumeration process, to recognize USB communication device and install corresponding
Driver.
7. the Local Bus based on FPGA as claimed in claim 2 turn USB system, it is characterised in that the processing module is also
Including order performance element, the data of buffer unit are stored in by FPGA module for replicating, and are sent to usb communication module；And/
Or, receiving the data transmitted by usb communication module and being stored in buffer unit.
8. the Local Bus based on FPGA as claimed in claim 1 turn USB system, it is characterised in that the FPGA module is also
Can be carried out data transmission by Local Bus agreements with other types chip.
9. a kind of chip, it is characterised in that chip includes the Local based on FPGA as described in claim 1-8 any one
Bus turns USB system, and outside FPGA on chip, FPGA passes through Local Bus agreements with the fpga chip or other chips of outside
Carry out data transmission, processor and the FPGA of chip are carried out data transmission by self-defining data host-host protocol, then are set by USB
Standby interface is transmitted with external communication device.
10. chip as claimed in claim 9, it is characterised in that chip includes：
Bottom storehouse, for system hardware platform is provided；
Hardware abstraction layer, is connected, there is provided standard interface with bottom storehouse, and hardware abstraction layer includes GPIO interface；
Flaggy, by calling hardware abstraction layer, there is provided general standard functions component, realizes functional module driving interface, is
Upper strata provides simple clearly unified call interface, and flaggy includes USB module and FPGA module；And,
Application layer, by the interface for calling flaggy, there is provided based on the application program that flaggy is developed, realize chip to Local Bus
With the conversion of USB.
11. chips as claimed in claim 9, it is characterised in that model CME-M7 of chip；And/or, chip processor
Model Cortex-M3.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611123546.1A CN106598901A (en) | 2016-12-08 | 2016-12-08 | System and chip for converting Local Bus into USB based on FPGA |
| PCT/CN2016/109450 WO2018103113A1 (en) | 2016-12-08 | 2016-12-12 | Fpga-based system for converting local bus into usb, and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611123546.1A CN106598901A (en) | 2016-12-08 | 2016-12-08 | System and chip for converting Local Bus into USB based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106598901A true CN106598901A (en) | 2017-04-26 |
Family
ID=58597598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611123546.1A Pending CN106598901A (en) | 2016-12-08 | 2016-12-08 | System and chip for converting Local Bus into USB based on FPGA |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106598901A (en) |
| WO (1) | WO2018103113A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114979813B (en) * | 2022-06-22 | 2023-10-20 | 扬州万方科技股份有限公司 | VPX equipment communication forwarding board and communication method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201111021Y (en) * | 2007-02-12 | 2008-09-03 | 深圳创维－Rgb电子有限公司 | Equipment interconnection equipment based on USB interface |
| US20090063747A1 (en) * | 2007-08-28 | 2009-03-05 | Rohati Systems, Inc. | Application network appliances with inter-module communications using a universal serial bus |
| CN101655825A (en) * | 2008-08-19 | 2010-02-24 | 研祥智能科技股份有限公司 | Device for achieving LPC-USB two-way communication by using FPGA and data conversion method of LPC-US and USB-LPC |
| CN104698314A (en) * | 2015-03-05 | 2015-06-10 | 中国空间技术研究院 | Device-level automatic testing platform and testing method for SRAM type FPGA |
| CN106155960A (en) * | 2016-06-29 | 2016-11-23 | 广州慧睿思通信息科技有限公司 | Shake hands and the UART serial port communication method of EDMA based on GPIO |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7222201B2 (en) * | 2003-01-06 | 2007-05-22 | Plx Technology, Inc. | Virtual endpoint for USB devices |
| CN202735907U (en) * | 2012-08-01 | 2013-02-13 | 成都爱斯顿科技有限公司 | Embedded computer circuit board based on microprocessor |
| CN104794088B (en) * | 2015-04-22 | 2018-05-01 | 成都为开微电子有限公司 | A kind of multiplex roles general line system extended chip design |
-
2016
- 2016-12-08 CN CN201611123546.1A patent/CN106598901A/en active Pending
- 2016-12-12 WO PCT/CN2016/109450 patent/WO2018103113A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201111021Y (en) * | 2007-02-12 | 2008-09-03 | 深圳创维－Rgb电子有限公司 | Equipment interconnection equipment based on USB interface |
| US20090063747A1 (en) * | 2007-08-28 | 2009-03-05 | Rohati Systems, Inc. | Application network appliances with inter-module communications using a universal serial bus |
| CN101655825A (en) * | 2008-08-19 | 2010-02-24 | 研祥智能科技股份有限公司 | Device for achieving LPC-USB two-way communication by using FPGA and data conversion method of LPC-US and USB-LPC |
| CN104698314A (en) * | 2015-03-05 | 2015-06-10 | 中国空间技术研究院 | Device-level automatic testing platform and testing method for SRAM type FPGA |
| CN106155960A (en) * | 2016-06-29 | 2016-11-23 | 广州慧睿思通信息科技有限公司 | Shake hands and the UART serial port communication method of EDMA based on GPIO |
Non-Patent Citations (5)
| Title |
|---|
| 刘利强等: "《嵌入式软件技术》", 31 August 2009, 哈尔滨工程大学出版社 * |
| 宣林: ""基于Intel Xscale处理器嵌入式系统的USB数据通信实现和优化"", 《中国优秀博硕士学位论文全文数据库(硕士) 信息科技辑》 * |
| 李岩: ""多通道皮肤听声器质量检测系统的研究"", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 牛跃听等: "《CAN总线嵌入式开发——从入门到实战（第2版）》", 30 April 2016, 北京航空航天大学出版社 * |
| 顾卫钢: "《手把手教你学DSP——基于TMS320X281x》", 30 April 2011, 北京航空航天大学出版社 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018103113A1 (en) | 2018-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10468078B2 (en) | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communication | |
| CN102866971B (en) | Device, the system and method for transmission data | |
| EP3158698B1 (en) | Systems and methods for providing power savings and interference mitigation on physical transmission media | |
| CN107145430A (en) | A kind of method for realizing NVMe SSD lightings by CPLD based on I2C interfaces | |
| CN103827841B (en) | The I/O connector of configurable bandwidth | |
| CN102638397A (en) | USB (universal serial bus) device communication transmission method, device and system | |
| CN104536746A (en) | Software structure based on DLL | |
| CN106598889A (en) | SATA (Serial Advanced Technology Attachment) master controller based on FPGA (Field Programmable Gate Array) sandwich plate | |
| CN102103562A (en) | Multi-power mode serial interface architecture | |
| CN106445853A (en) | Transformation method of SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver/Transmitter) interface on the basis of FPGA (Field Programmable Gate Array) | |
| CN105786736A (en) | Method, chip and device for multi-chip cascading | |
| CN103972909A (en) | TSC (thyristor switched capacitor) system and RS485 communication method thereof based on FPGA (Field Programmable Gate Array) | |
| CN106598901A (en) | System and chip for converting Local Bus into USB based on FPGA | |
| CN107992439A (en) | A kind of expansible data interactive method and system | |
| CN103106113A (en) | Interrupt event processing method and processing equipment | |
| CN105718410B (en) | A kind of LPC based on FPGA and SPI and I2C conversion adapters and its implementation | |
| CN108132898A (en) | Multiplex communication control method and communication box | |
| CN101047447B (en) | Point-to-point industrial series real-time communication system based on optical fibre and its control method | |
| CN106126446A (en) | A kind of USB device and the method identifying MacOS system thereof | |
| CN105872060A (en) | Communication method and system, and data collection end device | |
| CN105045740A (en) | Conversion method and circuit for communication interfaces | |
| CN112118166A (en) | Multi-chip networking system, method and application | |
| CN102594871A (en) | Data packaging method and system, adapter and Internet of things middleware | |
| CN106855846A (en) | A kind of PCIE signal extension system and method based on PCIE Switch | |
| CN107220154A (en) | The system for managing multiple address identical two-wire serial interface optical modules |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170426 |
|
| RJ01 | Rejection of invention patent application after publication |