CN106597761B

CN106597761B - Display panel and electronic device

Info

Publication number: CN106597761B
Application number: CN201510660438.7A
Authority: CN
Inventors: 崔博钦; 朱夏青; 孙铭谦; 刘桂伶
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2015-10-14
Filing date: 2015-10-14
Publication date: 2020-01-14
Anticipated expiration: 2035-10-14
Also published as: CN106597761A

Abstract

The invention discloses a display panel and an electronic device, wherein the display panel comprises a display medium layer arranged between a first substrate and a second substrate, a first scanning line, a second scanning line, a first data line and a second data line are arranged on the first substrate and define a pixel region in a staggered manner, the pixel region comprises a pixel electrode arranged on the first substrate, a common electrode is arranged on the pixel electrode, the common electrode comprises a first slit adjacent to the first data line and a second slit adjacent to the second data line in the pixel region, the first slit is provided with a first edge closest to the first data line, the second slit is provided with a second edge closest to the second data line, the pixel electrode is provided with a third edge positioned in the first slit and a fourth edge positioned in the second slit, and the distance from the first edge to the third edge is not equal to the distance from the second edge to the fourth edge.

Description

Display panel and electronic device

Technical Field

The present invention relates to a display panel, and more particularly, to an arrangement of a pixel electrode and a common electrode of a wide viewing angle liquid crystal display panel, and an electronic device including the display panel.

Background

In recent years, liquid crystal displays have been widely used in various electronic devices such as notebook computers, tablet computers, mobile phones, and the like because of their advantages such as thinness, lightweight, and low power consumption. In addition, for the application of large-sized displays, characteristics such as fast response, high contrast, and wide viewing angle are required, and In-plane Switching (IPS) type liquid crystal displays or Fringe Field Switching (FFS) type liquid crystal displays are wide viewing angle liquid crystal displays that can satisfy the above requirements.

The Fringe Field Switching (FFS) lcd has a transparent conductive pixel electrode and a common electrode, and the distance between the pixel electrode and the common electrode is smaller than the gap between the two substrates, so that a fringe field effect is generated between the pixel electrode and the common electrode to drive the liquid crystal to rotate.

However, it is difficult for a general Fringe Field Switching (FFS) type liquid crystal display to satisfy the transmittance of a bright state at every viewing angle.

Disclosure of Invention

The invention provides a configuration mode of a pixel electrode and a common electrode of a display panel, which enables a boundary electric field switching (FFS) type display panel to meet the requirement of bright state penetration rate at each visual angle. According to the display panel, the edge of the pixel electrode is arranged in the slit of the common electrode, and the distance relation among the edge of the pixel electrode, the slit edge of the common electrode and the edge of the data line is adjusted, so that the bright-state transmittance, the dark-state transmittance and the visual angle maintenance rate of the display panel can be in a required design range, and the display quality of the display panel is improved.

In some embodiments of the present invention, a display panel is provided, which includes a first substrate and a second substrate disposed opposite to each other, and a display medium layer disposed between the first substrate and the second substrate. The first scanning line and a second scanning line adjacent to the first scanning line, and the first data line and a second data line adjacent to the first data line are all arranged on the first substrate, wherein the first scanning line, the second scanning line, the first data line and the second data line define a pixel area in a staggered mode. The pixel region comprises a pixel electrode arranged on the first substrate, a common electrode arranged on the pixel electrode, and a first slit and a second slit which are arranged in the pixel region and correspond to the common electrode, wherein the first slit is adjacent to the first data line and is provided with a first edge closest to the first data line; the second slit is adjacent to the second data line and has a second edge closest to the second data line; the pixel electrode has a third edge located in the first slit and a fourth edge located in the second slit, and a first distance from the first edge to the third edge is not equal to a second distance from the second edge to the fourth edge.

In some embodiments of the present invention, an electronic device is further provided, where the electronic device includes the display panel, and the touch sensing structure is disposed on an inner surface of the second substrate of the display panel facing the first substrate, or on an outer surface of the second substrate opposite to the inner surface.

Drawings

FIG. 1 is a schematic partial plan view of a display panel according to some embodiments;

FIG. 2 is a schematic partial cross-sectional view of the display panel of FIG. 1 along section line a1-a2 according to some embodiments;

FIG. 3 is a schematic partial plan view of a display panel according to other embodiments;

FIG. 4 is a schematic partial cross-sectional view of the display panel of some embodiments, taken along section line b1-b2 of FIG. 3;

FIG. 5A is an enlarged schematic plan view of a region A of the display panel of FIG. 1 and a region B of the display panel of FIG. 3 according to some embodiments;

FIG. 5B is a schematic enlarged plan view of a region A of the display panel of FIG. 1 and a region B of the display panel of FIG. 3 according to other embodiments;

FIG. 6 is a graph of the bright state transmittance of the display panel with the same height as the first ratio parameter and the second ratio parameter according to some embodiments;

FIG. 7 is a graph of viewing angle maintenance of a display panel with equal height for a first ratio parameter and a second ratio parameter according to some embodiments;

FIG. 8 is a graph of the bright state transmittance of the display panel with the first offset parameter and the second offset parameter at equal heights according to some embodiments;

FIG. 9 is a graph of the transmittance of the display panel in the dark state versus the first ratio parameter and the second ratio parameter for some embodiments;

FIG. 10A is a schematic view of an electronic device, according to some embodiments;

FIG. 10B is a cross-sectional view of the electronic device along section line B-B of FIG. 10A according to some embodiments;

FIG. 10C is a cross-sectional view of the electronic device along section line B-B of FIG. 10A according to still other embodiments.

Description of the symbols

100-a display panel;

101-a first substrate; 102 to a second substrate;

102F-outer surface; 102B-an inside surface;

103-a display medium layer;

104-spacer;

105 to a first insulating layer; 106 to the second insulating layer;

107 to a third insulating layer; 108 to a fourth insulating layer;

109-black matrix;

110-data line;

110-1 to a first data line; 110-2 to a second data line;

111-source electrode;

112-a first alignment layer;

114 to a second alignment layer;

115. 117, 119, 162, 180-port;

120-scanning line;

121-a gate electrode;

130-shared electrode line;

140 to pixel electrodes;

150-a common electrode;

152. 152-3, 152-4 to a slit;

152-1 to a first slit; 152-2 to a first slit;

154-opening;

160-a drain electrode;

170-active layer;

s1-a first width; s2-a second width;

a1 to a fifth distance; a2 sixth distance;

b 1-a first distance; b 2-a second distance;

c 1-third distance; c2 to a fourth distance;

e1-first edge; e2-second edge;

e3-third edge; e4 fourth edge;

e5-fifth edge; e6 sixth edge;

e7-closest edge of first data line;

e8-closest edge of second data line;

p pixel area;

b-area;

300-an electronic device;

300A-active area; 300B-peripheral area;

200-touch sensing structure.

Detailed Description

Fig. 1 is a partial plan view of a display panel 100 according to some embodiments of the invention. The display panel 100 includes a plurality of data lines 110, the data lines 110 may be in a non-linear layout, such as a layout with a curved line, but generally have a substantial extending direction, such as an extending direction approximately along the Y-axis, and the data lines 110 are generally parallel to each other. In addition, the display panel 100 further includes a plurality of scan lines 120, the scan lines 120 may be in a linear layout form or a non-linear layout form, but substantially have a substantially extending direction, such as an extending direction approximately along the X-axis, and the scan lines 120 are substantially parallel to each other.

Two adjacent data lines 110 and two adjacent scan lines 120 are interlaced to define a pixel region, and the display panel 100 has a plurality of pixel regions. The pixel regions include pixel electrodes 140 and common electrodes 150, and in some embodiments, the display panel 100 is a Fringe Field Switching (FFS) type display panel having pixel electrodes 140 that are full-segment electrodes covering a portion of a pixel region in one pixel region, and the pixel electrodes 140 of adjacent pixels are spaced apart and electrically separated; the common electrode 150 has a plurality of slits 152 in one pixel region, as shown in fig. 1, in some embodiments, the common electrode 150 has three slits 152 in one pixel region, and the common electrodes 150 of adjacent pixels are connected together. According to some embodiments of the present invention, the common electrode 150 is disposed above the pixel electrode 140, and the edge of the pixel electrode 140 is located in the two slits 152 of the common electrode 150.

In addition, as shown in fig. 1, there is a common electrode line 130 under the scan line 120, the common electrode line 130 has substantially the same extending direction as the scan line 120, for example, an extending direction approximate to the X axis, and the common electrode 150 is electrically connected to the common electrode line 130 through a contact hole (contact hole) 180. In addition, a thin-film transistor (TFT) is disposed adjacent to an intersection of the scan line 120 and the data line 110, and is a switching element electrically connected to the data line 110 for controlling the pixel region.

The thin film transistor includes a gate electrode (gate electrode)121 formed of a portion of the scan line 120, a source electrode (source electrode)111 formed of a portion of the data line 110, a drain electrode (drain electrode)160, and an active layer (active layer)170 formed of a semiconductor material. As shown in fig. 1, the pixel electrode 140 is electrically connected to the drain electrode 160 through the connection hole 162. In addition, the common electrode 150 further has an opening 154 corresponding to the position of the thin film transistor, so as to prevent the common electrode 150 from generating electrical interference to the thin film transistor.

FIG. 2 is a partial cross-sectional view of the display panel 100 taken along section line a1-a2 of FIG. 1 according to some embodiments of the invention. As shown in fig. 2, the scan lines 120, the gate electrodes 121 formed of a portion of the scan lines 120, and the common electrode lines 130 are formed on the first substrate 101. In some embodiments, the scan lines 120, the gate electrodes 121 and the common electrode lines 130 may be formed by a same conductive layer, such as a metal layer, through deposition, photolithography and etching processes.

As shown in fig. 2, the first insulating layer 105 is formed on the scan lines 120, the gate electrodes 121, and the common electrode lines 130, and the first insulating layer 105 located above the gate electrodes 121 serves as a gate dielectric layer. The active layer 170 is formed on the first insulating layer 105, and in some embodiments, the material of the active layer 170 is amorphous silicon (amorphous silicon). In the embodiment of fig. 2, the thin film transistor is a bottom-gate Thin Film Transistor (TFT). The source electrode 111 and the drain electrode 160 of the thin film transistor are formed on the active layer 170, and in some embodiments, the data line 110, the source electrode 111 formed by a portion of the data line 110, and the drain electrode 160 are formed by a same conductive layer, such as a metal layer, through deposition, photolithography, and etching processes.

As shown in fig. 2, the second insulating layer 106 is formed on the source electrode 111 and the drain electrode 160, and on the active layer 170 and the first insulating layer 105. In some embodiments, the third insulating layer 107, which is a flat layer, is formed on the second insulating layer 106 (in other embodiments, the third insulating layer 107 may not be formed). A connection hole 162 is formed in the second insulating layer 106 and the third insulating layer 107, and the pixel electrode 140 is formed on the third insulating layer 107 and conformably within the connection hole 162, the pixel electrode 140 being electrically connected to the drain electrode 160 via the connection hole 162.

As shown in fig. 2, the fourth insulating layer 108 is formed on the pixel electrode 140 and conformably formed in the connection hole 162. Further, a connection hole 180 is formed in the first, second, third and fourth insulating

layers

105, 106, 107 and 108, and the common electrode 150 is formed on the fourth insulating layer 108 and conformably formed in the connection hole 180, so that the common electrode 150 is electrically connected to the common electrode line 130 through the connection hole 180. The common electrode 150 has a plurality of slits 152 in one pixel region, and may further have openings 154 corresponding to positions of the thin film transistors to avoid positions of channel regions of the thin film transistors.

In some embodiments, the pixel electrode 140 and the common electrode 150 are made of a transparent conductive material, such as Indium Tin Oxide (ITO), and the pixel electrode 140 or the common electrode 150 can be formed by deposition, photolithography, and etching processes. In some embodiments, the material of the first insulating layer 105, the second insulating layer 106, the third insulating layer 107, and the fourth insulating layer 108 may be an inorganic insulating material of silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing, and the material of the first insulating layer 105, the second insulating layer 106, the third insulating layer 107, and the fourth insulating layer 108 may be the same or different; in addition, the concentration ratios of the materials of the first insulating layer 105, the second insulating layer 106, the third insulating layer 107, and the fourth insulating layer 108 may be different, for example, the concentration ratios of the materials of the insulating layers may be different by adjusting the concentration of nitrogen or oxygen gas for forming each insulating layer or the time of the forming process. In some embodiments, the third insulating layer 107, which is a planarization layer, may be made of an organic material, such as a polyfluoroalkoxy Poly Fluoro Alkoxy (PFA) or a Color Filter (Color Filter) material.

As shown in fig. 2, the display panel 100 further has a second substrate 102 disposed opposite to the first substrate 101, and in some embodiments, the first substrate 101 and the second substrate 102 are, for example, glass substrates, plastic substrates, flexible substrates (flexible substrates), or barrier films (barrier films). A display medium layer 103 is interposed between the first substrate 101 and the second substrate 102. In some embodiments, the display medium layer 103 may be a liquid crystal layer, the second substrate 102 may be a Color Filter (CF) substrate, and the first substrate 101 may be a thin film transistor Array (TFT Array) substrate. In other embodiments, a color filter layer may be disposed on the first substrate 101, for example, the third insulating layer 107 may be replaced by a color filter layer material, or another color filter layer may be disposed between the second insulating layer 106 and the fourth insulating layer 108. In addition, a spacer 104, such as a photo spacer (photo spacer), is disposed between the first substrate 101 and the second substrate 102, the spacer 104 extends into the display medium layer 103, and the spacer 104 can support and determine a space (cell gap) between the first substrate 101 and the second substrate 102, the spacer 104 can be disposed on the first substrate 101 or the second substrate 102, and the spacer 104 can have different heights depending on design requirements. A Black Matrix (BM) 109 is further disposed between the spacer 104 and the second substrate 102, and a first alignment layer 112 is conformably formed on the common electrode 150 and the fourth insulating layer 108; a second alignment layer 114 is conformally formed on the spacers 104, the black matrix 109 and the second substrate 102, and the display medium layer 103 is interposed between the first alignment layer 112 and the second alignment layer 114. In addition, the display panel 100 may further include other elements not shown in fig. 2, such as upper and lower polarizers. In other embodiments, the black matrix 109 may also be disposed on the first substrate 101, depending on design requirements.

Fig. 3 is a partial plan view of the display panel 100 according to another embodiment of the invention. In the display panel 100 of fig. 3, the active layer 170 of the thin film transistor is made of low-temperature polysilicon (LTPS), and the thin film transistor is a dual-gate top-gate thin film transistor (top-gate TFT). According to some embodiments of the present disclosure, the display panel 100 of fig. 3 is a Fringe Field Switching (FFS) type liquid crystal display panel, the common electrode 150 is disposed above the pixel electrode 140, and the edge of the pixel electrode 140 adjacent to the data line 110 is located in two slits 152 of the common electrode 150. In the display panel 100 of fig. 3, the common electrode lines are not disposed below the scan lines 120.

FIG. 4 is a partial cross-sectional view of the display panel 100 taken along section line b1-b2 of FIG. 3 according to some embodiments of the invention. As shown in fig. 4, an active layer 170 is formed on a first substrate 101, a first insulating layer 105 is formed on the active layer 170 as an insulating dielectric layer with a gate electrode, a dual gate electrode composed of a portion of a scan line 120 is formed on the first insulating layer 105, and a second insulating layer 106 is formed on the dual gate electrode. As shown in fig. 4, a channel region generated at the overlapping portion of the active layer 170 and the dual gate formed by a portion of the scan line 120 is located above the active layer 170, so the thin film transistor is called a top-gate thin film transistor (top-gate TFT). In addition, connection holes 115 and 117 are formed in the first and second insulating

layers

105 and 106, and a source electrode formed of a portion of the data line 110 is formed on the second insulating layer 106 and conformably formed in the connection hole 115 to be electrically connected to the active layer 170. A drain electrode 160 of the tft is also formed on the second insulating layer 106 and conformably formed in the via 117 to electrically connect to the active layer 170.

As shown in fig. 4, a third insulating layer 107 is formed over the second insulating layer 106 and covers the thin film transistor. A connection hole 119 is formed in the third insulating layer 107 to expose a portion of the drain electrode 160. The pixel electrode 140 is formed on the third insulating layer 107 and conformably formed in the connection hole 119 so that the pixel electrode 140 is electrically connected to the drain electrode 160 through the connection hole 119.

As shown in fig. 4, the fourth insulating layer 108 is formed on the pixel electrode 140 and conformably formed in the connection hole 119. The common electrode 150 is formed on the fourth insulating layer 108 and conformably formed in the contact hole 119. The common electrode 150 has a plurality of slits 152 in one pixel region. The display panel 100 further includes a second substrate 102 disposed opposite to the first substrate 101, and a display medium layer 103, such as a liquid crystal layer, is interposed between the first substrate 101 and the second substrate 102. The spacers 104 may be disposed on the first substrate 101 or may be disposed on the second substrate 102, and the spacers 104 may have different heights according to design requirements. A Black Matrix (BM) 109 is further disposed between the spacer 104 and the second substrate 102, and a first alignment layer 112 is conformably formed on the common electrode 150 and the fourth insulating layer 108; a second alignment layer 114 is conformally formed on the spacers 104, the black matrix 109 and the second substrate 102, and the display medium layer 103 is interposed between the first alignment layer 112 and the second alignment layer 114. In addition, the display panel 100 may further include other elements not shown in fig. 4, such as upper and lower polarizers.

Fig. 5A is a schematic plan view of an area a of the display panel 100 of fig. 1 and an area B of the display panel 100 of fig. 3, wherein the rectangular areas a and B are obtained in a manner that the long sides of the rectangle are perpendicular to the extending direction of two adjacent data lines 110 of a pixel area, and thus the distances in fig. 5A are also determined in a manner of being perpendicular to the extending direction of the data lines 110 according to some embodiments of the invention.

Referring to fig. 5A, a pixel region P is between the first data line 110-1 and the second data line 110-2, and in some embodiments, the common electrode 150 shown in fig. 1 and 3 corresponds to one pixel region P having three slits 152-1 to 152-3. In some other embodiments, as shown in fig. 5B, the common electrode 150 may have four slits 152-1 to 152-4 corresponding to one pixel region P. As shown in fig. 5A and 5B, the common electrode 150 at least includes a first slit 152-1 adjacent to the first data line 110-1 and a second slit 152-2 adjacent to the second data line 110-2 in one pixel region P. As shown in fig. 5A and 5B, the first slit 152-1 has a first edge E1 closest to the first data line 110-1 and a fifth edge E5 away from the first data line 110-1, the first edge E1 and the fifth edge refer to the segment edges approximately substantially parallel to the extending direction of the first slit 152-1; the second slit 152-2 has a second edge E2 closest to the second data line 110-2 and a sixth edge E6 away from the first data line 110-1, and the second edge E2 and the sixth edge E6 refer to the segment edges approximately substantially parallel to the extending direction of the first slit 152-2.

According to the embodiment of the invention, in one pixel region P, the pixel electrode 140 has a third edge E3 located in the first slit 152-1, the third edge E3 refers to the segment edge approximately substantially parallel to the extending direction of the first slit 152-1; and the pixel electrode 140 has a fourth edge E4 located in the second slit 152-2, the fourth edge E4 refers to the edge of the segment approximately substantially parallel to the extending direction of the first slit 152-2. Selecting the edge E3 of the pixel electrode 140 to be within the slit of the common electrode 150 allows the edge E3 of the pixel electrode 140 not to be aligned with or completely overlap the two inner and outer edges E1, E5 of the slit of the common electrode 150. This is because when the edge E3 of the pixel electrode 140 is aligned with or completely overlaps the inner edge E5 of the slit of the common electrode 150, the fringe electric field generated between the pixel electrode 140 and the common electrode 150 cannot drive the liquid crystal effectively, and the bright state transmittance and the viewing angle maintenance ratio of the display panel are not good; when the edge E3 of the pixel electrode 140 is aligned with the outer edge E1 of the slit of the common electrode 150, the viewing angle maintenance ratio of the display panel is poor. The edge E4 of the pixel electrode 140 is also disposed at the same position as described above.

The viewing angle maintenance ratio is defined by a ratio of luminance of the display panel when the theta angle is 45 degrees and the phi angle is 45 degrees to luminance of the display panel when the theta angle is 45 degrees and the phi angle is 0 degrees, wherein the theta angle is an angle (for example, an angle between the theta angle and a substrate plane direction perpendicular to the display panel) to the substrate plane direction; and the included angle Φ is an included angle (for example, an included angle with the X-axis direction) with a direction in which the scanning lines of the display panel substantially extend. In this embodiment, when the angle θ is 45 degrees and the angle Φ is 45 degrees, the angle between the viewing angle and the absorption axis of the polarizer of the display panel is 45 degrees; when the included angle theta is 45 degrees and the included angle phi is 0 degree, the included angle between the visual angle and the polarized light plate absorption axis of the display panel is 0 degree. The brightness of the display panel may be measured using a light intensity instrument, such as model CA210, CS1000, or CS 2000. As the viewing angle maintenance ratio is higher, it means that the display panel can maintain the required brightness more uniformly at various viewing angles, and has good display quality.

Referring to fig. 5A and 5B, the common electrode 150 has a first slit 152-1 closer to the first data line 110-1, the first slit 152-1 has a fifth edge E5 opposite to the first edge E1 and farther from the first data line 110-1, a vertical distance between the fifth edge E5 and the third edge E3 of the pixel electrode 140 is a fifth distance a1, and the first slit 152-1 has a first width S1. Similarly, the common electrode 150 has a second slit 152-2 closer to the second data line 110-2, the second slit 152-2 has a sixth edge E6 opposite to the second edge E2 and farther from the second data line 110-2, a vertical distance from the sixth edge E6 to the fourth edge E4 of the pixel electrode 140 is a sixth distance a2, and the second slit 152-2 has a second width S2.

Referring to fig. 5A and 5B, a perpendicular distance between the first edge E1 of the first slit 152-1 to the closest edge E7 of the first data line 110-1 is a third distance c 1. Similarly, the perpendicular distance from the second edge E2 of the second slit 152-2 to the closest edge E8 of the second data line 110-2 is a fourth distance c 2.

Referring to fig. 6 and 7, fig. 6 is a graph illustrating the bright state transmittance of the display panel 100 according to some embodiments of the present invention, and the first ratio parameter on the vertical axis and the second ratio parameter on the horizontal axis are equal to each other. The first ratio parameter is a percentage of the fifth distance a1 divided by the first width S1(a1/S1), or a percentage of the sixth distance a2 divided by the second width S2(a2/S2), and the two first ratio parameters are not limited to be simultaneously satisfied or equal in the embodiments of the disclosure, and two different first ratio parameters may be respectively designed according to design requirements, that is, the two first ratio parameters may be the same or different; the second ratio parameter is a percentage of the third distance c1 divided by the first width S1(c1/S1), or a percentage of the fourth distance c2 divided by the second width S2(c2/S2), and the two second ratio parameters are not limited to be simultaneously satisfied or equal in the embodiments of the present invention, and two different second ratio parameters may be respectively designed according to design requirements, that is, the two second ratio parameters may be the same or different. Fig. 7 is a graph of the viewing angle maintenance rate of the display panel 100 plotted against a first ratio parameter on the vertical axis and a second ratio parameter on the horizontal axis according to some embodiments of the present disclosure. The first ratio parameter and the second ratio parameter may be designed according to design requirements, or may be designed in combination with each other, which is not limited herein.

As shown in fig. 6 and 7, when the first ratio parameter (a1/S1 or a2/S2) is equal to 0%, both the bright state transmittance and the viewing angle maintenance ratio are poor; when the first ratio parameter (a1/S1 or a2/S2) is equal to 100%, the viewing angle maintenance ratio is less excellent. Therefore, according to the embodiment of the present invention, the first ratio parameter (a1/S1 or a2/S2) is selected not to be equal to 0% or 100%, i.e., a1 or a2 is not 0, a1 is not equal to S1, or a2 is not equal to S2, i.e., the third edge E3 or the fourth edge E4 of the pixel electrode 140 is respectively located in the first slit 152-1 and the second slit 152-2 of the common electrode 150 without overlapping with the segment edge of the first slit 152-1 and the second slit 152-2 of the common electrode in the direction approximately parallel to the slit extension direction, so that the display panel 100 has better light state transmittance and viewing angle maintenance.

In addition, referring to fig. 7, in some embodiments of the present invention, when the percentage of the third distance c1 divided by the first width S1(c1/S1) is greater than between 10% and 100% (not equal to 100%), the viewing angle maintenance rate of the display panel may be greater than 0.90. In another embodiment, when the percentage of the fourth distance c2 divided by the second width S2(c2/S2) is greater than between 10% and 100% (not equal to 100%), the viewing angle maintenance rate of the display panel may be greater than 0.90.

Referring to fig. 7, in other embodiments of the present invention, when the percentage of the third distance c1 divided by the first width S1(c1/S1) is greater than 12.5% to 100% (not equal to 100%), the viewing angle maintenance rate of the display panel may be greater than 0.91. In another embodiment, when the percentage of the fourth distance c2 divided by the second width S2(c2/S2) is greater than between 12.5% and 100% (not equal to 100%), the viewing angle maintenance rate of the display panel may be greater than 0.91.

Therefore, the percentage of the third distance c1 divided by the first width S1(c1/S1) or the percentage of the fourth distance c2 divided by the second width S2(c2/S2) may be selected according to the requirement of the viewing angle maintenance ratio of the display panel.

Referring to fig. 7, in some embodiments of the invention, the percentage of the fifth distance a1 divided by the first width S1(a1/S1) may be between 17.5% and 98%. Likewise, the percentage of the sixth distance a2 divided by the second width S2(a2/S2) may be between 17.5% and 98%. This is because when the percentages of a1/S1 and a2/S2 are between 17.5% and 98%, the viewing angle maintenance ratio of the display panel can be greater than 0.91, and better display quality is achieved.

Referring to fig. 5A and 5B, a vertical distance from the first edge E1 to the third edge E3 is defined as a first distance B1, and a vertical distance from the second edge E2 to the fourth edge E4 is defined as a second distance B2, and according to some embodiments of the invention, the first distance B1 is not equal to the second distance B2. In another embodiment, the difference between the first distance b1 and the second distance b2 is between 0.5 μm and 20 μm. In yet another embodiment, the difference between the first distance b1 and the second distance b2 is between 0.5 μm and 10 μm. In yet another embodiment, the difference between the first distance b1 and the second distance b2 is between 0.5 μm and 5 μm. Therefore, when the manufacturing process of the display panel generates slight variation and the elements of the display panel are deviated, the bright state transmittance of the display panel is still in a stable interval and is not changed suddenly, and the display quality of the display panel can be maintained.

Referring to fig. 5A and 5B, the first slit 152-1 of the common electrode 150 has a first width S1, a perpendicular distance from the first edge E1 of the first slit 152-1 to the closest edge E7 of the first data line 110-1 is a third distance c1, and the edge E7 of the first data line 110-1 indicates an edge of the segment approximately substantially parallel to the extending direction of the first slit 152-1. The first offset (M-shift 1) is defined as the first offset (M-shift 1) obtained by subtracting the third distance c1 from one half of the first width S1 and dividing by the first width S1, i.e., (S1/2-c 1)/S1. Similarly, the second slit 152-2 of the common electrode 150 has a second width S2, the perpendicular distance from the second edge E2 of the second slit 152-2 to the nearest edge E8 of the second data line 110-2 is a fourth distance c2, and the edge E8 of the second data line 110-2 is about substantially parallel to the extending direction of the first slit 152-2. The second offset (M-shift2) is defined as the second offset (M-shift2) obtained by dividing one half of the second width S2 minus the fourth distance c2 by the second width S2, i.e., (S2/2-c 2)/S2.

Referring to fig. 5A and 5B, the first slit 152-1 of the common electrode 150 has a first width S1, and a third offset (P-shift3) is defined by subtracting the fifth distance a1 defined above from one half of the first width S1 and dividing by the first width S1, i.e., the third offset (P-shift3) is (S1/2-a 1)/S1. In another embodiment, the second slit 152-2 of the common electrode 150 has a second width S2, and the fourth offset (P-shift 4) is defined as the fourth offset (S2/2-a2)/S2 by dividing the second width S2 by the above-defined sixth distance a2 subtracted from one half of the second width S2.

Referring to fig. 8, fig. 8 is an isometric view of the bright-state transmittance of the display panel 100 according to some embodiments of the present invention, as compared with a first shift parameter on the vertical axis and a second shift parameter on the horizontal axis, where the first shift parameter is a percentage of a first shift amount (M-shift 1) ((S1/2) -c1)/S1 or a second shift amount (M-shift2) ((S2/2) -c2)/S2, and the second shift parameter is a percentage of a third shift amount (P-shift3) ((S1/2) -a1)/S1 or a fourth shift amount (P-shift 4) ((S2/2) -a 2)/S2.

As shown in fig. 8, when the second shift parameter (P-shift3 or P-shift 4) is equal to 0%, i.e., S1/2 is equal to a1 or S2/2 is equal to a2, the bright state transmittance of the display panel is at the peak of the contour, and the bright state transmittance changes sharply as long as the manufacturing process of the display panel slightly varies, so that it is preferable to select the second shift parameter (P-shift3 or P-shift 4) not equal to 0%, i.e., the third edge E3 or the fourth edge E4 of the pixel electrode 140 is not located at the midpoint of the first slit 152-1 and the second slit 152-2 of the common electrode 150, respectively, and the first distance B1 shown in fig. 5A and 5B is not equal to the second distance B2, so that the display panel 100 can be produced with a good yield.

According to some embodiments of the present invention, the third offset (P-shift3) or the fourth offset (P-shift 4) is not equal to 0%, nor is it equal to + 50% or is not equal to-50% (not equal to +/-50%). This is because when the third offset (P-shift3) or the fourth offset (P-shift 4) is equal to 0%, that is, when the edge of the pixel electrode 140 is located at the midpoint of the first slit 152-1 or the second slit 152-2 of the common electrode 150, the transmittance of the display panel in the bright state changes abruptly as long as the elements shift due to slight variations in the manufacturing process of the display panel, and therefore the third offset (P-shift3) or the fourth offset (P-shift 4) is selected to be different from 0%.

In addition, when the third offset amount (P-shift3) or the fourth offset amount (P-shift 4) is equal to +/-50%, it indicates that the edge of the pixel electrode 140 is aligned with the inner or outer section edge of the first slit 152-1 or the second slit 152-2 of the common electrode 150, and at this time, the bright state transmittance and the viewing angle maintenance ratio of the display panel are not good, so that the display panel can have better display quality by selecting the third offset amount (P-shift3) or the fourth offset amount (P-shift 4) to be not equal to +/-50%.

Referring to fig. 8, in some embodiments of the present invention, the first offset (M-shift 1) of the vertical axis is selected to be between + 25% and-25%, or the second offset (M-shift2) is also selected to be between + 25% and-25%, so that the bright state transmittance of the display panel can be maintained in a flat region with a small variation, and thus the bright state transmittance of the display panel can be maintained within a desired value range when the manufacturing process of the display panel is varied. This is because the polarities of the left and right data lines are usually different in one pixel region, so the coupling (crosstalk) amount of the left and right data lines to the entire pixel is also different, and crosstalk interference (crosstalk-talk) is easily generated, and when the first offset (M-shift 1) or the second offset (M-shift2) is controlled to be between + 25% and-25%, the difference of the bright state transmittance of the display panel is relatively moderate, so that the display quality of the display panel can be maintained, and all the design values can be mixed and matched according to the design requirements, which is not limited herein.

Referring to fig. 9, fig. 9 is a graph of the dark state transmittance of the display panel 100 according to some embodiments of the present invention, as compared to a first ratio parameter (a1/S1 or a2/S2) on the vertical axis and a second ratio parameter (c1/S1 or c2/S2) on the horizontal axis, the lower the dark state transmittance, the better. As shown in fig. 9, when the second ratio parameter (c1/S1 or c2/S2) is closer to 0%, i.e., the first slit 152-1 or the second slit 152-2 of the common electrode 150 is closer to the first data line 110-1 or the second data line 110-2, respectively, the dark transmittance is abruptly changed, and the display panel is prone to light leakage. The display needs to have a relatively stable transmittance variation to reduce the influence of the manufacturing process variation, and therefore, the second ratio parameter (c1/S1 or c2/S2) is selected to be greater than 25% to 100% (not equal to 100%), so that the display panel 100 has a better display quality.

Referring to fig. 9, in other embodiments of the present invention, when the percentage of the third distance c1 divided by the first width S1(c1/S1) is greater than 25% to 100% (not equal to 100%), the transmittance of the display panel in the dark state may be between 0.0 and 0.1. Similarly, when the percentage of the fourth distance c2 divided by the second width S2(c2/S2) is greater than 25% to 100% (not equal to 100%), the dark transmittance of the display panel can be between 0.0 and 0.1, such that the display panel has good display quality and no light leakage occurs. This is because when the first edge E1 of the first slit 152-1 of the common electrode 150 is closer to the first data line 110-1 or the second edge E2 of the second slit 152-2 is closer to the second data line 110-2, the percentage of c1/S1 or c2/S2 is closer to 0%, and the brightness of the display panel may generate a sharp change, so that the crosstalk-talk (crosstalk-talk) phenomenon between adjacent pixels is easily visible, resulting in poor display quality, and thus the percentage of c1/S1 or c2/S2 is controlled to be greater than 25% to achieve a low dark transmittance.

Fig. 10A is a schematic diagram of an electronic device 300 according to some embodiments of the invention. In some embodiments, the electronic device 300 is an electronic product with touch control and display functions, such as a mobile phone, a tablet computer, a mobile phone, a video device, and the like. As shown in fig. 10A, the electronic device 300 has an active area 300A and a peripheral area 300B located outside the active area 300A, wherein the active area 300A can perform touch and display functions, and the outer frame of the electronic device 300 is located in the peripheral area 300B. In one embodiment, the peripheral region 300b may be disposed on three outer sides of the active region 300A without surrounding the active region 300A.

Fig. 10B is a cross-sectional view of the electronic device 300 taken along section line B-B of fig. 10A according to some embodiments of the invention. As shown in fig. 10B, the electronic device 300 includes the display panel 100, and the touch sensing structure 200 is disposed outside the second substrate 102 of the display panel 100; in one embodiment, the touch sensing structure 200 is disposed On the outer surface 102F (On-cell touch) of the second substrate 102 of the display panel 100, and the inner surface 102B of the second substrate 102 faces the display medium layer 103 of the display panel 100. In an embodiment, the touch sensing structure 200 further includes a passivation layer (not shown) disposed on an outer side of the second substrate 102 away from the display medium layer 103, and the touch sensing structure 200 is disposed between the second substrate 102 and the passivation layer (not shown). In an embodiment, the touch sensing structure 200 may be an Out-cell touch panel (Out-cell touch) and is bonded to the display panel 100 by adhesion.

FIG. 10C is a cross-sectional view of the electronic device 300 taken along section line B-B of FIG. 10A according to other embodiments of the present invention. As shown In fig. 10C, the electronic device 300 includes the display panel 100, and the Touch sensing structure 200 is disposed on an inner side surface 102B of the second substrate 102 of the display panel 100 facing the first substrate 101, In this embodiment, the Touch sensing structure 200 is an In-cell Touch (In-cell Touch) layer disposed In the display panel 100. In another embodiment, the Touch sensing structure 200 may be disposed only on the first substrate 101 of the display panel 100 (not shown), and this embodiment is also an In-cell Touch (In-cell Touch) layer disposed In the display panel 100. In another embodiment, the Touch sensing structure 200 may be disposed on the second substrate and the first substrate at the same time, respectively, in this embodiment, a Hybrid Touch structure (Hybrid Touch).

In summary, according to some embodiments of the present invention, the edge of the pixel electrode of the display panel is located in the slit of the common electrode, and the distance relationship between the edge of the pixel electrode, the edge of the slit of the common electrode, and the edge of the data line is adjusted, so that the bright state transmittance and the viewing angle maintenance rate of the display panel can be kept in a relatively stable or high value range, or the dark state transmittance of the display panel is kept in a relatively stable or low value range, thereby improving the display quality of the display panel. The embodiments can be used in combination without conflict, and design values of only a single embodiment are not limited.

Although the present invention has been described in connection with the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.

Claims

1. A display panel, comprising:

a first substrate;

a second substrate disposed opposite to the first substrate;

the display medium layer is arranged between the first substrate and the second substrate;

the first scanning line and the second scanning line adjacent to the first scanning line are arranged on the first substrate; and

the first data line and the second data line adjacent to the first data line are arranged on the first substrate;

wherein the first scan line, the second scan line, the first data line and the second data line define a pixel region in an interlaced manner, the pixel region includes:

a pixel electrode disposed on the first substrate;

a common electrode disposed on the pixel electrode, the common electrode including a first slit and a second slit corresponding to the pixel region,

the first slit is adjacent to the first data line and has a first edge closest to the first data line; the second slit is adjacent to the second data line and has a second edge closest to the second data line; the pixel electrode has a third edge located in the first slit, the pixel electrode has a fourth edge located in the second slit, and a first distance from the first edge to the third edge is not equal to a second distance from the second edge to the fourth edge, wherein the first distance is a vertical distance from the first edge to the third edge and the second distance is a vertical distance from the second edge to the fourth edge;

the first slit has a first width, a vertical distance from the first edge to a nearest edge of the first data line is a third distance, and a percentage of the third distance divided by the first width is between 10% and 100%.

2. The display panel of claim 1, wherein the first width divided by the third distance subtracted from one half of the first width is a first offset, and the first offset is between + 25% and-25%.

3. The display panel of claim 1, wherein the second slit has a second width, a fourth distance is between the second edge of the second slit and the closest edge of the second data line, a second offset is obtained by dividing the second width by one half of the second width minus the fourth distance, and the second offset is between + 25% and-25%.

4. The display panel of claim 1, wherein the second slit has a second width, a fourth distance is between the second edge of the second slit and the nearest edge of the second data line, and a percentage of the fourth distance divided by the second width is between 25% and 100%.

5. The display panel of claim 1, wherein the first slit has a fifth edge opposite to the first edge, a fifth distance is between the fifth edge and the third edge of the pixel electrode, and a percentage of the fifth distance divided by the first width is between 17.5% and 98%.

6. The display panel of claim 1, wherein the second slit has a sixth edge opposite to the second edge, a sixth distance is between the sixth edge and the fourth edge of the pixel electrode, the second slit has a second width, and a percentage of the sixth distance divided by the second width is between 17.5% and 98%.

7. The display panel of claim 1, wherein the first slit has a fifth edge opposite to the first edge, a fifth distance is provided between the fifth edge and the third edge of the pixel electrode, the first slit has a first width, a half of the first width minus the fifth distance divided by the first width is a third offset, and the third offset is not equal to 0% and not equal to +/-50%.

8. The display panel of claim 1, wherein the second slit has a sixth edge opposite to the second edge, a sixth distance is provided between the sixth edge and the fourth edge of the pixel electrode, the second slit has a second width, a fourth offset is provided by dividing one half of the second width minus the sixth distance by the second width, and the fourth offset is not equal to 0% and not equal to +/-50%.

9. The display panel of claim 1, wherein the difference between the first distance and the second distance is between 0.5 μm and 20 μm.

10. An electronic device, comprising:

a display panel, comprising:

a first substrate;

a second substrate disposed opposite to the first substrate;

a pixel electrode disposed on the first substrate;

the first slit is adjacent to the first data line and has a first edge closest to the first data line; the second slit is adjacent to the second data line and has a second edge closest to the second data line; the pixel electrode has a third edge located in the first slit, the pixel electrode has a fourth edge located in the second slit, and a first distance from the first edge to the third edge is not equal to a second distance from the second edge to the fourth edge, wherein the first distance is a vertical distance from the first edge to the third edge and the second distance is a vertical distance from the second edge to the fourth edge; and

a touch sensing structure disposed on the second substrate or the first substrate of the display panel,

11. The electronic device of claim 10, wherein the first width divided by the third distance subtracted from one half of the first width is a first offset, and the first offset is between + 25% and-25%.

12. The electronic device of claim 10, wherein the second slit has a second width, a fourth distance is between the second edge of the second slit and the closest edge of the second data line, a second offset is obtained by dividing the second width by one-half of the second width minus the fourth distance, and the second offset is between + 25% and-25%.

13. The electronic device of claim 10, wherein the second slit has a second width, a fourth distance is between the second edge of the second slit and the closest edge of the second data line, and a percentage of the fourth distance divided by the second width is between 25% and 100%.

14. The electronic device of claim 10, wherein the first slit has a fifth edge opposite to the first edge, a fifth distance is between the fifth edge and the third edge of the pixel electrode, and a percentage of the fifth distance divided by the first width is between 17.5% and 98%.

15. The electronic device of claim 10, wherein the second slit has a sixth edge opposite to the second edge, a sixth distance is between the sixth edge and the fourth edge of the pixel electrode, the second slit has a second width, and a percentage of the sixth distance divided by the second width is between 17.5% and 98%.

16. The electronic device of claim 10, wherein the first slit has a fifth edge opposite to the first edge, a fifth distance is provided between the fifth edge and the third edge of the pixel electrode, the first slit has a first width, a half of the first width minus the fifth distance divided by the first width is a third offset, and the third offset is not equal to 0% and not equal to +/-50%.

17. The electronic device of claim 10, wherein the second slit has a sixth edge opposite to the second edge, a sixth distance is provided between the sixth edge and the fourth edge of the pixel electrode, the second slit has a second width, a fourth offset is provided by dividing one-half of the second width minus the sixth distance by the second width, and the fourth offset is not equal to 0% and not equal to +/-50%.

18. The electronic device of claim 10, wherein a difference between the first distance and the second distance is between 0.5 μm and 20 μm.