CN106572528B - Clock synchronization method and device - Google Patents
Clock synchronization method and device Download PDFInfo
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- CN106572528B CN106572528B CN201610911167.2A CN201610911167A CN106572528B CN 106572528 B CN106572528 B CN 106572528B CN 201610911167 A CN201610911167 A CN 201610911167A CN 106572528 B CN106572528 B CN 106572528B
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Abstract
The application provides a clock synchronization method and a device, which are characterized in that the one-way transmission average time delay is obtained by calculating the time of a first main clock, the time of the first local clock, the time of a second local clock and the time of the second main clock, a counting value is obtained by controlling a field programmable logic gate array to start counting and stop counting, and the field programmable logic gate array is controlled to count to a specified value according to the clock frequency of a reference time source of the field programmable logic gate array according to the one-way transmission average time delay, the time of the second main clock and the counting value, and then a 1pps signal is output, so that the synchronization of a slave clock and the time of the main clock. Because the time server is adopted in the scheme, a GPS antenna does not need to be erected and corresponding indoor forwarding equipment does not need to be installed, the cost is low, the problem of being influenced by the weather does not exist, and the problems that the cost is high and the weather is easily influenced due to the fact that the GPS antenna and the corresponding indoor forwarding equipment are used when the time of the base station and the time of the global satellite positioning system are synchronized in the prior art are solved.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a clock synchronization method and apparatus.
Background
Currently, most test drivers develop communication standards in TDD duplex mode, such as TD-SCDMA, CDMA2000, WiMAX, etc., which have strict requirements on frequency/time synchronization, and often need to maintain accurate time synchronization between air interfaces of the whole network.
The global positioning satellite system (GPS) is the best choice of clock reference source to achieve time synchronization. The GPS is an antenna navigation system composed of 24 satellites orbiting the earth, and has advantages of global coverage, high system clock accuracy, and good long-term stability. At present, basically, all existing network devices use a GPS clock scheme, and a GPS signal receiving device is installed at each base station to receive a clock signal transmitted by a satellite and then transmit the clock signal to the base station to implement time synchronization.
The GPS signal receiving device comprises a GPS antenna and corresponding indoor forwarding equipment, is high in cost and is easily influenced by weather, and the system base stations are out of step in severe weather, so that the call drop rate is increased.
Therefore, a clock synchronization method for reducing the cost and weather effect when controlling the synchronization between the base station time and the time of the global positioning system is needed.
Disclosure of Invention
In view of the above, the present invention provides a clock synchronization method and apparatus, so as to solve the problems of high cost and being easily influenced by weather due to the use of a GPS antenna and corresponding indoor forwarding equipment when controlling the synchronization between the base station time and the time of the global positioning system.
In order to solve the technical problems, the invention adopts the following technical scheme:
a method of clock synchronization, comprising:
acquiring a first local clock when a first received message is received; the first message is sent by a master clock of a clock server, and the first message carries a first master clock when the master clock sends the first message; the clock server is a clock server which locks a global positioning satellite system;
calculating to obtain the one-way transmission time delay from the master clock to the slave clock according to the first local clock and the first master clock;
generating an interrupt;
controlling a field programmable gate array to start counting;
judging whether the interruption is overtime;
judging that the interruption is overtime, and sending a second message to the master clock;
acquiring a second local clock when the second message is sent;
acquiring a second master clock when the master clock receives the second message;
calculating to obtain the one-way transmission time delay from the slave clock to the master clock according to the second local clock and the second master clock;
calculating to obtain the average time delay of the one-way transmission according to the one-way transmission time delay from the master clock to the slave clock and the one-way transmission time delay from the slave clock to the master clock;
controlling the field programmable gate array to stop counting;
acquiring a count value of the field programmable gate array;
controlling the field programmable gate array to count to a specified value according to the clock frequency of the reference time source of the field programmable gate array according to the one-way transmission average time delay, the second master clock and the count value;
and controlling the field programmable logic gate array to output a 1pps signal.
Preferably, the first and second electrodes are formed of a metal,
the obtaining of the first local clock when the first received packet is received includes:
receiving a first protocol packet sent from a physical layer chip through a precision time synchronization protocol, wherein the first protocol packet comprises the first local clock;
the obtaining of the second local clock when the second packet is sent includes:
receiving a second protocol packet sent from a physical layer chip through a precision time synchronization protocol, wherein the second protocol packet comprises the second local clock;
the obtaining of the second master clock when the master clock receives the second packet includes:
and receiving a third message sent by the master clock, wherein the third message carries a second master clock when the master clock receives the second message.
Preferably, the reference time source comprises an oven controlled crystal oscillator;
the clock synchronization method further comprises:
and performing frequency compensation according to the first master clock, the first local clock, a third master clock carried by the master clock when the master clock sends the first message next time, and a third local clock when the master clock receives the first message sent by the master clock next time.
Preferably, the reference time source comprises a common crystal oscillator;
the clock synchronization method further comprises:
frequency compensation is performed by adjusting the voltage.
Preferably, the controlling the field programmable gate array to count to a specified value according to the clock frequency of its reference time source according to the one-way transmission average delay, the second master clock and the count value includes:
calculating a counting starting point of the field programmable gate array; the calculation formula of the counting starting point is the second master clock, the average time delay of the unidirectional transmission and the counting value;
and controlling the field programmable gate array to count from the counting starting point to a specified value according to the clock frequency of the reference time source.
A clock synchronization apparatus, comprising:
the first obtaining unit is used for obtaining a first local clock when the first message is received; the first message is sent by a master clock of a clock server, and the first message carries a first master clock when the master clock sends the first message; the clock server is a clock server which locks a global positioning satellite system;
the first calculation unit is used for calculating the one-way transmission time delay from the master clock to the slave clock according to the first local clock and the first master clock;
an interrupt generation unit for generating an interrupt;
the first counting unit is used for controlling the field programmable logic gate array to start counting;
a judging unit for judging whether the interrupt is overtime;
the first sending unit is used for sending a second message to the master clock when the judging unit judges that the interruption is overtime;
a second obtaining unit, configured to obtain a second local clock when the second packet is sent;
a third obtaining unit, configured to obtain a second master clock when the master clock receives the second packet;
the second calculation unit is used for calculating the one-way transmission time delay from the slave clock to the master clock according to the second local clock and the second master clock;
the third calculating unit is used for calculating to obtain the average time delay of the unidirectional transmission according to the unidirectional transmission time delay from the master clock to the slave clock and the unidirectional transmission time delay from the slave clock to the master clock;
the second counting unit is used for controlling the field programmable logic gate array to stop counting;
the fourth acquisition unit is used for acquiring the count value of the field programmable logic gate array;
the third counting unit is used for controlling the field programmable gate array to count to a specified value according to the clock frequency of the reference time source of the field programmable gate array according to the unidirectional transmission average time delay, the second master clock and the counting value;
and the signal output unit is used for controlling the field programmable logic gate array to output a 1pps signal.
Preferably, the first and second electrodes are formed of a metal,
the first acquisition unit includes:
the first acquiring subunit is configured to receive, through a precision time synchronization protocol, a first protocol packet sent from a physical layer chip, where the first protocol packet includes the first local clock;
the second acquisition unit includes:
the second acquiring subunit is configured to receive, through a precision time synchronization protocol, a second protocol packet sent from a physical layer chip, where the second protocol packet includes the second local clock;
the third acquisition unit includes:
a third obtaining subunit, configured to receive a third packet sent by the master clock, where the third packet carries a second master clock when the master clock receives the second packet.
Preferably, when the reference time source includes an oven controlled crystal oscillator, the method further includes:
and the first frequency compensation unit is used for carrying out frequency compensation according to the first master clock, the first local clock and a third master clock carried by the master clock when the master clock sends a first message next time and the third local clock when the first acquisition unit acquires the received first message sent by the master clock next time.
Preferably, when the reference time source includes a common crystal oscillator, the method further includes:
and the second frequency compensation unit is used for carrying out frequency compensation through voltage adjustment.
Preferably, the third counting unit includes:
the fourth calculation unit is used for calculating the counting starting point of the field programmable logic gate array; the calculation formula of the counting starting point is the second master clock, the average time delay of the unidirectional transmission and the counting value;
and the counting subunit is used for controlling the field programmable logic gate array to count from the counting starting point to a specified value according to the clock frequency counting of the reference time source.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a clock synchronization method and a device, which are characterized in that the one-way transmission average time delay is obtained by calculating the time of a first main clock, the time of the first local clock, the time of a second local clock and the time of the second main clock, a counting value is obtained by controlling a field programmable logic gate array to start counting and stop counting, and the field programmable logic gate array is controlled to count to a specified value according to the clock frequency of a reference time source of the field programmable logic gate array according to the one-way transmission average time delay, the time of the second main clock and the counting value, and then a 1pps signal is output, so that the synchronization of a slave clock and the time of the main clock can be realized. Because the time server is adopted in the scheme, a GPS antenna does not need to be erected and corresponding indoor forwarding equipment does not need to be installed, the cost is low, the problem of being influenced by the weather does not exist, and the problems that the cost is high and the weather is easily influenced due to the fact that the GPS antenna and the corresponding indoor forwarding equipment are used when the time of the base station and the time of the global satellite positioning system are synchronized in the prior art are solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a method of clock synchronization provided by the present invention;
FIG. 2 is a flow chart of a message interaction process of a master clock and a slave clock;
fig. 3 is a schematic structural diagram of a clock synchronization apparatus provided in the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a clock synchronization method, which comprises the following steps with reference to fig. 1:
s101, acquiring a first local clock when a first received message is received;
the first message is sent by a master clock of the clock server, and the first message carries a first master clock when the master clock sends the first message.
It should be noted that, the transmission of the master clock and the slave clock may be single-step transmission or double-step transmission, when the transmission is single-step transmission, the first message is a Sync message, the Sync message carries a first master clock, when the transmission is double-step transmission, the first message is a Follow _ up message, the master clock first sends the Sync message, and when the Sync message is sent, the Follow _ up message, that is, the first message, is sent, and the Follow _ up message carries the first master clock.
Optionally, in another embodiment of the present invention, acquiring the first local clock when the first message is received includes:
a first protocol packet sent from a physical layer chip is received through a precision time synchronization protocol, and the first protocol packet comprises a first local clock.
Specifically, when the base station receives a first message sent by the master clock, the physical layer chip counts a clock generated by the local crystal oscillator clock, namely the first local clock, stamps the first local clock to an extended position of the first protocol packet, namely a timestamp, and sends the first protocol packet to the precision clock synchronization protocol PTP protocol processing module of the central processing unit through the precision time synchronization protocol.
And S102, calculating the one-way transmission time delay from the master clock to the slave clock according to the first local clock and the first master clock.
The method for calculating the one-way transmission delay from the master clock to the slave clock comprises the following steps:
specifically, a module for calculating the one-way transmission delay from the master clock to the slave clock is a PTP protocol processing module.
S103, generating an interrupt;
specifically, the PTP protocol processing module controls generation of an interrupt.
S104, controlling the field programmable logic gate array to start counting;
and when the PTP protocol processing module is controlled to generate interruption, the field programmable gate array starts to be controlled to count from zero.
S105, judging whether the interruption is overtime; when the interruption time is judged to be overtime, S106 is executed;
specifically, the PTP protocol processing module sets an interrupt time, determines whether the interrupt time is reached after the control generates the interrupt, and proves that the interrupt is overtime when the interrupt time is reached.
S106, sending a second message to a master clock;
specifically, when the timeout is determined, the PTP protocol processing module marks the timeout, and calls a callback function registered in the network driver to send a second message, where the second message is a delay _ req message.
S107, acquiring a second local clock when the second message is sent;
optionally, in another embodiment of the present invention, the obtaining a second local clock when the second packet is sent includes:
and receiving a second protocol packet transmitted from the physical layer chip through the precise time synchronization protocol, wherein the second protocol packet comprises a second local clock.
Specifically, the manner of acquiring the second local clock is the same as the manner of acquiring the first local clock, and when the second message is sent, the physical layer chip counts a clock generated by the local crystal oscillator clock, that is, the second local clock, hits the second local clock to the extended position of the second protocol packet, and sends the second local clock to the PTP protocol processing module through the precision time synchronization protocol.
S108, acquiring a second master clock when the master clock receives a second message;
optionally, in another embodiment of the present invention, the obtaining the second master clock when the master clock receives the second packet includes:
and receiving a third message sent by the master clock, wherein the third message carries the second master clock when the master clock receives the second message.
Specifically, after receiving the second message, the master clock sends a third message to the slave clock, where the third message carries the second master clock when the master clock receives the second message. Wherein, the third message refers to a Delay _ resp message.
S109, calculating to obtain the one-way transmission time delay from the slave clock to the master clock according to the second local clock and the second master clock;
specifically, the calculation formula of the one-way transmission delay from the slave clock to the master clock is as follows:
and the one-way transmission time delay from the slave clock to the master clock is the second master clock and the second local clock. Specifically, the module for calculating the one-way transmission delay from the clock to the master clock is a PTP protocol processing module of the central processing unit.
S110, calculating to obtain the average time delay of the one-way transmission according to the one-way transmission time delay from the master clock to the slave clock and the one-way transmission time delay from the slave clock to the master clock;
specifically, the one-way transmission delay from the master clock to the slave clock is the average one-way transmission delay plus the time deviation of the master clock and the slave clock.
The one-way transmission time delay from the slave clock to the master clock is the average time delay of one-way transmission-the time deviation of the master clock and the slave clock.
According to the two formulas, the calculation formula for deriving the average time delay of the unidirectional transmission is as follows:
the average time delay of one-way transmission is (one-way transmission time delay from the master clock to the slave clock + one-way transmission time delay from the slave clock to the master clock)/2.
S111, controlling the field programmable logic gate array to stop counting;
and when the PTP protocol processing module calculates the average time delay of the unidirectional transmission, the field programmable gate array is controlled to stop counting.
S112, obtaining a counting value of the field programmable logic gate array;
specifically, the counting value of the field programmable gate array is a counting value of the field programmable gate array when the field programmable gate array is controlled to stop.
S113, controlling the field programmable gate array to count to a designated value according to the clock frequency of the reference time source of the field programmable gate array according to the one-way transmission average time delay, the second master clock and the count value;
optionally, in another embodiment of the present invention, controlling the field programmable gate array to count to a specified value according to the clock frequency of the reference time source of the field programmable gate array according to the one-way transmission average delay, the second master clock, and the count value includes:
calculating a counting starting point of the field programmable logic gate array; the calculation formula of the counting starting point is a second master clock, the one-way transmission average time delay and a counting value;
and controlling the field programmable gate array to start counting from the counting starting point according to the clock frequency of the reference time source and count to a specified value.
It should be noted that the calculation formula of the starting point of counting may also be the first master clock + the third master clock-the first local clock + the one-way transmission average delay + the count value;
the first master clock + the third master clock-the first local clock + the unidirectional transmission average delay + the count value is equivalent to the second master clock-the unidirectional transmission average delay + the count value, and the calculation formula for calculating the counting starting point is the second master clock-the unidirectional transmission average delay + the count value because the time of the master clock is accurate.
And S114, controlling the field programmable logic gate array to output a 1pps signal.
Specifically, after the counting starting point is counted, the PTP protocol processing module controls the field programmable gate array to start counting from the counting starting point according to the clock frequency of the reference time source, and outputs a 1pps signal after counting to a specified value.
The embodiment of the invention provides a clock synchronization method, which is characterized in that the unidirectional transmission average time delay is obtained by calculating the first main clock time, the first local clock time, the second local clock time and the second main clock time, the counting value is obtained by controlling the field programmable logic gate array to start counting and stop counting, and the field programmable logic gate array is controlled to count to a specified value according to the clock frequency of a reference time source of the field programmable logic gate array according to the unidirectional transmission average time delay, the second main clock time and the counting value, and then a 1pps signal is output, so that the synchronization of the slave clock and the main clock time can be realized. Because the time server is adopted in the scheme, a GPS antenna does not need to be erected and corresponding indoor forwarding equipment does not need to be installed, the cost is low, the problem of being influenced by the weather does not exist, and the problems that the cost is high and the weather is easily influenced due to the fact that the GPS antenna and the corresponding indoor forwarding equipment are used when the time of the base station and the time of the global satellite positioning system are synchronized in the prior art are solved.
Optionally, in another embodiment of the present invention, the reference time source is an oven controlled crystal oscillator;
the clock synchronization method further comprises:
and performing frequency compensation according to the first master clock, the first local clock, a third master clock carried by the master clock when the master clock sends the first message next time, and a third local clock when the master clock receives the first message sent by the master clock next time.
Specifically, when the reference time source includes an oven controlled crystal oscillator, the precision of the oven controlled crystal oscillator is high, and the frequency difference between the master clock and the slave clock is small, at this time, in order to reduce the frequency difference, a frequency compensation method may be adopted, and specifically, the frequency compensation is performed according to the first master clock, the first local clock, and a third local clock carried by the master clock when the master clock transmits the first packet next time, and a third local clock when the master clock receives the first packet transmitted next time. It should be noted that, since the frequency difference between the master clock and the slave clock is small, it is also possible to perform no frequency compensation at this time.
Specifically, the transmission of the messages between the master clock and the slave clock is repeated continuously, a first message sent by the master clock carries the first master clock, a next first message sent by the master clock carries the third master clock, and when the slave clock receives the next first message sent by the master clock, the third local clock is obtained, and the frequency difference coefficient is calculated according to the first master clock, the first local clock, the third master clock and the third local clock.
The calculation formula of the frequency difference coefficient is as follows:
frequency difference coefficient ═ third master clock-first master clock)/(third local clock-first local clock).
And after calculating the frequency difference coefficient, compensating the one-way transmission average time delay, namely replacing (T2-T3) with the frequency difference coefficient (T2-T3).
In the embodiment, when the reference time source comprises an oven controlled crystal oscillator, the frequency difference coefficient pair is calculated
The frequency is compensated, and the frequency difference between the master clock and the slave clock can be reduced.
Optionally, in another embodiment of the present invention, the reference time source includes a common crystal oscillator;
the clock synchronization method further comprises:
frequency compensation is performed by adjusting the voltage.
Specifically, when the reference time source includes a common crystal oscillator, the frequency difference between the master clock and the slave clock is large due to the poor precision of the common crystal oscillator, and the frequency compensation is performed by a voltage adjustment method.
In this embodiment, when the reference time source includes a common crystal oscillator, the frequency compensation is performed by adjusting the voltage, so that the frequency difference between the master clock and the slave clock can be reduced.
In order to understand the message interaction process between the master clock and the slave clock more clearly, the explanation is now made with reference to fig. 2.
S201, sending a first message;
specifically, the master clock sends a first message to the slave clock, the first message is a Sync message when single-step transmission is performed between the master clock and the slave clock, and the first message is a Follow _ up message when double-step transmission is performed between the master clock and the slave clock.
S202, acquiring a first local clock when the first message is received;
after the slave clock receives the first message, the PTP protocol processing module obtains a first local clock from the physical layer chip. The PTP protocol processing module calculates and obtains the one-way transmission time delay from the master clock to the slave clock according to the first local clock and the first master clock.
S203, sending a second message;
specifically, when the PTP protocol processing module determines that the interrupt is overtime, the slave clock sends the second message to the master clock.
S204, acquiring a second local clock when the second message is sent;
specifically, the PTP protocol processing module obtains the second local clock from the physical layer chip.
S205, sending a third message;
it should be noted that the third packet carries the second master clock when the master clock receives the second packet.
At this time, the PTP protocol processing module calculates a one-way transmission delay from the slave clock to the master clock according to the second master clock and the second local clock.
The embodiment introduces a message interaction process between a master clock and a slave clock, and can calculate the one-way transmission delay from the master clock to the slave clock and the one-way transmission delay from the slave clock to the master clock by using time information carried in mutual transmission messages.
Optionally, another embodiment of the present invention provides a clock synchronization apparatus, referring to fig. 3, including:
a first obtaining unit 101, configured to obtain a first local clock when the first packet is received; the first message is sent by a master clock of a clock server, and the first message carries a first master clock when the master clock sends the first message; the clock server is a clock server which locks the global satellite positioning system;
the first calculating unit 102 is configured to calculate a one-way transmission delay from a master clock to a slave clock according to a first local clock and a first master clock;
an interrupt generation unit 103 for generating an interrupt;
the first counting unit 104 is used for controlling the field programmable gate array to start counting;
a judging unit 105 for judging whether the interrupt is overtime;
a first sending unit 106, configured to send a second message to the master clock when the determining unit 105 determines that the interrupt is overtime;
a second obtaining unit 107, configured to obtain a second local clock when the second packet is sent;
a third obtaining unit 108, configured to obtain a second master clock when the master clock receives the second packet;
a second calculating unit 109, configured to calculate a one-way transmission delay from the slave clock to the master clock according to the second local clock and the second master clock;
a third calculating unit 110, configured to calculate an average time delay of unidirectional transmission according to the unidirectional transmission time delay from the master clock to the slave clock and the unidirectional transmission time delay from the slave clock to the master clock;
the second counting unit 111 is used for controlling the field programmable logic gate array to stop counting;
a fourth obtaining unit 112, configured to obtain a count value of the field programmable gate array;
the third counting unit 113 is configured to control the field programmable gate array to count to a specified value according to the clock frequency of the reference time source of the field programmable gate array, according to the one-way transmission average delay, the second master clock and the count value;
and a signal output unit 114 for controlling the field programmable gate array to output a 1pps signal.
Optionally, in another embodiment of the present invention, the first obtaining unit 101 includes:
the first acquiring subunit is configured to receive, through a precision time synchronization protocol, a first protocol packet sent from a physical layer chip, where the first protocol packet includes a first local clock.
Optionally, in another embodiment of the present invention, the second obtaining unit 107 includes:
and the second acquisition subunit is used for receiving a second protocol packet sent from the physical layer chip through the precise time synchronization protocol, wherein the second protocol packet contains a second local clock.
Optionally, in another embodiment of the present invention, the third obtaining unit 108 includes:
and the third acquiring subunit is configured to receive a third packet sent by the master clock, where the third packet carries a second master clock when the master clock receives the second packet.
Optionally, in another embodiment of the present invention, the third counting unit 113 includes:
the fourth calculation unit is used for calculating the counting starting point of the field programmable logic gate array; the calculation formula of the counting starting point is a second master clock, the one-way transmission average time delay and a counting value;
and the counting subunit is used for controlling the field programmable gate array to count from the counting starting point to a specified value according to the clock frequency counting of the reference time source.
In this embodiment, the one-way transmission average time delay is calculated by the first master clock time, the first local clock time, the second local clock time, and the second master clock time, the count value is obtained by controlling the field programmable logic gate array to start counting and stop counting, and the 1pps signal is output after the field programmable logic gate array is controlled to count to a specified value according to the clock frequency of the reference time source of the field programmable logic gate array according to the one-way transmission average time delay, the second master clock time, and the count value, so that the slave clock and the master clock can be synchronized. Because the time server is adopted in the scheme, a GPS antenna does not need to be erected and corresponding indoor forwarding equipment does not need to be installed, the cost is low, the problem of being influenced by the weather does not exist, and the problems that the cost is high and the weather is easily influenced due to the fact that the GPS antenna and the corresponding indoor forwarding equipment are used when the time of the base station and the time of the global satellite positioning system are synchronized in the prior art are solved.
It should be noted that, please refer to the contents in the above embodiments for the working process of each unit in this embodiment, which is not described herein again.
Optionally, in another embodiment of the present invention, when the reference time source includes an oven controlled crystal oscillator, the method further includes:
and the first frequency compensation unit is configured to perform frequency compensation according to the first master clock, the first local clock, a third master clock carried when the master clock sends the first packet next time, and a third local clock when the first obtaining unit 101 obtains the received first packet sent by the master clock next time.
When the reference time source comprises a common crystal oscillator, the method further comprises the following steps:
and the second frequency compensation unit is used for carrying out frequency compensation through voltage adjustment.
In this embodiment, frequency compensation is performed, and the frequency difference between the master clock and the slave clock can be reduced.
It should be noted that, please refer to the contents in the above embodiments for the working process of each unit in this embodiment, which is not described herein again.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A method of clock synchronization, comprising:
acquiring a first local clock when a first received message is received; the first message is sent by a master clock of a clock server, and the first message carries a first master clock when the master clock sends the first message; the clock server is a clock server which locks a global positioning satellite system;
calculating to obtain the one-way transmission time delay from the master clock to the slave clock according to the first local clock and the first master clock;
generating an interrupt;
controlling a field programmable gate array to start counting;
judging whether the interruption is overtime;
judging that the interruption is overtime, and sending a second message to the master clock;
acquiring a second local clock when the second message is sent;
acquiring a second master clock when the master clock receives the second message;
calculating to obtain the one-way transmission time delay from the slave clock to the master clock according to the second local clock and the second master clock;
calculating to obtain the average time delay of the one-way transmission according to the one-way transmission time delay from the master clock to the slave clock and the one-way transmission time delay from the slave clock to the master clock;
controlling the field programmable gate array to stop counting;
acquiring a count value of the field programmable gate array;
controlling the field programmable gate array to count to a specified value according to the clock frequency of the reference time source of the field programmable gate array according to the one-way transmission average time delay, the second master clock and the count value; the controlling the field programmable gate array to count to a specified value according to the clock frequency of the reference time source of the field programmable gate array according to the one-way transmission average delay, the second master clock and the count value comprises: calculating a counting starting point of the field programmable gate array; the calculation formula of the counting starting point is the second master clock, the average time delay of the unidirectional transmission and the counting value; controlling the field programmable gate array to start counting from the counting starting point according to the clock frequency of the reference time source of the field programmable gate array and count to a specified value;
and controlling the field programmable logic gate array to output a 1pps signal.
2. The clock synchronization method of claim 1,
the obtaining of the first local clock when the first received packet is received includes:
receiving a first protocol packet sent from a physical layer chip through a precision time synchronization protocol, wherein the first protocol packet comprises the first local clock;
the obtaining of the second local clock when the second packet is sent includes:
receiving a second protocol packet sent from a physical layer chip through a precision time synchronization protocol, wherein the second protocol packet comprises the second local clock;
the obtaining of the second master clock when the master clock receives the second packet includes:
and receiving a third message sent by the master clock, wherein the third message carries a second master clock when the master clock receives the second message.
3. The clock synchronization method of claim 1, wherein the reference time source comprises an oven controlled crystal oscillator;
the clock synchronization method further comprises:
and performing frequency compensation according to the first master clock, the first local clock, a third master clock carried by the master clock when the master clock sends the first message next time, and a third local clock when the master clock receives the first message sent by the master clock next time.
4. The clock synchronization method of claim 1, wherein the reference time source comprises a common crystal oscillator;
the clock synchronization method further comprises:
frequency compensation is performed by adjusting the voltage.
5. A clock synchronization apparatus, comprising:
the first obtaining unit is used for obtaining a first local clock when the first message is received; the first message is sent by a master clock of a clock server, and the first message carries a first master clock when the master clock sends the first message; the clock server is a clock server which locks a global positioning satellite system;
the first calculation unit is used for calculating the one-way transmission time delay from the master clock to the slave clock according to the first local clock and the first master clock;
an interrupt generation unit for generating an interrupt;
the first counting unit is used for controlling the field programmable logic gate array to start counting;
a judging unit for judging whether the interrupt is overtime;
the first sending unit is used for sending a second message to the master clock when the judging unit judges that the interruption is overtime;
a second obtaining unit, configured to obtain a second local clock when the second packet is sent;
a third obtaining unit, configured to obtain a second master clock when the master clock receives the second packet;
the second calculation unit is used for calculating the one-way transmission time delay from the slave clock to the master clock according to the second local clock and the second master clock;
the third calculating unit is used for calculating to obtain the average time delay of the unidirectional transmission according to the unidirectional transmission time delay from the master clock to the slave clock and the unidirectional transmission time delay from the slave clock to the master clock;
the second counting unit is used for controlling the field programmable logic gate array to stop counting;
the fourth acquisition unit is used for acquiring the count value of the field programmable logic gate array;
the third counting unit is used for controlling the field programmable gate array to count to a specified value according to the clock frequency of the reference time source of the field programmable gate array according to the unidirectional transmission average time delay, the second master clock and the counting value; the third counting unit includes: the fourth calculation unit is used for calculating the counting starting point of the field programmable logic gate array; the calculation formula of the counting starting point is the second master clock, the average time delay of the unidirectional transmission and the counting value; the counting subunit is used for controlling the field programmable logic gate array to count from the counting starting point according to the clock frequency of the reference time source of the field programmable logic gate array and count to a specified value;
and the signal output unit is used for controlling the field programmable logic gate array to output a 1pps signal.
6. The clock synchronization apparatus of claim 5,
the first acquisition unit includes:
the first acquiring subunit is configured to receive, through a precision time synchronization protocol, a first protocol packet sent from a physical layer chip, where the first protocol packet includes the first local clock;
the second acquisition unit includes:
the second acquiring subunit is configured to receive, through a precision time synchronization protocol, a second protocol packet sent from a physical layer chip, where the second protocol packet includes the second local clock;
the third acquisition unit includes:
a third obtaining subunit, configured to receive a third packet sent by the master clock, where the third packet carries a second master clock when the master clock receives the second packet.
7. The clock synchronization apparatus of claim 5, wherein when the reference time source comprises an oven controlled crystal oscillator, further comprising:
and the first frequency compensation unit is used for carrying out frequency compensation according to the first master clock, the first local clock and a third master clock carried by the master clock when the master clock sends a first message next time and the third local clock when the first acquisition unit acquires the received first message sent by the master clock next time.
8. The clock synchronization apparatus of claim 5, wherein when the reference time source comprises a common crystal oscillator, further comprising:
and the second frequency compensation unit is used for carrying out frequency compensation through voltage adjustment.
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| CN111867045B (en) * | 2020-06-19 | 2022-07-26 | 联想(北京)有限公司 | Method, device and system for clock synchronization between cells |
| CN112462717B (en) * | 2020-12-03 | 2021-11-30 | 摩通传动与控制(深圳)有限公司 | High-precision multi-axis clock synchronization method based on EtherCAT |
| CN112702783B (en) * | 2020-12-21 | 2022-09-09 | 四川吉赛特科技有限公司 | Auxiliary time service method applied to node station |
| CN114095109A (en) * | 2021-11-17 | 2022-02-25 | 深圳市领创星通科技有限公司 | Clock synchronization method, device, equipment and storage medium |
| CN114339984A (en) * | 2021-12-31 | 2022-04-12 | 中国联合网络通信集团有限公司 | Method, device and equipment for calibrating time precision of bearer network and storage medium |
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