CN106572528A - Clock synchronization method and device - Google Patents
Clock synchronization method and device Download PDFInfo
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- CN106572528A CN106572528A CN201610911167.2A CN201610911167A CN106572528A CN 106572528 A CN106572528 A CN 106572528A CN 201610911167 A CN201610911167 A CN 201610911167A CN 106572528 A CN106572528 A CN 106572528A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
Abstract
The invention provides a clock synchronization method and device, and the method comprises the steps: calculating and obtaining unidirectional transmission mean time delay through first main clock time, second local clock time, second local clock time and second main clock time; obtaining a count value through controlling a field-programmable gate array to start and stop counting; controlling the field-programmable gate array to output a 1pps signal according to the unidirectional transmission mean time delay, the second main clock time and the count value when a specific value is counted according to the clock frequency of a reference time source, thereby achieving the synchronization of a slave clock and a main clock. Because a time server is employed in the scheme, the method does not need a GPS antenna and corresponding indoor forwarding equipment, is lower in cost, can avoid a problem of weather impact, and solves problems of high cost and weather cost caused by the application of the GPS antenna and the corresponding indoor forwarding equipment during the synchronization of a control base station time and the time of the GPS in the prior art.
Description
Technical field
The present invention relates to the communications field, in particular, is related to a kind of clock synchronizing method and device.
Background technology
The communication standard of Most current TDD TDD duplex modes, such as TD SDMA TD-
, all there is the strict demand to frequency/time synchronized, often need in SCDMA, CDMA2000, worldwide interoperability for microwave accesses WiMAX etc.
The whole network is wanted between eating dishes without rice or wine, to keep accurate time synchronized.
GPS (GPS) is the optimum selection of the timing reference input for realizing time synchronized.GPS be one by
24 antenna navigation system around the satellite composition of earth operating, its advantage is Global coverage, and system clock accuracy is high, long
Phase good stability.At present, essentially all of existing network equipment all uses gps clock scheme, by installing GPS letters in each base station
Number reception device, receives the clock signal that satellite sends, then sends base station to and realize time synchronized.
Gps signal reception device includes gps antenna and corresponding interior forwarding unit, relatively costly, and easily receives
To the impact of weather, step-out between system base-station can be caused in harsh climate, increase cutting off rate.
Therefore, need badly it is a kind of in the time synchronized of control base station time and GPS, reduces cost with
And reduce the clock synchronizing method that weather affects.
The content of the invention
In view of this, the present invention provides a kind of clock synchronizing method and device, to solve in control base station time and the whole world
During the time synchronized of global position system, the high expensive that caused using gps antenna and corresponding interior forwarding unit and
The problem for easily being affected by weather.
To solve above-mentioned technical problem, following technical scheme is present invention employs：
A kind of clock synchronizing method, including：
Obtain the first local clock during the first message for receiving；First message is by the master clock of clock server
Send, and in first message, carry the first master clock when the master clock sends first message；The clock
Server is the clock server for having locked GPS；
Master clock is calculated to the one-way transmission from clock according to first local clock and first master clock
Time delay；
Produce interruption；
Control field programmable gate array is started counting up；
Judge whether interruption is overtime；
Judge interrupt time-out, the second message is sent to the master clock；
Obtain the second local clock during second message for sending；
Obtain the second master clock when the master clock receives second message；
One-way transmission from clock to master clock is calculated according to second local clock and second master clock
Time delay；
During according to the master clock to the unidirectional transmission time delay from clock and the one-way transmission from clock to master clock
Prolong, be calculated one-way transmission average delay；
Control the field programmable gate array to stop counting；
Obtain the count value of the field programmable gate array；
According to the one-way transmission average delay, second master clock and the count value, controlling the scene can compile
Journey logic gate array count down to specified numerical value according to the clock frequency in source during its benchmark；
Control the field programmable gate array output 1pps signals.
Preferably,
The first local clock during the first message that the acquisition is received, including：
The first protocol package for sending is received from physical chip by accurate time synchronization protocol, is wrapped in first agreement
Containing first local clock；
The second local clock during second message that the acquisition sends, including：
The second protocol bag for sending is received from physical chip by accurate time synchronization protocol, is wrapped in the second protocol
Containing second local clock；
Second master clock obtained when the master clock receives second message, including：
The 3rd message that sent by the master clock of reception, the 3rd message carry the master clock and receive described the
The second master clock during two messages.
Preferably, during the benchmark, source includes constant-temperature crystal oscillator；
The clock synchronizing method also includes：
When sending the first message next time according to first master clock, first local clock, the master clock, take
The 3rd local clock during the first message that the 3rd master clock and the reception master clock of band is sent next time, enters line frequency
Compensation.
Preferably, during the benchmark, source includes ordinary crystal oscillators；
The clock synchronizing method also includes：
Frequency compensation is carried out by adjusting voltage.
Preferably, it is described according to the one-way transmission average delay, second master clock and the count value, control institute
State field programmable gate array and specified numerical value is count down to according to the clock frequency in source during its benchmark, including：
Calculate the counting starting point of the field programmable gate array；The computing formula for counting starting point is described the
Two master clocks-one-way transmission the average delay+count value；
Control the field programmable gate array to be opened from the counting starting point according to the clock frequency in source during its benchmark
Begin to count, count down to specified numerical value.
A kind of clock synchronization apparatus, including：
First acquisition unit, for obtaining the first local clock during the first message for receiving；First message be by
The master clock of clock server sends, and carry in first message when master clock sends first message the
One master clock；The clock server is the clock server for having locked GPS；
First computing unit, for being calculated master clock and arriving according to first local clock and first master clock
From the unidirectional transmission time delay of clock；
Interrupt generating unit, for producing interruption；
First counting unit, starts counting up for controlling field programmable gate array；
Judging unit, for judging whether interruption is overtime；
First transmitting element, for judging interrupt time-out when the judging unit, send the second message to it is described main when
Clock；
Second acquisition unit, for obtaining the second local clock during second message for sending；
3rd acquiring unit, for obtaining the second master clock when the master clock receives second message；
Second computing unit, for according to second local clock and second master clock be calculated from clock to
The unidirectional transmission time delay of master clock；
3rd computing unit, for according to the master clock to the unidirectional transmission time delay from clock and described from clock to master
The unidirectional transmission time delay of clock, is calculated one-way transmission average delay；
Second counting unit, stops counting for controlling the field programmable gate array；
4th acquiring unit, for obtaining the count value of the field programmable gate array；
3rd counting unit, for according to the one-way transmission average delay, second master clock and the count value,
Control the field programmable gate array and specified numerical value is count down to according to the clock frequency in source during its benchmark；
Signal output unit, for controlling the field programmable gate array output 1pps signals.
Preferably,
The first acquisition unit includes：
First obtains subelement, for receiving from physical chip the first agreement for sending by accurate time synchronization protocol
Bag, includes first local clock in first agreement；
The second acquisition unit includes：
Second obtains subelement, for receiving from physical chip the second protocol for sending by accurate time synchronization protocol
Bag, includes second local clock in the second protocol；
3rd acquiring unit includes：
3rd obtains subelement, and for receiving the 3rd message sent by the master clock, the 3rd message is carried
The master clock receives the second master clock during second message.
Preferably, when when the benchmark, source includes constant-temperature crystal oscillator, also include：
First frequency compensating unit, for according under first master clock, first local clock, the master clock
When once sending the first message, the 3rd master clock of carrying and the first acquisition unit are obtained under the master clock for receiving
The 3rd local clock during the first message for once sending, carries out frequency compensation.
Preferably, when when benchmark, source includes ordinary crystal oscillators, also include：
Second frequency compensating unit, carries out frequency compensation for by adjusting voltage.
Preferably, the 3rd counting unit includes：
4th computing unit, for calculating the counting starting point of the field programmable gate array；The counting starting point
Computing formula be the second master clock-one-way transmission average delay+count value；
Count sub-element, based on controlling clock frequency of the field programmable gate array according to source during its benchmark
Number is started counting up from the counting starting point, count down to specified numerical value.
Compared to prior art, the invention has the advantages that：
The invention provides a kind of clock synchronizing method and device, during by the first master clock time, the first local clock
Between, the second local clock time and the second master clock time be calculated one-way transmission average delay, can be compiled by control scene
Journey logic gate array is started counting up and stopping counts to get count value, according to the one-way transmission average delay, the second master clock
Time and the count value, control the field programmable gate array and count down to finger according to the clock frequency in source during its benchmark
After fixed number value, 1pps signals are exported, can be accomplished synchronous with master clock time from clock.As this programme uses the time
Server, it is not necessary to set up gps antenna and install corresponding interior forwarding unit, cost is relatively low, is also not in by weather
The problem of impact, solves in prior art in the time synchronized of control base station time and GPS, uses
Gps antenna and corresponding interior forwarding unit and the high expensive that causes and the problem for easily being affected by weather.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
Accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Inventive embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can be with basis
The accompanying drawing of offer obtains other accompanying drawings.
The method flow diagram of the clock synchronizing method that Fig. 1 is provided for the present invention；
Fig. 2 is the flow chart of master clock and the message interaction process from clock；
The structural representation of the clock synchronization apparatus that Fig. 3 is provided for the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The invention provides a kind of clock synchronizing method, reference Fig. 1, including：
The first local clock during the first message that S101, acquisition are received；
Wherein, the first message is sent by the master clock of clock server, and master clock transmission is carried in the first message
The first master clock during the first message.
It should be noted that master clock and can be single step transmission, or the transmission of double steps from clock transfer, when for singly
When walking transmission, the first message is Sync messages, and the first master clock is carried in Sync messages, when transmitting for double steps, the first report
Text is Follow_up messages, and master clock sends Sync messages first, after Sync messages send, sends Follow_up reports
Text, i.e. the first message, carry the first master clock in Follow_up messages.
Optionally, in another embodiment of the present invention, the first local clock during the first message for receiving is obtained, including：
The first protocol package for sending is received from physical chip by accurate time synchronization protocol, is included in the first agreement
First local clock.
Specifically, when base station receives the first message of master clock transmission, local crystal oscillator clock is produced by physical chip
Clock count, i.e. the first local clock got to the expanding location in the first protocol package, that is, beaten the time by the first local clock
Stamp, the first protocol package is sent by accurate time synchronization protocol to the accurate clock synchronization protocol PTP protocol of central processing unit
Processing module.
S102, when master clock is calculated according to the first local clock and the first master clock to one-way transmission from clock
Prolong.
Master clock to the computational methods of the one-way transmission delays from clock is：
Master clock to the-the first master clock of one-way transmission delays=the first local clock from clock, specifically, when calculating main
Clock to the one-way transmission delays from clock module be PTP protocol processing module.
S103, generation interruption；
Specifically, PTP protocol processing module control produces interruption.
S104, control field programmable gate array are started counting up；
Have no progeny in the control of PTP protocol processing module is produced, start control field programmable gate array and start from scratch
Count.
S105, judge to interrupt whether time-out；When interrupt time-out is judged, S106 is performed；
Specifically, PTP protocol processing module was had no progeny in control is produced already provided with a break period, and judgement is
It is no to reach the break period, when the break period is reached, it was demonstrated that interrupt time-out.
S106, the second message of transmission are to master clock；
Specifically, when time-out is judged, now PTP protocol processing module makes labelling, and calls and be registered to network-driven
The call back function of program sends the second message, wherein, the second message is delay_req messages.
The second local clock during the second message that S107, acquisition send；
Optionally, in another embodiment of the present invention, the second local clock during the second message for sending is obtained, including：
The second protocol bag for sending is received from physical chip by accurate time synchronization protocol, is included in second protocol
Second local clock.
Specifically, the mode for obtaining the second local clock is the same with the mode for obtaining the first local clock, when transmission second
During message, the second local clock is beaten by the clock count that local crystal oscillator clock is produced by physical chip, i.e. the second local clock
To the expanding location of second protocol bag, sent to PTP protocol processing module by accurate time synchronization protocol.
S108, obtain the second master clock when master clock receives the second message；
Optionally, in another embodiment of the present invention, acquisition master clock receives the second master clock during the second message, bag
Include：
The 3rd message sent by master clock is received, the 3rd message carries second when master clock receives the second message and leads
Clock.
Specifically, after master clock receives the second message, the 3rd message is sent extremely from clock, when the 3rd message carries main
Clock receives the second master clock during the second message.Wherein, the 3rd message refers to Delay_resp messages.
S109, when being calculated the one-way transmission from clock to master clock according to the second local clock and the second master clock
Prolong；
Specifically, the computing formula of the unidirectional transmission time delay from clock to master clock is：
The-the second local clock of unidirectional transmission time delay=the second master clock from clock to master clock.Specifically, calculate from when
Clock is to the PTP protocol processing module that the module of the unidirectional transmission time delay of master clock is central processing unit.
S110, the unidirectional transmission time delay according to master clock to the unidirectional transmission time delay from clock and from clock to master clock,
It is calculated one-way transmission average delay；
Specifically, time of the master clock to the unidirectional transmission time delay from clock=one-way transmission average delay+master-salve clock
Deviation.
The time deviation of the unidirectional transmission time delay from clock to master clock=one-way transmission average delay-master-salve clock.
According to above-mentioned two formula, derive that the computing formula of one-way transmission average delay is：
One-way transmission average delay=(master clock to the unidirectional transmission time delay from clock+unidirectional from clock to master clock
Propagation delay time)/2.
S111, control field programmable gate array stop counting；
After PTP protocol processing module is calculated one-way transmission average delay, field programmable gate array is controlled
Stop counting.
S112, the count value for obtaining field programmable gate array；
Specifically, when the count value of field programmable gate array stops for control field programmable gate array,
The numerical value of the counting of field programmable gate array.
S113, according to one-way transmission average delay, the second master clock and count value, control field programmable gate array
Specified numerical value is count down to according to the clock frequency in source during its benchmark；
Optionally, in another embodiment of the present invention, according to one-way transmission average delay, the second master clock and count value,
Control field programmable gate array count down to specified numerical value according to the clock frequency in source during its benchmark, including：
Calculate the counting starting point of field programmable gate array；The computing formula for counting starting point is the second master clock-mono-
To transmission average delay+count value；
Control field programmable gate array is started counting up from starting point is counted according to the clock frequency in source during its benchmark, is counted
Count to specified numerical value.
It should be noted that the computing formula for counting starting point can also be that first the+the three master clock-the first of master clock is local
Clock+one-way transmission average delay+count value；
Wherein, first+the three the-the first local clock of master clock of master clock+one-way transmission average delay+count value and second
Master clock-one-way transmission average delay+count value is equivalent, as the time of master clock is accurate, so the meter chosen
The computing formula of several starting points of calculating is the second master clock-one-way transmission average delay+count value.
S114, control field programmable gate array output 1pps signals.
Specifically, after counting out counting starting point, PTP protocol processing module controls field programmable gate array according to which
During benchmark, the clock frequency in source is started counting up from starting point is counted, and after counting down to specified numerical value, exports 1pps signals.
A kind of clock synchronizing method is embodiments provided, during by the first master clock time, the first local clock
Between, the second local clock time and the second master clock time be calculated one-way transmission average delay, can be compiled by control scene
Journey logic gate array is started counting up and stopping counts to get count value, according to one-way transmission average delay, the second master clock time
And count value, control field programmable gate array is count down to after specified numerical value according to the clock frequency in source during its benchmark, defeated
Go out 1pps signals, can accomplish synchronous with master clock time from clock.As this programme uses time server, it is not required to
Gps antenna to be set up and the corresponding interior forwarding unit of installation, cost are relatively low, are also not in the problem affected by weather,
Solve in prior art in the time synchronized of control base station time and GPS, using gps antenna and
Corresponding interior forwarding unit and the high expensive that causes and the problem for easily being affected by weather.
Optionally, in another embodiment of the present invention, during benchmark, source is constant-temperature crystal oscillator；
Clock synchronizing method also includes：
When sending the first message next time according to the first master clock, the first local clock, master clock, the 3rd of carrying the it is main when
The 3rd local clock during the first message that clock and reception master clock are sent next time, carries out frequency compensation.
Specifically, when benchmark, source includes constant-temperature crystal oscillator, and the precision of constant-temperature crystal oscillator is higher, master clock and
From the frequency difference very little of clock, now in order to reduce frequency difference, frequency compensated method can be adopted, specifically, according to
When first master clock, the first local clock, master clock send the first message next time, the 3rd master clock of carrying and reception are led
The 3rd local clock during the first message that clock is sent next time, carries out frequency compensation.It should be noted that due to master clock
With the frequency difference very little from clock, frequency compensation is not now carried out also possible.
Specifically, master clock and be constantly to repeat from the message transmissions between clock, the first message that master clock sends
In carry the first master clock, carry the 3rd master clock in the first message of the next one that master clock sends, receive from clock and lead
Clock send the first message of the next one when, obtain the 3rd local clock, according to the first master clock, the first local clock, the 3rd
Master clock and the 3rd local clock calculate frequency deviation.
The computing formula of frequency deviation is：
Frequency deviation=(the 3rd the-the first master clock of master clock)/(the 3rd the-the first local clock of local clock).
After being calculated frequency deviation, one-way transmission average delay is compensated, i.e., with frequency deviation * (T2-T3) come
Replace (T2-T3).
In the present embodiment, when when benchmark, source includes constant-temperature crystal oscillator, by calculating frequency deviation pair
Frequency is compensated, and can reduce master clock with the frequency difference from clock.
Optionally, in another embodiment of the present invention, during benchmark, source includes ordinary crystal oscillators；
Clock synchronizing method also includes：
Frequency compensation is carried out by adjusting voltage.
Specifically, when when benchmark, source includes ordinary crystal oscillators, due to the low precision of ordinary crystal oscillators, cause
Master clock is larger with the frequency difference from clock, now by adjusting the method for voltage carrying out frequency compensation.
In the present embodiment, when source includes ordinary crystal oscillators when benchmark, frequency compensation, energy are carried out by adjusting voltage
Enough reduce master clock with the frequency difference from clock.
Master clock is understood with the message interaction mistake from clock in order to what those skilled in the art can become more apparent
Journey, explains in conjunction with Fig. 2.
S201, the first message of transmission；
Specifically, master clock sends the first message to from clock, when master clock and when between clock being single step transmission, the
One message is Sync messages, and when master clock and when between clock being double step transmission, the first message is Follow_up messages, is had
Body is explained and refers to described above.
The first local clock during the first message that S202, acquisition are received；
Receive after the first message from clock, it is local that PTP protocol processing module acquires first from physical chip
Clock.PTP protocol processing module is calculated master clock to from the unidirectional of clock according to the first local clock and the first master clock
Propagation delay time.
S203, the second message of transmission；
Specifically, when PTP protocol processing module judges interrupt time-out, the second message is sent to master clock from clock.
The second local clock during the second message that S204, acquisition send；
Specifically, PTP protocol processing module acquires the second local clock from physical chip.
S205, the 3rd message of transmission；
It should be noted that the second master clock when master clock receives the second message is carried in the 3rd message.
Now, PTP protocol processing module according to the second master clock and the second local clock be calculated from clock to it is main when
The unidirectional transmission time delay of clock.
This embodiment describes master clock and from the message interaction process between clock, can be by mutual transmitting message
The temporal information of carrying is calculated one-way transmission of the master clock to the unidirectional transmission time delay from clock and from clock to master clock
Time delay.
Optionally, a kind of clock synchronization apparatus are provided in another embodiment of the present invention, with reference to Fig. 3, including：
First acquisition unit 101, for obtaining the first local clock during the first message for receiving；First message be by when
The master clock of clock server sends, and the first master clock when master clock sends the first message is carried in the first message；Clock
Server is the clock server for having locked GPS；
First computing unit 102, for according to the first local clock and the first master clock be calculated master clock to from when
The unidirectional transmission time delay of clock；
Interrupt generating unit 103, for producing interruption；
First counting unit 104, starts counting up for controlling field programmable gate array；
Judging unit 105, for judging whether interruption is overtime；
First transmitting element 106, for judging interrupt time-out when judging unit 105, sends the second message to master clock；
Second acquisition unit 107, for obtaining the second local clock during the second message for sending；
3rd acquiring unit 108, for obtaining the second master clock when master clock receives the second message；
Second computing unit 109, for according to the second local clock and the second master clock be calculated from clock to it is main when
The unidirectional transmission time delay of clock；
3rd computing unit 110, for according to master clock to the unidirectional transmission time delay from clock and from clock to master clock
Unidirectional transmission time delay, be calculated one-way transmission average delay；
Second counting unit 111, stops counting for controlling field programmable gate array；
4th acquiring unit 112, for obtaining the count value of field programmable gate array；
3rd counting unit 113, for according to one-way transmission average delay, the second master clock and count value, control scene
Programmable gate array count down to specified numerical value according to the clock frequency in source during its benchmark；
Signal output unit 114, for controlling field programmable gate array output 1pps signals.
Optionally, in another embodiment of the present invention, first acquisition unit 101 includes：
First obtains subelement, for receiving from physical chip the first agreement for sending by accurate time synchronization protocol
Bag, includes the first local clock in the first agreement.
Optionally, in another embodiment of the present invention, second acquisition unit 107 includes：
Second obtains subelement, for receiving from physical chip the second protocol for sending by accurate time synchronization protocol
Bag, includes the second local clock in second protocol.
Optionally, in another embodiment of the present invention, the 3rd acquiring unit 108 includes：
3rd obtains subelement, and for receiving the 3rd message sent by master clock, the 3rd message carries master clock receipts
To the second master clock during the second message.
Optionally, in another embodiment of the present invention, the 3rd counting unit 113 includes：
4th computing unit, for calculating the counting starting point of field programmable gate array；The calculating for counting starting point is public
Formula is the second master clock-one-way transmission average delay+count value；
Count sub-element, for control field programmable gate array according to during its benchmark source clock frequency count from
Count starting point to start counting up, count down to specified numerical value.
In the present embodiment, by the first master clock time, the first local clock time, the second local clock time and second
Master clock time is calculated one-way transmission average delay, is started counting up and is stopped by control field programmable gate array
Count value is counted to get, according to one-way transmission average delay, the second master clock time and count value, field programmable logic is controlled
Gate array is count down to after specified numerical value according to the clock frequency in source during its benchmark, export 1pps signals, can accomplish from clock with
The synchronization of master clock time.As this programme uses time server, it is not necessary to set up gps antenna and install corresponding
Indoor forwarding unit, cost are relatively low, are also not in the problem affected by weather, solve in prior art in control base station
Between and during GPS time synchronized, the cost caused using gps antenna and corresponding interior forwarding unit
The higher and easy problem affected by weather.
It should be noted that in the present embodiment unit the course of work, refer to the content in above-described embodiment,
This repeats no more.
Optionally, in another embodiment of the present invention, when when benchmark, source includes constant-temperature crystal oscillator, also include：
First frequency compensating unit, for sending first according to the first master clock, the first local clock, master clock next time
During message, the 3rd master clock of carrying and first acquisition unit 101 obtain the first report that the master clock for receiving is sent next time
The 3rd local clock when literary, carries out frequency compensation.
When benchmark, source includes ordinary crystal oscillators, also include：
Second frequency compensating unit, carries out frequency compensation for by adjusting voltage.
In the present embodiment, frequency compensation is carried out, master clock can be reduced with the frequency difference from clock.
It should be noted that in the present embodiment unit the course of work, refer to the content in above-described embodiment,
This repeats no more.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
Various modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized without departing from the spirit or scope of the present invention in other embodiments.Therefore, the present invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope for causing.
Claims (10)
1. a kind of clock synchronizing method, it is characterised in that include：
Obtain the first local clock during the first message for receiving；First message is sent out by the master clock of clock server
Send, and in first message, carry the first master clock when the master clock sends first message；The clock clothes
Business device is the clock server for having locked GPS；
Master clock is calculated to the unidirectional transmission time delay from clock according to first local clock and first master clock；
Produce interruption；
Control field programmable gate array is started counting up；
Judge whether interruption is overtime；
Judge interrupt time-out, the second message is sent to the master clock；
Obtain the second local clock during second message for sending；
Obtain the second master clock when the master clock receives second message；
Unidirectional transmission time delay from clock to master clock is calculated according to second local clock and second master clock；
According to the master clock to the unidirectional transmission time delay from clock and the unidirectional transmission time delay from clock to master clock, meter
Calculation obtains one-way transmission average delay；
Control the field programmable gate array to stop counting；
Obtain the count value of the field programmable gate array；
According to the one-way transmission average delay, second master clock and the count value, control the field-programmable and patrol
Collect gate array and specified numerical value is count down to according to the clock frequency in source during its benchmark；
Control the field programmable gate array output 1pps signals.
2. clock synchronizing method according to claim 1, it is characterised in that
The first local clock during the first message that the acquisition is received, including：
The first protocol package for sending is received from physical chip by accurate time synchronization protocol, is included in first agreement
First local clock；
The second local clock during second message that the acquisition sends, including：
The second protocol bag for sending is received from physical chip by accurate time synchronization protocol, is included in the second protocol
Second local clock；
Second master clock obtained when the master clock receives second message, including：
The 3rd message that reception is sent by the master clock, the 3rd message carry the master clock and receive second report
The second master clock when literary.
3. clock synchronizing method according to claim 1, it is characterised in that source includes that constant temperature crystal vibrates during the benchmark
Device；
The clock synchronizing method also includes：
When sending the first message next time according to first master clock, first local clock, the master clock, carrying
The 3rd local clock during the first message that the 3rd master clock and the reception master clock are sent next time, enters line frequency benefit
Repay.
4. clock synchronizing method according to claim 1, it is characterised in that source includes that common crystal vibrates during the benchmark
Device；
The clock synchronizing method also includes：
Frequency compensation is carried out by adjusting voltage.
5. clock synchronizing method according to claim 1, it is characterised in that described according to the one-way transmission mean time
Prolong, second master clock and the count value, control the field programmable gate array according to during its benchmark source when
Clock frequency counting to specified numerical value, including：
Calculate the counting starting point of the field programmable gate array；The computing formula for counting starting point is the described second master
Clock-one-way transmission the average delay+count value；
Control the field programmable gate array and meter is started from the counting starting point according to the clock frequency in source during its benchmark
Number, count down to specified numerical value.
6. a kind of clock synchronization apparatus, it is characterised in that include：
First acquisition unit, for obtaining the first local clock during the first message for receiving；First message is by clock
The master clock of server sends, and first when master clock transmission first message is carried in first message is led
Clock；The clock server is the clock server for having locked GPS；
First computing unit, for according to first local clock and first master clock be calculated master clock to from when
The unidirectional transmission time delay of clock；
Interrupt generating unit, for producing interruption；
First counting unit, starts counting up for controlling field programmable gate array；
Judging unit, for judging whether interruption is overtime；
First transmitting element, for judging interrupt time-out when the judging unit, sends the second message to the master clock；
Second acquisition unit, for obtaining the second local clock during second message for sending；
3rd acquiring unit, for obtaining the second master clock when the master clock receives second message；
Second computing unit, for according to second local clock and second master clock be calculated from clock to it is main when
The unidirectional transmission time delay of clock；
3rd computing unit, for according to the master clock to the unidirectional transmission time delay from clock and described from clock to master clock
Unidirectional transmission time delay, be calculated one-way transmission average delay；
Second counting unit, stops counting for controlling the field programmable gate array；
4th acquiring unit, for obtaining the count value of the field programmable gate array；
3rd counting unit, for according to the one-way transmission average delay, second master clock and the count value, control
The field programmable gate array count down to specified numerical value according to the clock frequency in source during its benchmark；
Signal output unit, for controlling the field programmable gate array output 1pps signals.
7. clock synchronization apparatus according to claim 6, it is characterised in that
The first acquisition unit includes：
First obtains subelement, for receiving from physical chip the first protocol package for sending by accurate time synchronization protocol,
Include first local clock in first agreement；
The second acquisition unit includes：
Second obtains subelement, for receiving from physical chip the second protocol bag for sending by accurate time synchronization protocol,
Include second local clock in the second protocol；
3rd acquiring unit includes：
3rd obtains subelement, and for receiving the 3rd message sent by the master clock, the 3rd message carries described
Master clock receives the second master clock during second message.
8. clock synchronization apparatus according to claim 6, it is characterised in that source includes that constant temperature crystal shakes when the benchmark
When swinging device, also include：
First frequency compensating unit, for according to first master clock, first local clock, the master clock next time
When sending the first message, the 3rd master clock of carrying and the first acquisition unit obtain the master clock for receiving next time
The 3rd local clock during the first message for sending, carries out frequency compensation.
9. clock synchronization apparatus according to claim 6, it is characterised in that source includes ordinary crystal oscillators when benchmark
When, also include：
Second frequency compensating unit, carries out frequency compensation for by adjusting voltage.
10. clock synchronization apparatus according to claim 6, it is characterised in that the 3rd counting unit includes：
4th computing unit, for calculating the counting starting point of the field programmable gate array；The meter for counting starting point
Calculation formula is the second master clock-one-way transmission average delay+count value；
Count sub-element, for control the field programmable gate array according to during its benchmark source clock frequency count from
The counting starting point is started counting up, and count down to specified numerical value.
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| CN111867045A (en) * | 2020-06-19 | 2020-10-30 | 联想(北京)有限公司 | Method, device and system for clock synchronization between cells |
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| CN114095109A (en) * | 2021-11-17 | 2022-02-25 | 深圳市领创星通科技有限公司 | Clock synchronization method, device, equipment and storage medium |
| CN114339984A (en) * | 2021-12-31 | 2022-04-12 | 中国联合网络通信集团有限公司 | Method, device and equipment for calibrating time precision of bearer network and storage medium |
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