CN106571337B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents

Semiconductor device, manufacturing method thereof and electronic device Download PDF

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CN106571337B
CN106571337B CN201510669891.4A CN201510669891A CN106571337B CN 106571337 B CN106571337 B CN 106571337B CN 201510669891 A CN201510669891 A CN 201510669891A CN 106571337 B CN106571337 B CN 106571337B
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oxide layer
layer
region
semiconductor substrate
isolation structure
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CN106571337A (en
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禹国宾
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

The invention provides a manufacturing method of a semiconductor device, the semiconductor device and an electronic device, wherein the manufacturing method comprises the following steps: providing a semiconductor substrate, and forming an isolation structure on the semiconductor substrate, wherein the isolation structure divides the semiconductor substrate into an I/O (input/output) area and a core area; forming a dummy oxide layer on the semiconductor substrate; removing the virtual oxide layer on the I/O area; forming a nitride layer on the I/O region; oxidizing the nitride layer to form a first gate oxide layer; and removing the virtual oxide layer of the kernel region, and forming a second grid oxide layer on the kernel region. According to the manufacturing method of the semiconductor device, on one hand, the I/O which is less affected by interface nitrogen continues to use silicon oxynitride as an interface layer to obtain a good equivalent oxide layer thickness, and on the other hand, in the core region which is more affected by the interface nitrogen, silicon oxide is used as the interface layer, so that the influence of the interface nitrogen is overcome, and the performance of the semiconductor device/integrated circuit is improved.

Description

Semiconductor device, manufacturing method thereof and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
With the development of semiconductor technology, the geometric dimensions of large-scale integrated circuit CMOS (complementary metal oxide) devices are continuously shrinking, the feature sizes of semiconductor devices are shrinking to nanometer level, and the conventional SiO devices are2Have been unsuitable for use as gate oxide layers, various improved techniques have been proposed, one of which is the use of SiON as an interfacial layer. For high performance logic circuit with 45nm node, the Equivalent Oxide Thickness (EOT) is required to be less than 0.7nm, and the gate leakage current is required to be less thanA gate dielectric film having good properties. For technology nodes of 32nm and below, the SiON film used as the interface layer under the high-K metal gate has a thickness of less than 1nm, and nitrogen is concentrated at the film-substrate interface, which is negative in the pair of ultra-thin SiON filmsBias temperature instability has an effect.
For the requirement of device shrinking, the SiON film is a key process for gate oxide thickness shrinking, and stress engineering is introduced at the technical node of 28nm and below. However, for ultra-thin gate oxides, especially core gate oxides, the presence of interfacial nitrogen can lead to reduced bias temperature stability (BTI Fail) and reduced device performance due to their thin thickness.
Therefore, it is necessary to provide a new manufacturing method to solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, and forming an isolation structure on the semiconductor substrate, wherein the isolation structure divides the semiconductor substrate into an I/O (input/output) area and a core area; forming a dummy oxide layer on the semiconductor substrate; removing the virtual oxide layer on the I/O area; forming a nitride layer on the I/O region; oxidizing the nitride layer to form a first gate oxide layer; and removing the virtual oxide layer of the kernel region, and forming a second grid oxide layer on the kernel region.
Further, a nitride layer is formed on the I/O region by a low energy plasma nitridation process.
Further, the nitride layer is a silicon nitride layer.
Further, the thickness of the first gate oxide layer is larger than that of the second gate oxide layer.
In the manufacturing method of the semiconductor device, silicon oxynitride interface layers and silicon oxide interface layers are respectively formed in an I/O region and a core region of an integrated circuit in an advanced process, such as a technical node of 28nm or below, so that on one hand, I/O with small influence of interface nitrogen continues to use silicon oxynitride as an interface layer to obtain a good equivalent oxide layer thickness, and on the other hand, in the core region with large influence of interface nitrogen, silicon oxide is used as the interface layer, so that the influence of interface nitrogen is overcome, and the performance of the semiconductor device/the integrated circuit is improved.
Another aspect of the present invention provides a semiconductor device manufactured by the above method of the present invention, the semiconductor device comprising: the semiconductor device comprises a semiconductor substrate, wherein an isolation structure is formed on the semiconductor substrate, the isolation structure divides the semiconductor substrate into an I/O (input/output) area and a core area, a first grid oxide layer is formed on the I/O area, and a second grid oxide layer is formed on the core area.
Further, the first gate oxide layer is a silicon oxynitride layer, and the second gate oxide layer is a silicon oxide layer.
Further, the thickness of the first gate oxide layer is larger than that of the second gate oxide layer.
According to the semiconductor device, the silicon oxynitride interface layer and the silicon oxide interface layer are respectively formed in the I/O area and the core area of the integrated circuit, so that on one hand, the I/O with small influence of interface nitrogen continues to use the silicon oxynitride as the interface layer to obtain a good equivalent oxide layer thickness, and on the other hand, in the core area with large influence of the interface nitrogen, the silicon oxide is used as the interface layer, so that the influence of the interface nitrogen is overcome, and the performance of the semiconductor device/the integrated circuit is improved.
In another aspect, the present invention provides an electronic device including the semiconductor device provided by the present invention.
The electronic device provided by the invention has similar advantages due to the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a flow chart of steps of a method of fabrication according to an embodiment of the invention;
fig. 2A to 2F are schematic cross-sectional views of devices obtained by sequentially performing steps according to a manufacturing method of an embodiment of the present invention;
fig. 3 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
A method for manufacturing a semiconductor device of the present invention will be described in detail below with reference to fig. 1 and fig. 2A to 2F.
Firstly, step S101 is executed to provide a semiconductor substrate, and an isolation structure is formed on the semiconductor substrate, wherein the isolation structure divides the semiconductor substrate into an I/O region and a core region.
As shown in fig. 2A, a semiconductor substrate 200 is provided, on which an isolation structure 201 is formed, the isolation structure 201 dividing the semiconductor substrate into an I/O region and a core (core) region.
The semiconductor substrate 200 is a bulk silicon substrate, which may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like. Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure may be formed in the semiconductor substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, and in this embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon.
The isolation structure 201 may be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, and may be formed by an isolation structure forming method commonly used in the art. As an example, in the present implementation, the isolation structure 201 is a shallow trench isolation structure, which is formed by patterning and etching on the semiconductor substrate 200, such as forming a trench for forming the shallow trench isolation structure 201 by patterning and etching, and then forming the shallow trench isolation structure 201 by filling an isolation material into the trench. The etching process may be a dry etching process or a wet etching process, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. The isolation materials include, but are not limited to: undoped Silicon Glass (USG), silicon dioxide, silicon nitride, and the like. As an example, in the present embodiment, Undoped Silicon Glass (USG) is used as the isolation material of the isolation structure 201, which may be formed by a common deposition process such as CVD, and will not be described herein.
The isolation structure 201 divides the semiconductor substrate 200 into an I/O region and a Core (Core) region, and the left side region of the isolation structure 201 is a region for forming an I/O circuit portion and the right side is a region for Core (Core) circuits in this embodiment, as an example. It is to be understood that the same is by way of illustration only and is not intended as a limitation upon the present invention.
Next, step 102 is performed to form a dummy oxide layer on the semiconductor substrate.
As shown in fig. 2B, a dummy oxide layer 202 is formed on the semiconductor substrate 200. The dummy oxide layer 202 is an oxide layer that is subsequently removed. As an example, the dummy oxide layer 202 is made of silicon dioxide in the present embodiment. The dummy oxide layer 202 may be formed by a thermal oxidation process such as dry oxygen oxidation, wet oxygen oxidation, high pressure oxidation, or by a CVD process such as rapid thermal CVD, LPCVD, HDPCVD, or the like. The dummy oxide layer 202 may illustratively be
Then, step 103 is performed to remove the dummy oxide layer on the I/O region.
As shown in fig. 2C, the dummy oxide layer on the I/O area, i.e. the portion of the dummy oxide layer 202 on the left side of the isolation structure 201, is removed. The process may be removed by photolithography patterning and etching, that is, first forming a photoresist on the semiconductor substrate 200, then defining a photoresist image by exposure, development, etc., the photoresist image exposing a portion of the oxide layer 202 on the left side of the isolation structure 201, and then removing the dummy oxide layer on the I/O region by an etching process using the photoresist image as a mask. The etching process may be a wet etching process or a dry etching process. The dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. The source gases for the dry etch may include CF4, CHF3, or other fluorocarbon gases. As an example, in this embodiment, the etching is dry etching, and the process parameters of the dry etching include: the etching gas comprises CF4, CHF3, etc., the flow rate is 50 sccm-500 sccm, 10 sccm-100 sccm, and the pressure is 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents millimeter mercury column.
Next, step 104 is performed to form a nitride layer in the I/O region.
As shown in fig. 2D, a nitride layer 203 is formed in the I/O region. I.e. a nitride layer 203 is formed on the semiconductor substrate area made of the isolation structure 201. In this embodiment, a low-energy nitrogen plasma nitridation process is adopted, i.e., the implantation energy of the semiconductor in the I/O region is 2.0eV to 4.6eV and the dose is 1 × 10 eV at a process temperature of 300 deg.C to 800 deg.C14atoms/cm2～2×1016atoms/cm2The nitrogen plasma converts the surface layer of the semiconductor substrate 200 of the I/O region into silicon nitride, thereby forming a silicon nitride layer.
Next, step 105 is performed to oxidize the nitride layer to form a first gate oxide layer 204.
As shown in fig. 2E, the nitride layer 203 is oxidized to form a first gate oxide layer 204. As an example, the first gate oxide layer 204 is made of silicon dioxide in the present embodiment. The first gate oxide layer 204 may be formed by oxidizing the nitride layer 203 in an oxygen-containing ambient by a thermal oxidation process, such as dry oxygen oxidation, wet oxygen oxidation, high pressure oxidation, etc., to convert the silicon nitride to silicon oxynitride, such that the first gate oxide layer 204 is formed, and the exemplary first gate oxide layer 204 may be a silicon oxynitride
Then, step 106 is executed to remove the dummy oxide layer in the core region and form a second gate oxide layer on the core region.
As shown in fig. 2F, the dummy oxide layer in the core region is removed, and a second gate oxide layer 205 is formed on the core region. Namely, the dummy oxide layer 202 on the right side of the isolation structure 201 is removed, and a second gate oxide layer 205 is formed on the semiconductor substrate on the right side of the isolation structure.
The dummy oxide layer except the core region may be removed by photolithography patterning and etching, that is, first, a photoresist is formed on the semiconductor substrate 200, and then a photoresist image is defined by exposure, development, etc., the photoresist image exposes a portion of the semiconductor substrate 200 on the right side of the isolation structure 201, and then the dummy oxide layer on the core region is removed by an etching process using the photoresist image as a mask. The etching process may be a wet etching process or a dry etching process. The dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. The source gases for the dry etch may include CF4, CHF3, or other fluorocarbon gases. As an example, in this embodiment, the etching is dry etching, and the process parameters of the dry etching include: the etching gas comprises CF4, CHF3, etc., the flow rate is 50 sccm-500 sccm, 10 sccm-100 sccm, and the pressure is 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents millimeter mercury column.
The second gate oxide layer 205 may be formed by a thermal oxidation process such as dry oxygen oxidation, wet oxygen oxidation, high pressure oxidation, or by a CVD process such as rapid thermal CVD, LPCVD, HDPCVD, or the like. The second gate oxide layer 205 may illustratively be
Now, the process steps performed by the method according to the embodiment of the present invention are completed, and it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps, but also other required steps, such as a step of forming a gate electrode, or a step of forming a source/drain electrode, before, during, or after the above steps, which are included in the scope of the method for manufacturing the present invention.
Through the manufacturing method of the invention, in the advanced process, such as in the technical node of 28nm and below, silicon oxynitride interface layers and silicon oxide interface layers are respectively formed in an I/O region and a core region of an integrated circuit, so that on one hand, I/O which is less affected by interface nitrogen continuously uses silicon oxynitride as an interface layer to obtain a good equivalent oxide layer thickness, and on the other hand, in the core region which is more affected by interface nitrogen, silicon oxide is used as the interface layer, thereby overcoming the influence of interface nitrogen and improving the performance of a semiconductor device/the integrated circuit.
Example two
The invention also provides a semiconductor device manufactured by the method in the first embodiment, which comprises the following steps: the semiconductor device comprises a semiconductor substrate 300, wherein an isolation structure 301 is formed on the semiconductor substrate 300, the isolation structure 301 divides the semiconductor substrate into an I/O region and a core region, a first gate oxide layer 302 is formed on the I/O region, a second gate oxide layer 303 is formed on the core region, and the thickness of the first gate oxide layer 302 is larger than that of the second gate oxide layer 303. The semiconductor substrate 300 is a bulk silicon substrate, which may be at least one of the materials mentioned below: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like. Devices, such as NMOS and/or PMOS, etc., may be formed on the semiconductor substrate. Also, a conductive member may be formed in the semiconductor substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure may be formed in the semiconductor substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, and in this embodiment, the constituent material of the semiconductor substrate 300 is monocrystalline silicon.
The isolation structure 301 may be a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure, and may be formed by an isolation structure forming method commonly used in the art. As an example, in the present implementation, the isolation structure 301 is a shallow trench isolation structure, which is formed by patterning and etching on the semiconductor substrate 300, such as forming a trench for forming the shallow trench isolation structure 301 by patterning and etching, and then forming the shallow trench isolation structure 301 by filling an isolation material into the trench. The etching process may be a dry etching process or a wet etching process, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. The isolation materials include, but are not limited to: undoped Silicon Glass (USG), silicon dioxide, silicon nitride, and the like. As an example, in the present embodiment, Undoped Silicon Glass (USG) is used as the isolation material of the isolation structure 301, which may be formed by a common deposition process such as CVD, and will not be described herein.
The isolation structure 301 divides the semiconductor substrate 300 into an I/O region and a Core (Core) region, and the left side region of the isolation structure 301 is a region for forming an I/O circuit portion and the right side is a region for Core (Core) circuits in this embodiment, as an example. It is to be understood that the same is by way of illustration only and is not intended as a limitation upon the present invention.
The first gate oxide layer 302 is formed by oxidizing a nitride layer, i.e., first forming a nitride layer in the I/O region, which can be formed, for example, by using a low-energy nitrogen plasma nitridation process, the nitrogen plasma implantation energy being 2.0eV to 4.6eV, and the implantation dose being 1 × 1014atoms/cm2～2×1016atoms/cm2/cm2The temperature of the injection process is 300-800 ℃. The first gate oxide layer 302 is then formed by oxidizing the nitride layer to convert the silicon nitride film to a silicon oxynitride film, which may be, for example, of a thickness such as
The second gate oxide layer 303 may be formed by a thermal oxidation process such as dry oxygen oxidation, wet oxygen oxidation, high pressure oxidation, or by a CVD process such as rapid thermal CVD, LPCVD, HDPCVD, or the like.The thickness thereof may be, for example
EXAMPLE III
The invention further provides an electronic device which comprises the semiconductor device.
The electronic device also has the advantages described above, since the semiconductor device included has higher performance.
The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, and a PSP, or may be an intermediate product having the semiconductor device, for example: a mobile phone mainboard with the integrated circuit, and the like.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (5)

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, and forming an isolation structure on the semiconductor substrate, wherein the isolation structure divides the semiconductor substrate into an I/O (input/output) area and a core area;
forming a dummy oxide layer on the semiconductor substrate;
removing the virtual oxide layer on the I/O area;
forming a nitride layer on the I/O region;
oxidizing the nitride layer to form a first gate oxide layer;
removing the dummy oxide layer of the core region, and forming a second gate oxide layer on the core region,
the thickness of the first grid electrode oxidation layer is larger than that of the second grid electrode oxidation layer, the first grid electrode oxidation layer is a silicon oxynitride layer, and the second grid electrode oxidation layer is a silicon oxide layer.
2. The method of claim 1, wherein a nitride layer is formed in the I/O region by a low energy plasma nitridation process.
3. A method according to claim 1 or 2, wherein said nitride layer is a silicon nitride layer.
4. A semiconductor device prepared by the method of any of claims 1-3, comprising: the semiconductor substrate is divided into an I/O region and a core region by the isolation structure, a first grid oxide layer is formed on the I/O region, a second grid oxide layer is formed on the core region, the thickness of the first grid oxide layer is larger than that of the second grid oxide layer, the first grid oxide layer is a silicon oxynitride layer, and the second grid oxide layer is a silicon oxide layer.
5. An electronic device comprising the semiconductor device according to claim 4.
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