CN106559156A - The method and apparatus of clock frequency identification - Google Patents

Abstract

The invention discloses a kind of clock frequency knows method for distinguishing, including：The network equipment after receiving an input signal, on the basis of the internal signal produced by which, obtains the pulse number of the input signal in the predetermined period of the internal signal；Pulse number according to input signal is obtained is differentiated to the clock frequency type belonging to the input signal.The invention also discloses a kind of device of clock frequency identification.Present invention achieves differentiating to receiving the clock frequency type belonging to input signal, relative to the interface for increasing device reception varying input signal on network devices, or according to the accordingly modification configuration in software of the different network equipments, the cost of the network equipment is reduced, and improves the accuracy differentiated to input signal.

Description

The method and apparatus of clock frequency identification

Technical field

The present invention relates to terminal unit technical field, more particularly to a kind of clock frequency knowledge method for distinguishing and dress Put.

Background technology

In a communication network, Frequency Synchronization is most basic requirement.Frequency Synchronization is also referred to as clock synchronization, refers to The particular kind of relationship that frequency or phase place between signal keeps certain strict, its corresponding significant instant is with same Mean Speed occurs, to maintain all devices in communication network run with same speed.Once clock is not It is synchronous, the problems such as communication equipment can produce error code or business off and on.SDH (Synchronous Digital Hierarchy, SDH) or synchronous ethernet equipment according to ITUT G.781 all Offer meets 2M HZ, 2Mbit/s clock interfaces of ITUT G.823 interface standards, ITUT G.8262 pair when The performance of clock is such as drifted about, shakes etc. and proposing performance requirement.

With the development of wireless network, the networking model in network is more and more flexible.Light net under cable network It will be a kind of following application trend that network unit (Optical Network Unit, ONU) connects mobile base station.In State is moved to be not only restricted to american global positioning system (Global Positioning System, GPS), Propose two kinds of replacement schemes.One kind is to transmit accurately time signal by wire transmission network, another It is time signal source by the big-dipper satellite of China's independent research kind to be, is awarded with big-dipper satellite bimodulus using GPS When, it is active and standby each other.Combine in terms of the source of time and transmission two and break away from the dependence to GPS of America.Have In gauze network, the mode of transmission time has two kinds at present, and one kind is using IEEE 1588V2 (IEEE U.S. electricity Gas IEEE) by the synchronization of message deadline, another kind is to add day time by pulse per second (PPS) to agreement (i.e. 1pps+tod) transparent transmission mode.No matter which kind of mode, mobile radio network to be reached are high-precision for the time The requirement of degree all be unable to do without the synchronization of clock frequency.

In the networking of 1pps+tod transparent transmissions, the source of 1pps+tod is possibly according to China Mobile's form output Equipment, or GPS device.Gps clock equipment provides the output of two classes, and a class is that gps clock is same Step, the clock tame constant-temperature crystal oscillator (Oven Controlled Crystal using satellite-signal Oscillator, OCXO) or rubidium clock acquisition highly stable frequency.It is another kind of be after clock synchronization, Local recovery obtains more stable time scale information, including 1pps+tod information.Gps clock equipment is except adopting Outside GPS device, Big Dipper star system is may be selected, performance is higher.The outputting standard of GPS synchronised clock source devices Most widely used in interface is 10MHZ clock frequency signals, and the signal transmits split-second precision as downstream The synchronised clock frequency of information.

At present, in the network device, 2MHZ frequencies are all supported (such as the SDH clock frequencies of 2.048MHZ) Interface, after increased time synchronized, the application of 10MHZ frequencies (such as the gps clock frequency of 10MHZ) Increase, and problems faced is：(1) increase device on current equipment, there is provided receive different clocks The interface of frequency, now device hardware need to change, the artificial alternative costs of arranging net are improved.(2) existing Software in increase configuration, connected according to outside distinct device, corresponding modification configuration.User needs to know The definite signal frequency of device external connection, once configuration error, then cannot correctly recognize signal, cause Clock rate synchronization fails, and Time Transmission precision is not up to standard, affects downstream wireless communication, causes handss The problems such as machine user's communication goes offline.

The content of the invention

Present invention is primarily targeted at providing a kind of method and apparatus of clock frequency identification, it is intended to realize Differentiate to receiving the clock frequency type belonging to input signal, relative to increasing on network devices Device receives the interface of varying input signal, or is accordingly changed according to the different network equipments in software Configuration, reduces the cost of the network equipment and improves the accuracy differentiated to input signal.

For achieving the above object, the invention provides a kind of clock frequency knows method for distinguishing, including：

The network equipment after receiving an input signal, on the basis of the internal signal produced by which, is obtained The pulse number of input signal in the predetermined period of the internal signal；

Pulse number according to input signal is obtained is carried out to the clock frequency type belonging to the input signal Differentiate.

Alternatively, the network equipment after receiving an input signal, with the internal signal produced by which is Benchmark, the pulse number for obtaining the input signal in the predetermined period of the internal signal include：

The network equipment after receiving an input signal, on the basis of the internal pps pulse per second signal for producing, is being examined When measuring the first rising edge arrival of the pps pulse per second signal, start to carry out the pulse of the input signal Count；

Stop counting when the second rising edge for detecting the pps pulse per second signal is reached, obtain in the second The pulse number of the input signal in a cycle of pulse signal.

Alternatively, the basis obtains the pulse number of input signal to the clock belonging to the input signal Frequency type carries out differentiation to be included：

When the pulse number of the input signal is in the range of the first predetermined number, then the input letter is judged Number for SDH clock frequency signal；

When the pulse number of the input signal is in the range of the second predetermined number, then the input letter is judged Number for global positioning system clock frequency signal.

A kind of clock frequency knows method for distinguishing, including：

The network equipment after receiving an input signal, on the basis of the input signal, is obtained described defeated The pulse number of the internal signal produced by entering in the predetermined period of signal；

Pulse number according to internal signal is obtained is carried out to the clock frequency type belonging to the input signal Differentiate.

Alternatively, the network equipment after receiving an input signal, on the basis of the input signal, The pulse number for obtaining the internal signal produced by the predetermined period of the input signal includes：

The network equipment is after receiving an input signal, on the basis of the input signal, described detecting When first rising edge of input signal is reached, start to count the pulse of the internal high-frequency signal for producing；

Stop counting when the second rising edge for detecting the input signal is reached, obtain in the input The pulse number of the high-frequency signal in a cycle of signal.

Alternatively, the basis obtains the pulse number of internal signal to the clock belonging to the input signal Frequency type carries out differentiation to be included：

When the pulse number of the high-frequency signal is in the range of the 3rd predetermined number, then the input letter is judged Number for SDH clock frequency signal；

When the pulse number of the high-frequency signal is in the range of the 4th predetermined number, then the input letter is judged Number for global positioning system clock frequency signal.

Alternatively, the network equipment after receiving an input signal, on the basis of the input signal, The pulse number for obtaining the internal signal produced by the predetermined period of the input signal includes：

The network equipment is after receiving an input signal, on the basis of the input signal, described detecting When the rising edge of input signal is reached, start to count the pulse of the internal high-frequency signal for producing；

Stop counting when the trailing edge for detecting the input signal is reached, obtain in the input signal Half period in the high-frequency signal pulse number.

Alternatively, the basis obtains the pulse number of internal signal to the clock belonging to the input signal Frequency type carries out differentiation to be included：

The high-frequency signal according to frequency N of the high-frequency signal and in the half period of the input signal Pulse number X, calculates frequency R=N/ (2*X) of the input signal；

When the frequency of the input signal is in the range of the first predeterminated frequency, then judge the input signal as The clock frequency signal of SDH；

When the frequency of the input signal is in the range of the second predeterminated frequency, then judge the input signal as The clock frequency signal of global positioning system.

Additionally, for achieving the above object, present invention also offers a kind of device of clock frequency identification, bag Include：

Pulse number acquisition module, with produced by which for the network equipment after receiving an input signal On the basis of internal signal, the pulse number of the input signal in the predetermined period of the internal signal is obtained；

Type identification module, obtains the pulse number of input signal to belonging to the input signal for basis Clock frequency type differentiated.

Alternatively, the pulse number acquisition module is additionally operable to, the network equipment after receiving an input signal, On the basis of the internal pps pulse per second signal for producing, arrive in the first rising edge for detecting the pps pulse per second signal Up to when, start to count the pulse of the input signal；When detecting the of the pps pulse per second signal Stop counting when two rising edges are reached, obtain the input letter in a cycle of the pps pulse per second signal Number pulse number.

Alternatively, the type identification module is additionally operable to, when the pulse number of the input signal is first In the range of predetermined number, then clock frequency signal of the input signal as SDH is judged；When The pulse number of the input signal then judges the input signal as complete in the range of the second predetermined number The clock frequency signal of ball alignment system.

A kind of device of clock frequency identification, including：

Alternatively, acquisition module, is believed with the input for the network equipment after receiving an input signal On the basis of number, the pulse number of the internal signal produced by the predetermined period of the input signal is obtained；

Discrimination module, for according to obtain the pulse number of internal signal to belonging to the input signal when Clock frequency type is differentiated.

Alternatively, the acquisition module is additionally operable to, the network equipment after receiving an input signal, with described On the basis of input signal, when the first rising edge for detecting the input signal is reached, start to inside The pulse of the high-frequency signal of generation is counted；When the second rising edge for detecting the input signal is reached When stop count, obtain the pulse number of the high-frequency signal in a cycle of the input signal.

Alternatively, the discrimination module is additionally operable to, when the pulse number of the high-frequency signal is preset the 3rd In the range of number, then clock frequency signal of the input signal as SDH is judged；When described The pulse number of high-frequency signal in the range of the 4th predetermined number then judges the input signal and determines as the whole world The clock frequency signal of position system.

Alternatively, the acquisition module is additionally operable to, the network equipment after receiving an input signal, with described On the basis of input signal, when the rising edge for detecting the input signal is reached, start to internal generation The pulse of high-frequency signal counted；Stop meter when the trailing edge for detecting the input signal is reached Number, obtains the pulse number of the high-frequency signal in the half period of the input signal.

Alternatively, the discrimination module is additionally operable to, according to frequency N of the high-frequency signal and described defeated Enter the pulse number X of high-frequency signal in the half period of signal, calculate frequency R=N/ of the input signal (2*X)；

When the frequency of the input signal is in the range of the first predeterminated frequency, then judge the input signal as The clock frequency signal of SDH；When the frequency of the input signal is in the second predeterminated frequency scope It is interior, then judge clock frequency signal of the input signal as global positioning system.

The embodiment of the present invention in the network equipment after receiving an input signal, with the internal signal produced by which On the basis of, the pulse number for obtaining input signal in the predetermined period of signal internally comes to input signal institute The clock frequency type of category is differentiated.So that realizing to receiving the clock frequency belonging to input signal Type is differentiated, relative to the interface for increasing device reception varying input signal on network devices, or Person reduces the cost of the network equipment and carries according to the accordingly modification configuration in software of the different network equipments The high accuracy differentiated by input signal.

Description of the drawings

Fig. 1 is the schematic flow sheet that clock frequency of the present invention knows method for distinguishing first embodiment；

Fig. 2 is the schematic flow sheet that clock frequency of the present invention knows method for distinguishing second embodiment；

Fig. 3 is the high-level schematic functional block diagram of the device first embodiment of clock frequency identification of the present invention；

Fig. 4 is the high-level schematic functional block diagram of the device second embodiment of clock frequency identification of the present invention.

The realization of the object of the invention, functional characteristics and advantage will be done further in conjunction with the embodiments referring to the drawings Explanation.

Specific embodiment

It should be appreciated that specific embodiment described herein is not used to limit only to explain the present invention The fixed present invention.

As shown in figure 1, showing that a kind of clock frequency of the invention knows method for distinguishing first embodiment.The reality The clock frequency knowledge method for distinguishing for applying example includes：

Step S10, the network equipment after receiving an input signal, on the basis of the internal signal produced by which, Obtain the pulse number of the input signal in the predetermined period of the internal signal；

The present embodiment clock frequency is known method for distinguishing and be can be applicable to used in consolidated network device port SDH clocks, synchronous ethernet (Synchrous Ethernet Clock, SEC) clock, bag transmission net (Packet Translate network, PTN) clock, GPS synchronised clocks etc. be identified.The network equipment may include Packet Transport Network (Packet Transport Network, PTN) equipment, optical line terminal (Optical Line Terminal, OLT), ONU etc..

CPLD (Complex Programmable Logic are built-in with the network device Device, CPLD) or field programmable gate array (Field-Programmable Gate Array, ) etc. FPGA PLD completes the identification to clock frequency and selects processing function.Input signal It is and the generation such as the clock frequency instrument of network equipment external connection, gps clock instrument.Specifically, The network equipment after receiving an input signal, on the basis of internal signal, as sample frequency, The predetermined period formed between the rising edge or trailing edge of CPLD/FPGA detection internal signal arrivals, and In the triggering network equipment, built-in enumerator is calculated in the predetermined period of the internal signal, the arteries and veins of input signal Rush number.Internal signal may include with the pps pulse per second signal (i.e. 1pps) produced by CPLD/FPGA, by High-frequency signal that network equipment system clock or crystal oscillator are produced etc., its frequency more high accuracy are also higher.This is pre- If the cycle may be configured as a cycle or multiple cycles, flexibly arrange also dependent on concrete condition, its In, a cycle can be the distance between two adjacent rising edges of internal signal or trailing edge.

Step S20, basis obtain the pulse number of input signal to the clock frequency belonging to the input signal Type is differentiated.

The pulse of the input signal obtained according to rolling counters forward in network device internal CPLD/FPGA Number, determines the type belonging to input signal, for example, if obtaining 2048000 pulses, judge input Signal is the SDH clock frequencies of 2.048MHZ, if obtaining 10000000 pulses, judges input Signal is the GPS synchronised clock frequencies of 10MHZ.The type according to determined by input signal, CPLD/FPGA selects the processing mode of matching to carry out scaling down processing to input signal, will input signal turn It is changed to the unified frequency (i.e. fixed frequency) of the network equipment.Then unified frequency is sent through hardware link To phaselocked loop, behind phase lock loop locks following frequency source, characteristic frequency will be exported by user's request and be distributed to Whole system equipment is used, so as to complete the function of Frequency Synchronization.

The embodiment of the present invention in the network equipment after receiving an input signal, with the internal signal produced by which On the basis of, the pulse number for obtaining input signal in the predetermined period of signal internally comes to input signal institute The clock frequency type of category is differentiated, and completes corresponding frequencies process after recognition.So that the network equipment Automatic discrimination can be carried out to receiving the clock frequency type belonging to input signal, be realized to clock frequency Rate port carries out flexible and effective use, receives different input letters relative to device is increased on network devices Number interface, or according to the different network equipments in software accordingly modification configuration, reduce network and set Standby cost and improve the accuracy differentiated to input signal.

Further, based on above-mentioned first embodiment, in the present embodiment, above-mentioned steps S10 may include： The network equipment after receiving an input signal, on the basis of the internal pps pulse per second signal for producing, is being detected When first rising edge of the pps pulse per second signal is reached, start to count the pulse of the input signal；

Stop counting when the second rising edge for detecting the pps pulse per second signal is reached, obtain in the second The pulse number of the input signal in a cycle of pulse signal.

In the present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the GPS synchronised clock frequency sharing a ports of 10MHZ.

The network equipment under the pattern that port processes clock frequency, believe by the pulse per second (PPS) that CPLD/FPGA is produced On the basis of number, as sample frequency, flip-flop number carries out step-by-step counting to the input signal for receiving, For example, count pulse number of the input signal within a pps pulse per second signal cycle.Specifically, method one： When CPLD/FPGA receives input signal, and detect first rising edge arrival of pps pulse per second signal When, flip-flop number starts to count the pulse of input signal.On second of pps pulse per second signal Rise along stopping counting when reaching, obtain the pulse number of the input signal in a cycle of pps pulse per second signal. Method two：After CPLD/FPGA receives input signal, enumerator starts to enter the pulse of input signal Row is counted, and is reset by the rising edge triggering of pps pulse per second signal.Due to each input signal from scratch, Counting in first pps pulse per second signal may be discontented with a cycle, it is therefore desirable to by first pulse per second (PPS) Count value in signal is abandoned, i.e., when second pps pulse per second signal rising edge is reached, by counter O reset, Restart to count, stop counting when the rising edge of next pps pulse per second signal is reached.Then according to defeated Enter the pulse number of signal, differentiate that the input signal is 2.048MHZ signals or 10MHZ signals.When So, it is also possible to which the pulse to input signal within multiple cycles of pps pulse per second signal is counted, above-mentioned to obtain The mode for taking the pulse number of input signal is only enumerating for specific embodiment, and those skilled in the art carry Other for going out obtain the pulse number of input signal in the way of performing corresponding operation, the present invention's In protection domain.The present embodiment realizes the arteries and veins to input signal using pps pulse per second signal as sampled signal Rushing number carries out accurate counting.

Further, based on above-described embodiment, in the present embodiment, above-mentioned steps S20 may include：Work as institute The pulse number of input signal is stated in the range of the first predetermined number, then judges the input signal as synchronization The clock frequency signal of digital hierarchy；

When the pulse number of the input signal is in the range of the second predetermined number, then the input letter is judged Number for global positioning system clock frequency signal.

The present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the gps clock frequency sharing a port of 10MHZ.Input letter is obtained above-mentioned Number pulse number after, according to the pulse number of input signal, CPLD/FPGA differentiates that the input signal is 2.048MHZ signals or 10MHZ signals.The 2.048MHZ signal standardss within the pulse per second (PPS) cycle Counting can reach 2048000 pulses, and due to the presence of frequency deviation, the pulse number that enumerator is obtained should Certain error is allowed.Specifically, it is assumed that obtain the pulse number of input signal in the first predetermined number model In enclosing, then judge input signal as 2.048MHZ SDH clock frequencies, the first predetermined number scope May be configured as 2048000 ± 12.If the pulse number of the input signal for obtaining is in the second predetermined number model In enclosing, then judge input signal as 10MHZ gps clock frequency, the second predetermined number scope can It is set to 10000000 ± 12.The first predetermined number scope and the second predetermined number scope can be according to tools Body situation and flexibly arrange.It is determined that after clock frequency type belonging to input signal, can according to difference when Clock frequency carries out respective handling, is divided into the frequency of network equipment needs.

The present embodiment in the same network equipment, the SDH clock frequencies of 2.048MHZ and 10MHZ Gps clock frequency sharing a port, and need not increase user configuring operation, pass through The PLDs such as CPLD/FPGA complete frequency identification and select processing function.Only need to increase The programming content of CPLD/FPGA, the CPLD/FPGA files of existing network of upgrading reach just can the network equipment The function of supporting gps clock frequency is added in the application, had both been reduced the cost of the network equipment, and had been also complied with The O＆M of Virtual network operator is required.

Further, as shown in Fig. 2 showing that a kind of clock frequency of the invention knows method for distinguishing second in fact Apply example.The clock frequency of the embodiment knows method for distinguishing to be included：

Step S30, the network equipment after receiving an input signal, on the basis of the input signal, are obtained The pulse number of produced internal signal in the predetermined period of the input signal；

The present embodiment clock frequency is known method for distinguishing and be can be applicable to used in consolidated network device port SDH clocks, synchronous Ethernet clock (Synchrous Ethernet Clock, SEC), bag transmission net (Packet Translate network, PTN) clock, GPS synchronised clocks etc. be identified.The network equipment may include Packet Transport Network (Packet Transport Network, PTN) equipment, optical line terminal (Optical Line Terminal, OLT), ONU etc..

CPLD (Complex Programmable Logic are built-in with the network device Device, CPLD) or field programmable gate array (Field-Programmable Gate Array, ) etc. FPGA PLD completes the identification to clock frequency and selects processing function.Input signal It is and the generation such as the clock frequency instrument of network equipment external connection, gps clock instrument.Specifically, The network equipment after receiving an input signal, on the basis of input signal, as sample frequency, is examined The predetermined period formed between the rising edge or trailing edge of surveying input signal arrival, and trigger the network equipment In built-in enumerator calculate in the predetermined period of the input signal, the pulse number of internal signal.It is internal Signal is may include with the pps pulse per second signal (i.e. 1pps) produced by CPLD/FPGA, by network equipment system The high-frequency signal that high-frequency signal that clock or crystal oscillator are produced etc. is provided by the network equipment itself, its frequency are higher Precision is also higher.The predetermined period may be configured as a cycle or multiple cycles, also dependent on concrete feelings Condition and flexibly arrange, wherein, a cycle can be two adjacent rising edges of input signal or trailing edge The distance between.

Step S40, basis obtain the pulse number of internal signal to the clock frequency belonging to the input signal Type is differentiated.

The pulse of the internal signal obtained according to rolling counters forward in network device internal CPLD/FPGA Number, determines the type belonging to input signal, and for example, if obtaining 9 pulses, input signal is 2.048MHZ SDH clock frequencies, if obtaining 1 pulse, input signal is the GPS synchronised clocks of 10MHZ Frequency.After CPLD/FPGA types according to determined by input signal, the processing mode of matching is selected to defeated Entering signal carries out scaling down processing, will input signal be converted to the unified frequency of the network equipment and (fix Frequency).Then unified frequency is delivered to into phaselocked loop through hardware link, behind phase lock loop locks following frequency source, Characteristic frequency will be exported by user's request and be distributed to the use of whole system equipment, so as to complete Frequency Synchronization Function.

The embodiment of the present invention after receiving an input signal, on the basis of input signal, is obtained in the network equipment The pulse number of the internal signal produced by being taken in the predetermined period of input signal comes to belonging to input signal Clock frequency type differentiated, and complete after recognition corresponding frequencies process.Enable the network equipment It is enough to carry out automatic discrimination to receiving the clock frequency type belonging to input signal, realize to clock frequency Port carries out flexible and effective use, receives varying input signal relative to device is increased on network devices Interface, or according to the different network equipments in software accordingly modification configuration, reduce the network equipment Cost and improve the accuracy differentiated to input signal.

Further, based on above-mentioned second embodiment, in one embodiment, above-mentioned steps S30 may include： The network equipment after receiving an input signal, on the basis of the input signal, is detecting the input When first rising edge of signal is reached, start to count the pulse of the internal high-frequency signal for producing；

Stop counting when the second rising edge for detecting the input signal is reached, obtain in the input The pulse number of the high-frequency signal in a cycle of signal.

In the present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the GPS synchronised clock frequency sharing a ports of 10MHZ.

The high-frequency signal for being produced by system clock or crystal oscillator in the network device may include 77.76MHZ and 19.44MHZ, below will illustrate so that 19.44MHZ high-frequency signals do benchmark as an example.With input signal On the basis of, as sample frequency, flip-flop number is produced to device systems clock or crystal oscillator The pulse of 19.44MHZ high-frequency signals is counted.Specifically, the network equipment processes clock frequency in port Pattern under, enumerator calculates high-frequency signal arteries and veins between the two neighboring rising edge of input signal or trailing edge Rush number.I.e. after input signal is received, in first rising edge arrival hour counter of input signal Start to calculate the pulse number of high-frequency signal, stop counting when second rising edge of input signal is reached, Obtain the pulse number of the high-frequency signal in a cycle of input signal.Then CPLD/FPGA according to The pulse number of 19.44MHZ high-frequency signals, differentiate the input signal be 2.048MHZ signals or 10MHZ signals.It is of course also possible to the pulse to high-frequency signal within multiple cycles of input signal is carried out Count, do not limit the present invention.The present embodiment is taken as frequency with high-frequency signal, realizes to input The pulse number of signal carries out accurate counting.

Further, based on above-mentioned second embodiment, in one embodiment, above-mentioned steps S40 may include： When the pulse number of the high-frequency signal is in the range of the 3rd predetermined number, then judge the input signal as The clock frequency signal of SDH；

When the pulse number of the high-frequency signal is in the range of the 4th predetermined number, then the input letter is judged Number for global positioning system clock frequency signal.

The present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the gps clock frequency sharing a port of 10MHZ.High frequency letter is obtained above-mentioned Number pulse number after, according to the pulse number of high-frequency signal, CPLD/FPGA differentiates that the input signal is 2.048MHZ signals or 10MHZ signals.Specifically, due to the presence of frequency deviation, when high-frequency signal Pulse number in the range of the 3rd predetermined number, then judge input signal as 2.048MHZ SDH clocks Frequency, the 3rd predetermined number scope may be configured as 8～10 pulses.When the pulse number of high-frequency signal exists In the range of 4th predetermined number, then judge input signal as 10MHZ gps clock frequency, the 4th Predetermined number scope may be configured as 1～3 pulse.3rd predetermined number scope and the 4th predetermined number model Enclose and can arrange as the case may be and flexibly.Certainly, also can using both intermediate values 5 as decision boundaries, If the pulse number of the high-frequency signal for obtaining is less than or equal to 5, judge that input signal is 2.048MHZ's SDH clock frequencies；If the pulse number of the high-frequency signal for obtaining be more than 5, judge input signal as The gps clock frequency of 10MHZ.After finally determining the clock frequency type belonging to input signal, CPLD/FPGA is divided into frequency needed for the network equipment to the input signal.

The present embodiment in the same network equipment, the SDH clock frequencies of 2.048MHZ and 10MHZ Gps clock frequency sharing a port, and need not increase user configuring operation, pass through The PLDs such as CPLD/FPGA complete frequency identification and select processing function, reduce network and set Standby cost.

Further, based on above-mentioned second embodiment, in another embodiment, above-mentioned steps S30 can be wrapped Include：The network equipment is after receiving an input signal, on the basis of the input signal, described detecting When the rising edge of input signal is reached, start to count the pulse of the internal high-frequency signal for producing；

Stop counting when the trailing edge for detecting the input signal is reached, obtain in the input signal Half period in the high-frequency signal pulse number.

In the present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the GPS synchronised clock frequency sharing a ports of 10MHZ.

The high-frequency signal for being produced by system clock or crystal oscillator in the network device may include 77.76MHZ and 19.44MHZ, below will illustrate so that 19.44MHZ high frequency points signals do benchmark as an example.To be input into letter On the basis of number, as sample frequency, and the pulse by enumerator to 19.44MHZ high-frequency signals is entered Row is counted.Specifically, the network equipment is under the pattern that port processes clock frequency, adjacent in input signal Rising edge and trailing edge between obtain high-frequency signal pulse number.I.e. when CPLD/FPGA receives input After signal, start to calculate the pulse number of high-frequency signal in the rising edge arrival hour counter of input signal, Stop counting when the trailing edge of input signal is reached, obtain in the half period of input signal 19.44MHZ the pulse number of high-frequency signal.Then pulse numbers of the CPLD/FPGA according to high-frequency signal, Differentiate that the input signal is 2.048MHZ signals or 10MHZ signals.It is of course also possible in input letter Number multiple cycles in the pulse of high-frequency signal is counted, limit the present invention.The present embodiment with High-frequency signal is taken as frequency, and also high accuracy is also higher for the frequency of high-frequency signal, realizes to input letter Number pulse number carry out accurate counting.

Further, based on above-mentioned second embodiment, in another embodiment, above-mentioned steps S40 can be wrapped Include：The high-frequency signal according to frequency N of the high-frequency signal and in the half period of the input signal Pulse number X, calculates frequency R=N/ (2*X) of the input signal；

When the frequency of the input signal is in the range of the first predeterminated frequency, then judge the input signal as The clock frequency signal of SDH；

When the frequency of the input signal is in the range of the second predeterminated frequency, then judge the input signal as The clock frequency signal of global positioning system.

The present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the gps clock frequency sharing a port of 10MHZ.Obtain above-mentioned After the pulse number of 19.44MHZ high-frequency signals, pulse number meters of the CPLD/FPGA according to high-frequency signal Calculate input signal frequency, and according to the frequency for obtaining differentiate the input signal be 2.048MHZ signals also It is 10MHZ signals.Specifically, using 19.44MHZ high-frequency signals as sample frequency, it is assumed that sampling frequency Rate is N, and the pulse number for counting to get is X, obtains the sampling period for 1/N, general by sample frequency N The pulse number X for obtaining and sample frequency N are calculated the high-frequency signal in a cycle of input signal Persistent period be t=2*X* (1/N).As the waveform of signal is sine, the i.e. dutycycle of low and high level All it is 0.5, then needs for the time for calculating high level to be multiplied by 2, obtain the duration of a cycle, it is inverted Obtain the frequency of input signal.Frequency R=1/ of input signal is calculated further according to sample frequency N and time t T=N/ (2*X).

It should be noted that due to the presence of frequency deviation, the frequency for calculating should allow certain error. When the frequency of input signal is in the range of the first predeterminated frequency, then judge that input signal is 2.048MHZ's SDH clock frequencies, the first predeterminated frequency scope may be configured as 2.048MHZ ± 26HZ.When input letter Number frequency in the range of the second predeterminated frequency, then judge input signal as 2.048MHZ SDH clocks Frequency, the second predeterminated frequency scope may be configured as 10MHZ ± 120HZ.First predeterminated frequency scope and Second predeterminated frequency scope is configured also dependent on concrete condition, is not limited and is invented.Then Input signal is divided into net according to result of determination according to the processing mode of different frequency by CPLD/FPGA The frequency that network equipment needs.I.e. PLD can divide into symbol according to the processing mode of different frequency The clock frequency of self-demand is closed, and is supplied to the network equipment network equipment can be reached with synchronous clock source The final purpose of clock rate synchronization.

The present embodiment in the same network equipment, the SDH clock frequencies of 2.048MHZ and 10MHZ Gps clock frequency sharing a port, and need not increase user configuring operation, pass through The PLDs such as CPLD/FPGA complete frequency identification and select processing function.Only need to increase The programming content of CPLD/FPGA, the CPLD/FPGA files of existing network of upgrading reach just can the network equipment The function of supporting GPS frequency is added in the application, reduces the cost of the network equipment.

Accordingly, as shown in figure 3, proposing a kind of device first embodiment of clock frequency identification of the invention. The device of the clock frequency identification of the embodiment includes：

Pulse number acquisition module 100, with produced by which for the network equipment after receiving an input signal Internal signal on the basis of, obtain the pulse number of the input signal in the predetermined period of the internal signal；

The present embodiment clock frequency is known method for distinguishing and be can be applicable to used in consolidated network device port SDH clocks, synchronous ethernet (Synchrous Ethernet Clock, SEC) clock, bag transmission net (Packet Translate network, PTN) clock, GPS synchronised clocks etc. be identified.The network equipment may include Packet Transport Network (Packet Transport Network, PTN) equipment, optical line terminal (Optical Line Terminal, OLT), ONU etc..

CPLD (Complex Programmable Logic are built-in with the network device Device, CPLD) or field programmable gate array (Field-Programmable Gate Array, ) etc. FPGA PLD completes the identification to clock frequency and selects processing function.Input signal It is and the generation such as the clock frequency instrument of network equipment external connection, gps clock instrument.Specifically, The network equipment after receiving an input signal, on the basis of internal signal, as sample frequency, The predetermined period formed between the rising edge or trailing edge of CPLD/FPGA detection internal signal arrivals, and In calling the triggering network equipment of pulse number acquisition module 100, built-in enumerator is calculated in the internal signal In predetermined period, the pulse number of input signal.Internal signal is may include with produced by CPLD/FPGA Pps pulse per second signal (i.e. 1pps), the high-frequency signal produced by network equipment system clock or crystal oscillator etc., its frequency Rate more high accuracy is also higher.The predetermined period may be configured as a cycle or multiple cycles, also dependent on Concrete condition and flexibly arrange, wherein, a cycle can be two adjacent rising edges of internal signal or The distance between trailing edge.

Type identification module 200, obtains the pulse number of input signal to the input signal institute for basis The clock frequency type of category is differentiated.

The pulse of the input signal obtained according to rolling counters forward in network device internal CPLD/FPGA Number, the type by belonging to type identification module 200 determines input signal, for example, if obtaining 2048000 Individual pulse, then judge that input signal is the SDH clock frequencies of 2.048MHZ, if obtaining 10000000 Individual pulse, then judge that input signal is the GPS synchronised clock frequencies of 10MHZ.According to input signal institute It is determined that type, CPLD/FPGA select matching processing mode scaling down processing is carried out to input signal, i.e., Input signal is converted to into the unified frequency (i.e. fixed frequency) of the network equipment.Then by unified frequency Jing Cross hardware link and deliver to phaselocked loop, behind phase lock loop locks following frequency source, will export specific by user's request Frequency is simultaneously distributed to the use of whole system equipment, so as to complete the function of Frequency Synchronization.

The embodiment of the present invention in the network equipment after receiving an input signal, with the internal signal produced by which On the basis of, the pulse number for obtaining input signal in the predetermined period of signal internally comes to input signal institute The clock frequency type of category is differentiated, and completes corresponding frequencies process after recognition.So that the network equipment Automatic discrimination can be carried out to receiving the clock frequency type belonging to input signal, be realized to clock frequency Rate port carries out flexible and effective use, receives different input letters relative to device is increased on network devices Number interface, or according to the different network equipments in software accordingly modification configuration, reduce network and set Standby cost and improve the accuracy differentiated to input signal.

Further, based on above-mentioned first embodiment, in the present embodiment, above-mentioned pulse number acquisition module 100 are additionally operable to, the network equipment after receiving an input signal, on the basis of the internal pps pulse per second signal for producing, When the first rising edge for detecting the pps pulse per second signal is reached, start the pulse to the input signal Counted；Stop counting when the second rising edge for detecting the pps pulse per second signal is reached, obtain The pulse number of the input signal in a cycle of the pps pulse per second signal.

In the present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the GPS synchronised clock frequency sharing a ports of 10MHZ.

The network equipment under the pattern that port processes clock frequency, believe by the pulse per second (PPS) that CPLD/FPGA is produced On the basis of number, as sample frequency, by 100 flip-flop number of pulse number acquisition module to receiving Input signal carry out step-by-step counting, for example, statistics input signal is within the pps pulse per second signal cycle Pulse number.Specifically, method one：When CPLD/FPGA receives input signal, and detect a second arteries and veins It is when rushing first rising edge arrival of signal, right by 100 flip-flop number of pulse number acquisition module The pulse of input signal is counted.Stop counting when second rising edge of pps pulse per second signal is reached, Obtain the pulse number of the input signal in a cycle of pps pulse per second signal.Method two：When It is after CPLD/FPGA receives input signal, right by 100 flip-flop number of pulse number acquisition module The pulse of input signal is counted, and is reset by the rising edge triggering of pps pulse per second signal.Due to defeated every time Enter signal from scratch, the counting in first pps pulse per second signal may be discontented with a cycle, therefore need Count value in first pps pulse per second signal is abandoned, i.e., is reached in second pps pulse per second signal rising edge When, by counter O reset, restart to count, stop when the rising edge of next pps pulse per second signal is reached Only count.Then according to the pulse number of input signal, differentiates that the input signal is 2.048MHZ signals Or 10MHZ signals.It is of course also possible to the arteries and veins within multiple cycles of pps pulse per second signal to input signal Capable counting is rushed in, the mode of the pulse number of above-mentioned acquisition input signal is only enumerating for specific embodiment, The pulse number of other acquisition input signals that those skilled in the art propose is to perform the side of operation accordingly Formula, within the scope of the present invention.The present embodiment is realized using pps pulse per second signal as sampled signal Accurate counting carried out to the pulse number of input signal.

Further, based on above-described embodiment, in the present embodiment, the above-mentioned type discrimination module 200 is also used In, when the pulse number of the input signal is in the range of the first predetermined number, then judge it is described input letter Number for SDH clock frequency signal；When the pulse number of the input signal is preset second In the range of number, then clock frequency signal of the input signal as global positioning system is judged.

The present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the gps clock frequency sharing a port of 10MHZ.Input letter is obtained above-mentioned Number pulse number after, according to the pulse number of input signal, type identification module 200 differentiates that the input is believed Number it is 2.048MHZ signals or 10MHZ signals.The 2.048MHZ signals within the pulse per second (PPS) cycle Standard is counted and can reach 2048000 pulses, due to the presence of frequency deviation, the pulse number that enumerator is obtained Certain error should have been allowed.Specifically, it is assumed that obtain the pulse number of input signal at first default Number scopes in, then judge input signal as 2.048MHZ SDH clock frequencies, first predetermined number Scope may be configured as 2048000 ± 12.If the pulse number of the input signal for obtaining is at second default Number scopes in, then judge input signal as 10MHZ gps clock frequency, the second predetermined number model Enclose and may be configured as 10000000 ± 12.The first predetermined number scope and the second predetermined number scope can roots Flexibly arrange according to concrete condition.It is determined that after clock frequency type belonging to input signal, can be according to not Respective handling is carried out with clock frequency, the frequency of network equipment needs is divided into.

The present embodiment in the same network equipment, the SDH clock frequencies of 2.048MHZ and 10MHZ Gps clock frequency sharing a port, and need not increase user configuring operation, pass through The PLDs such as CPLD/FPGA complete frequency identification and select processing function.Only need to increase The programming content of CPLD/FPGA, the CPLD/FPGA files of existing network of upgrading reach just can the network equipment The function of supporting gps clock frequency is added in the application, had both been reduced the cost of the network equipment, and had been also complied with The O＆M of Virtual network operator is required.

Further, as shown in figure 4, proposing that a kind of device second of clock frequency identification of the invention is implemented Example.The device of the clock frequency identification of the embodiment includes：

Acquisition module 300, with the input signal as base for the network equipment after receiving an input signal Standard, obtains the pulse number of the internal signal produced by the predetermined period of the input signal；

The present embodiment clock frequency is known method for distinguishing and be can be applicable to used in consolidated network device port SDH clocks, synchronous Ethernet clock (Synchrous Ethernet Clock, SEC), bag transmission net (Packet Translate network, PTN) clock, GPS synchronised clocks etc. be identified.The network equipment may include Packet Transport Network (Packet Transport Network, PTN) equipment, optical line terminal (Optical Line Terminal, OLT), ONU etc..

CPLD (Complex Programmable Logic are built-in with the network device Device, CPLD) or field programmable gate array (Field-Programmable Gate Array, ) etc. FPGA PLD completes the identification to clock frequency and selects processing function.Input signal It is and the generation such as the clock frequency instrument of network equipment external connection, gps clock instrument.Specifically, The network equipment after receiving an input signal, on the basis of input signal, as sample frequency, is examined The predetermined period formed between the rising edge or trailing edge of surveying input signal arrival, and by acquisition module 300 In the triggering network equipment, built-in enumerator is calculated in the predetermined period of the input signal, the arteries and veins of internal signal Rush number.Internal signal may include with the pps pulse per second signal (i.e. 1pps) produced by CPLD/FPGA, by The high frequency letter that high-frequency signal that network equipment system clock or crystal oscillator are produced etc. is provided by the network equipment itself Number, its frequency more high accuracy is also higher.The predetermined period may be configured as a cycle or multiple cycles, Flexibly arrange also dependent on concrete condition, wherein, a cycle can be adjacent upper of input signal two Rise the distance between edge or trailing edge.

Discrimination module 400, obtains the pulse number of internal signal to belonging to the input signal for basis Clock frequency type is differentiated.

The pulse of the internal signal obtained according to rolling counters forward in network device internal CPLD/FPGA Number, the type by belonging to discrimination module 400 determines input signal, for example, if obtaining 9 pulses, Input signal is the SDH clock frequencies of 2.048MHZ, if obtaining 1 pulse, input signal is The GPS synchronised clock frequencies of 10MHZ.After 400 type according to determined by input signal of discrimination module, CPLD/FPGA selects the processing mode of matching to carry out scaling down processing to input signal, will input signal turn It is changed to the unified frequency (i.e. fixed frequency) of the network equipment.Then unified frequency is sent through hardware link To phaselocked loop, behind phase lock loop locks following frequency source, characteristic frequency will be exported by user's request and be distributed to Whole system equipment is used, so as to complete the function of Frequency Synchronization.

The embodiment of the present invention after receiving an input signal, on the basis of input signal, is obtained in the network equipment The pulse number of the internal signal produced by being taken in the predetermined period of input signal comes to belonging to input signal Clock frequency type differentiated, and complete after recognition corresponding frequencies process.Enable the network equipment It is enough to carry out automatic discrimination to receiving the clock frequency type belonging to input signal, realize to clock frequency Port carries out flexible and effective use, receives varying input signal relative to device is increased on network devices Interface, or according to the different network equipments in software accordingly modification configuration, reduce the network equipment Cost and improve the accuracy differentiated to input signal.

Further, based on above-mentioned second embodiment, in one embodiment, above-mentioned acquisition module 300 is gone back For, the network equipment after receiving an input signal, on the basis of the input signal, detecting When stating the first rising edge arrival of input signal, start to count the pulse of the internal high-frequency signal for producing Number；Stop counting when the second rising edge for detecting the input signal is reached, obtain in the input The pulse number of the high-frequency signal in a cycle of signal.

In the present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the GPS synchronised clock frequency sharing a ports of 10MHZ.

The high-frequency signal for being produced by system clock or crystal oscillator in the network device may include 77.76MHZ and 19.44MHZ, below will illustrate so that 19.44MHZ high-frequency signals do benchmark as an example.With input signal On the basis of, as sample frequency, by 300 flip-flop number of acquisition module to device systems clock or crystalline substance The pulse of 19.44MHZ high-frequency signals of generation of shaking is counted.Specifically, the network equipment is in port Under the pattern of reason clock frequency, 300 flip-flop number of acquisition module is in the two neighboring rising edge of input signal Or between trailing edge, calculate high-frequency signal pulse number.I.e. after input signal is received, in input signal First rising edge arrival hour counter start to calculate the pulse number of high-frequency signal, in input signal the Two rising edges stop counting when reaching, and obtain the pulse of the high-frequency signal in a cycle of input signal Number.Then pulse numbers of the CPLD/FPGA according to 19.44MHZ high-frequency signals, differentiates that the input is believed Number it is 2.048MHZ signals or 10MHZ signals.It is of course also possible in multiple cycles of input signal The interior pulse to high-frequency signal is counted, and does not limit the present invention.The present embodiment using high-frequency signal as Using frequency, realizing the pulse number to input signal carries out accurate counting.

Further, based on above-mentioned second embodiment, in one embodiment, above-mentioned discrimination module 400 is gone back For when the pulse number of the high-frequency signal is in the range of the 3rd predetermined number, then judging the input Clock frequency signal of the signal for SDH；When the pulse number of the high-frequency signal it is pre- the 4th If in the range of number, then judging clock frequency signal of the input signal as global positioning system.

The present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the gps clock frequency sharing a port of 10MHZ.High frequency letter is obtained above-mentioned Number pulse number after, according to the pulse number of high-frequency signal, discrimination module 400 differentiates that the input signal is 2.048MHZ signals or 10MHZ signals.Specifically, due to the presence of frequency deviation, when high-frequency signal Pulse number in the range of the 3rd predetermined number, then judge input signal as 2.048MHZ SDH clocks Frequency, the 3rd predetermined number scope may be configured as 8～10 pulses.When the pulse number of high-frequency signal exists In the range of 4th predetermined number, then judge input signal as 10MHZ gps clock frequency, the 4th Predetermined number scope may be configured as 1～3 pulse.3rd predetermined number scope and the 4th predetermined number model Enclose and can arrange as the case may be and flexibly.Certainly, also can using both intermediate values 5 as decision boundaries, If the pulse number of the high-frequency signal for obtaining is less than or equal to 5, judge that input signal is 2.048MHZ's SDH clock frequencies；If the pulse number of the high-frequency signal for obtaining be more than 5, judge input signal as The gps clock frequency of 10MHZ.After finally determining the clock frequency type belonging to input signal, CPLD/FPGA is divided into frequency needed for the network equipment to the input signal.

The present embodiment in the same network equipment, the SDH clock frequencies of 2.048MHZ and 10MHZ Gps clock frequency sharing a port, and need not increase user configuring operation, pass through The PLDs such as CPLD/FPGA complete frequency identification and select processing function, reduce network and set Standby cost.

Further, based on above-mentioned second embodiment, in another embodiment, above-mentioned acquisition module 300 It is additionally operable to, the network equipment after receiving an input signal, on the basis of the input signal, is being detected When the rising edge of the input signal is reached, start to count the pulse of the internal high-frequency signal for producing； Stop counting when the trailing edge for detecting the input signal is reached, obtain the half of the input signal The pulse number of the high-frequency signal in the individual cycle.

In the present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the GPS synchronised clock frequency sharing a ports of 10MHZ.

The high-frequency signal for being produced by system clock or crystal oscillator in the network device may include 77.76MHZ and 19.44MHZ, below will illustrate so that 19.44MHZ high frequency points signals do benchmark as an example.To be input into letter On the basis of number, as sample frequency, and by 300 flip-flop number of acquisition module to 19.44MHZ The pulse of high-frequency signal is counted.Specifically, the network equipment port process clock frequency pattern under, Acquisition module 300 obtains high-frequency signal pulse number between the adjacent rising edge of input signal and trailing edge. I.e. after CPLD/FPGA receives input signal, start in the rising edge arrival hour counter of input signal The pulse number of high-frequency signal is calculated, is stopped counting when the trailing edge of input signal is reached, is obtained defeated Enter the pulse number of 19.44MHZ high-frequency signals in the half period of signal.Then CPLD/FPGA according to The pulse number of high-frequency signal, differentiates that the input signal is 2.048MHZ signals or 10MHZ signals. It is of course also possible to the pulse to high-frequency signal within multiple cycles of input signal is counted, do not limit The fixed present invention.The present embodiment is taken as frequency with high-frequency signal, and the frequency of high-frequency signal is also in high precision Higher, realizing the pulse number to input signal carries out accurate counting.

Further, based on above-mentioned second embodiment, in another embodiment, above-mentioned discrimination module 400 It is additionally operable to, the high frequency letter according to frequency N of the high-frequency signal and in the half period of the input signal Number pulse number X, calculate frequency R=N/ (2*X) of the input signal；

When the frequency of the input signal is in the range of the first predeterminated frequency, then judge the input signal as The clock frequency signal of SDH；When the frequency of the input signal is in the second predeterminated frequency scope It is interior, then judge clock frequency signal of the input signal as global positioning system.

The present embodiment will with the same network equipment, by the SDH clock frequencies of 2.048MHZ and It is described in detail as a example by the gps clock frequency sharing a port of 10MHZ.Obtain above-mentioned After the pulse number of 19.44MHZ high-frequency signals, pulse number meter of the discrimination module 400 according to high-frequency signal The frequency of input signal is calculated, according to the frequency for obtaining, CPLD/FPGA differentiates that the input signal is 2.048MHZ signals or 10MHZ signals.Specifically, using 19.44MHZ high-frequency signals as sampling Frequency, it is assumed that sample frequency is N, the pulse number for counting to get are X, are adopted by sample frequency N The sample cycle is 1/N, and the pulse number X for obtaining and sample frequency N are calculated the one of input signal The persistent period of individual high frequency intra-cycle signal is t=2*X* (1/N).As the waveform of signal is sine, i.e., The dutycycle of low and high level is all 0.5, then need for the time for calculating high level to be multiplied by 2, obtain one it is all The duration of phase, the inverted frequency for obtaining input signal.Calculate defeated further according to sample frequency N and time t Enter frequency R=1/t=N/ (2*X) of signal.

It should be noted that due to the presence of frequency deviation, the frequency for calculating should allow certain error. When the frequency of input signal is in the range of the first predeterminated frequency, then judge that input signal is 2.048MHZ's SDH clock frequencies, the first predeterminated frequency scope may be configured as 2.048MHZ ± 26HZ.When input letter Number frequency in the range of the second predeterminated frequency, then judge input signal as 2.048MHZ SDH clocks Frequency, the second predeterminated frequency scope may be configured as 10MHZ ± 120HZ.First predeterminated frequency scope and Second predeterminated frequency scope is configured also dependent on concrete condition, is not limited and is invented.Then Input signal is divided into net according to result of determination according to the processing mode of different frequency by CPLD/FPGA The frequency that network equipment needs.I.e. PLD can divide into symbol according to the processing mode of different frequency The clock frequency of self-demand is closed, and is supplied to the network equipment network equipment can be reached with synchronous clock source The final purpose of clock rate synchronization.

The present embodiment in the same network equipment, the SDH clock frequencies of 2.048MHZ and 10MHZ Gps clock frequency sharing a port, and need not increase user configuring operation, pass through The PLDs such as CPLD/FPGA complete frequency identification and select processing function.Only need to increase The programming content of CPLD/FPGA, the CPLD/FPGA files of existing network of upgrading reach just can the network equipment The function of supporting GPS frequency is added in the application, reduces the cost of the network equipment.

Through the above description of the embodiments, those skilled in the art can be understood that above-mentioned Embodiment method can add the mode of required general hardware platform to realize by software, naturally it is also possible to logical Cross hardware, but the former is more preferably embodiment in many cases.It is based on such understanding, of the invention The part that technical scheme is substantially contributed to prior art in other words can in the form of software product body Reveal and, the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disc, light Disk) in, use so that a station terminal equipment including some instructions (can be mobile phone, computer, service Device, air-conditioner, or network equipment etc.) perform method described in each embodiment of the invention.

The preferred embodiments of the present invention are these are only, the scope of the claims of the present invention is not thereby limited, it is every The equivalent structure made using description of the invention and accompanying drawing content or equivalent flow conversion, or directly or Connect and be used in other related technical fields, be included within the scope of the present invention.

Claims (16)

1. a kind of clock frequency knows method for distinguishing, it is characterised in that the clock frequency knows method for distinguishing bag Include following steps：

The network equipment after receiving an input signal, on the basis of the internal signal produced by which, is obtained The pulse number of input signal in the predetermined period of the internal signal；

Pulse number according to input signal is obtained is carried out to the clock frequency type belonging to the input signal Differentiate.

2. clock frequency as claimed in claim 1 knows method for distinguishing, it is characterised in that the network sets For after receiving an input signal, on the basis of the internal signal produced by which, obtain in the internal letter Number predetermined period in the pulse number of input signal include：

The network equipment after receiving an input signal, on the basis of the internal pps pulse per second signal for producing, is being examined When measuring the first rising edge arrival of the pps pulse per second signal, start to carry out the pulse of the input signal Count；

Stop counting when the second rising edge for detecting the pps pulse per second signal is reached, obtain in the second The pulse number of the input signal in a cycle of pulse signal.

3. clock frequency as claimed in claim 2 knows method for distinguishing, it is characterised in that the basis is obtained Pulse number to input signal carries out differentiation to the clock frequency type belonging to the input signal and includes：

When the pulse number of the input signal is in the range of the first predetermined number, then the input letter is judged Number for SDH clock frequency signal；

When the pulse number of the input signal is in the range of the second predetermined number, then the input letter is judged Number for global positioning system clock frequency signal.

4. a kind of clock frequency knows method for distinguishing, it is characterised in that the clock frequency knows method for distinguishing bag Include following steps：

The network equipment after receiving an input signal, on the basis of the input signal, is obtained described defeated The pulse number of the internal signal produced by entering in the predetermined period of signal；

Pulse number according to internal signal is obtained is carried out to the clock frequency type belonging to the input signal Differentiate.

5. clock frequency as claimed in claim 4 knows method for distinguishing, it is characterised in that the network sets For after receiving an input signal, on the basis of the input signal, obtain in the pre- of the input signal If the pulse number of the internal signal produced by the cycle includes：

The network equipment is after receiving an input signal, on the basis of the input signal, described detecting When first rising edge of input signal is reached, start to count the pulse of the internal high-frequency signal for producing；

Stop counting when the second rising edge for detecting the input signal is reached, obtain in the input The pulse number of the high-frequency signal in a cycle of signal.

6. clock frequency as claimed in claim 5 knows method for distinguishing, it is characterised in that the basis is obtained Pulse number to internal signal carries out differentiation to the clock frequency type belonging to the input signal and includes：

When the pulse number of the high-frequency signal is in the range of the 3rd predetermined number, then the input letter is judged Number for SDH clock frequency signal；

When the pulse number of the high-frequency signal is in the range of the 4th predetermined number, then the input letter is judged Number for global positioning system clock frequency signal.

7. clock frequency as claimed in claim 4 knows method for distinguishing, it is characterised in that the network sets For after receiving an input signal, on the basis of the input signal, obtain in the pre- of the input signal If the pulse number of the internal signal produced by the cycle includes：

The network equipment is after receiving an input signal, on the basis of the input signal, described detecting When the rising edge of input signal is reached, start to count the pulse of the internal high-frequency signal for producing；

Stop counting when the trailing edge for detecting the input signal is reached, obtain in the input signal Half period in the high-frequency signal pulse number.

8. clock frequency as claimed in claim 7 knows method for distinguishing, it is characterised in that the basis is obtained Pulse number to internal signal carries out differentiation to the clock frequency type belonging to the input signal and includes：

The high-frequency signal according to frequency N of the high-frequency signal and in the half period of the input signal Pulse number X, calculates frequency R=N/ (2*X) of the input signal；

When the frequency of the input signal is in the range of the first predeterminated frequency, then judge the input signal as The clock frequency signal of SDH；

When the frequency of the input signal is in the range of the second predeterminated frequency, then judge the input signal as The clock frequency signal of global positioning system.

9. a kind of device that clock frequency is recognized, it is characterised in that the device bag of the clock frequency identification Include：

Pulse number acquisition module, with produced by which for the network equipment after receiving an input signal On the basis of internal signal, the pulse number of the input signal in the predetermined period of the internal signal is obtained；

Type identification module, obtains the pulse number of input signal to belonging to the input signal for basis Clock frequency type differentiated.

10. the device that clock frequency as claimed in claim 9 is recognized, it is characterised in that the pulse Number acquisition module is additionally operable to, the network equipment after receiving an input signal, with the internal pulse per second (PPS) for producing On the basis of signal, when the first rising edge for detecting the pps pulse per second signal is reached, start to described defeated The pulse for entering signal is counted；Stop when the second rising edge for detecting the pps pulse per second signal is reached Count, obtain the pulse number of the input signal in a cycle of the pps pulse per second signal.

The device of 11. clock frequency identifications as claimed in claim 10, it is characterised in that the type Discrimination module is additionally operable to, and when the pulse number of the input signal is in the range of the first predetermined number, then sentences Clock frequency signal of the fixed input signal for SDH；When the pulse of the input signal Number then judges clock frequency of the input signal as global positioning system in the range of the second predetermined number Signal.

A kind of 12. devices of clock frequency identification, it is characterised in that the device of the clock frequency identification Including：

Acquisition module, on the basis of the input signal for the network equipment after receiving an input signal, Obtain the pulse number of the internal signal produced by the predetermined period of the input signal；

Discrimination module, for according to obtain the pulse number of internal signal to belonging to the input signal when Clock frequency type is differentiated.

The device of 13. clock frequency identifications as claimed in claim 12, it is characterised in that the acquisition Module is additionally operable to, and the network equipment after receiving an input signal, on the basis of the input signal, is being examined When measuring the first rising edge arrival of the input signal, start the pulse to the internal high-frequency signal for producing Counted；Stop counting when the second rising edge for detecting the input signal is reached, obtain in institute State the pulse number of the high-frequency signal in a cycle of input signal.

The device of 14. clock frequency identifications as claimed in claim 13, it is characterised in that the differentiation Module is additionally operable to, and when the pulse number of the high-frequency signal is in the range of the 3rd predetermined number, then judges institute State the clock frequency signal that input signal is SDH；When the pulse number of the high-frequency signal exists In the range of 4th predetermined number, then clock frequency signal of the input signal as global positioning system is judged.

The device of 15. clock frequency identifications as claimed in claim 12, it is characterised in that the acquisition Module is additionally operable to, and the network equipment after receiving an input signal, on the basis of the input signal, is being examined When measuring the rising edge arrival of the input signal, start to carry out the pulse of the internal high-frequency signal for producing Count；Stop counting when the trailing edge for detecting the input signal is reached, obtain in the input letter Number half period in the high-frequency signal pulse number.

The device of 16. clock frequency identifications as claimed in claim 15, it is characterised in that the differentiation Module is additionally operable to, high according to frequency N of the high-frequency signal and in the half period of the input signal The pulse number X of frequency signal, calculates frequency R=N/ (2*X) of the input signal；

When the frequency of the input signal is in the range of the first predeterminated frequency, then judge the input signal as The clock frequency signal of SDH；When the frequency of the input signal is in the second predeterminated frequency scope It is interior, then judge clock frequency signal of the input signal as global positioning system.