CN102355318A - Method and device for recognizing clock reference type - Google Patents
Method and device for recognizing clock reference type Download PDFInfo
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- CN102355318A CN102355318A CN2011102347963A CN201110234796A CN102355318A CN 102355318 A CN102355318 A CN 102355318A CN 2011102347963 A CN2011102347963 A CN 2011102347963A CN 201110234796 A CN201110234796 A CN 201110234796A CN 102355318 A CN102355318 A CN 102355318A
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Abstract
The invention discloses a method and device for recognizing a clock reference type. The method comprises the steps of: analyzing an input data code stream, and acquiring verification information carried by the data code stream under the condition of recognizing the frame header position of the data code stream; and comparing the acquired verification information and the preset verification information, and determining a clock reference in the data code stream as a line extraction clock under the condition that the acquired verification information is correct. According to the invention, the clock reference type can be automatically recognized without adopting a selection discrimination manner of combining a cable or joint with manual jumper wire switch settings.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of recognition methods and device of clock reference type.
Background technology
At present, the clock reference type that can import in the clock system has three kinds:
1, circuit extracts clock; Need from the track data code stream, extract clock signal; Transmitting terminal will include SSM (Synchronization Status Message; Synchronication status message) after information, line interface type, circuit extract the clock coding of data such as port numbers, service board frame-saw groove information and check register with 2.048MHZ, redispatches to receiving terminal; Receiving terminal parses data content from the track data code stream, and recovers line clock;
2, HZ (hertz) clock belongs to the square-wave signal of standard, mainly is divided into 2.048MHZ (E1) clock and 1.544MHZ (T1) clock;
3, BPS (baud rate) clock adopts HDB3 or B8ZS coded system, mainly is divided into 2.048MBPS (E1) clock and 1.544MBPS (T1) clock.
In the prior art, the method that adopts is to distinguish the benchmark type through cable or joint usually; Also have and adopt same cable and joint, adopt artificial jumper switch to select to distinguish the benchmark type simultaneously.But when adopting above-mentioned dual mode, circuit is the judgment standard type automatically, could the selection reference type and can only rely on manual work to carry out that wire jumper is provided with, thus cause the operating efficiency of clock system low excessively, increased human cost.
Summary of the invention
Main purpose of the present invention is to provide a kind of recognition methods and device of clock reference type, to address the above problem at least.
According to an aspect of the present invention, a kind of recognition methods of clock reference type is provided, has comprised: the data code flow to input is resolved, and under the situation of the frame head position of identifying data code flow, obtains the check information that data code flow carries; The check information that obtains is compared with preset check information, and under the correct situation of the check information of confirming to obtain, the clock reference in the specified data code stream is that circuit extracts clock.
Preferably, in the frame head position that can not identify data code flow or confirm also to comprise under the incorrect situation of the check information that obtains: obtain the number of cycles value that data code flow comprises in count cycle of current preset; Obtain numerical value normal period of signal mode coupling pre-configured and data code flow; A compare cycle numerical value and normal period a numerical value difference, during less than preset threshold value, confirm that clock reference is the HZ clock in difference.
Preferably, be not less than in difference under the situation of threshold value, this method also comprises: judge LIU (Line Interface Unit; Line interface unit) LOS (Lost Of Signal; Dropout) whether the read clock benchmark is not lost, if confirm that then clock reference is the BPS clock.
Preferably, the clock reference in the specified data code stream is that circuit extracts after the clock, also comprises: produce pulse signal in the frame head position, wherein, the frequency of pulse signal equals the frame rate of data code flow.
Preferably, after definite clock reference is the HZ clock, also comprise: select the corresponding divide ratio of signal mode with clock reference; Produce the 8KHZ clock according to divide ratio from the HZ clock division.
Preferably, after definite clock reference is the BPS clock, also comprise: LIU goes out the HZ clock from the BPS clock recovery, and produces the 8KHZ clock through frequency division.
Preferably; Before the data code flow of input is resolved; This method also comprises: use following coded system that clock reference is encoded, obtain data code flow: data 0 are sent with two identical data b it, and data 1 are sent with two different data b it.
According to a further aspect in the invention; A kind of recognition device of clock reference type is provided, has comprised: decoder module is used for the data code flow of input is resolved; Under the situation of the frame head position of identifying data code flow, obtain the check information that data code flow carries; First comparison module, the check information that is used for obtaining compares with preset check information, and under the correct situation of the check information of confirming to obtain, the clock reference in the specified data code stream is that circuit extracts clock.
Preferably, this device also comprises: first acquisition module is used to obtain the number of cycles value that data code flow comprises in count cycle of current preset; Second acquisition module is used to obtain numerical value normal period that signal mode pre-configured and data code flow mates; Second comparison module, be used for a compare cycle numerical value and normal period a numerical value difference, during less than preset threshold value, confirm that clock reference is the HZ clock in difference.
Preferably, this device also comprises: judge module is used to judge whether the read clock benchmark is not lost for the dropout (LOS) of line interface unit (LIU), if confirm that then clock reference is the BPS clock.
Through the present invention; The mode of clock reference type is judged and is discerned in employing voluntarily by circuit; Solved tradition with cable or joint; Adopt the mode of artificial jumper switch that the clock reference type is distinguished the troublesome poeration that causes, the problem of waste of manpower capital simultaneously, and then reached the effect of having heightened operating efficiency, having saved human capital.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart according to the recognition methods of the clock reference type of the embodiment of the invention;
Fig. 2 is the identification process figure of clock reference type according to the preferred embodiment of the invention;
Fig. 3 is the structural representation according to the recognition device of the clock reference type of the embodiment of the invention;
Fig. 4 is the structural representation according to a preferred embodiment of the embodiment of the invention;
Fig. 5 is the structural representation according to another preferred embodiment of the embodiment of the invention;
Fig. 6 is the preferred circuit block diagram that the clock reference types of devices according to the embodiment of the invention can adopt.
Embodiment
Hereinafter will with reference to the accompanying drawings and combine embodiment to describe the present invention in detail.Need to prove that under the situation of not conflicting, embodiment and the characteristic among the embodiment among the application can make up each other.
Fig. 1 is the flow chart according to the recognition methods of the clock reference type of the embodiment of the invention, and as shown in Figure 1, this method mainly may further comprise the steps (step S102-step S104):
Step S102 resolves the data code flow of input, under the situation of the frame head position of identifying data code flow, obtains the check information that data code flow carries;
In embodiments of the present invention; Can adopt decoder module that the data code stream is decoded; Generally speaking; Decoder module can be arranged on logical block inside; When carrying out decode operation, decoder module can also parse SSM (Synchronization Status Message, Synchronication status message) information.If can identify the frame head position of data code flow, whether the check information of then can judge separating out is correct, if can not discern, can judge that then clock reference is not that circuit extracts clock.
Step S104 compares check information and the preset check information that obtains, and under the correct situation of the check information of confirming to obtain, the clock reference in the specified data code stream is that circuit extracts clock.
In embodiments of the present invention, compare the back at check information that obtains and preset check information and find to confirm the check information that obtains also incorrect (that is, inconsistent), can judge that then clock reference is not that circuit extracts clock with preset check information.
Preferably, judging that the clock reference type is not after circuit extracts clock, can continue to judge that current clock reference is HZ (hertz) clock or BPS (baud rate) clock.For example:
In a preferred implementation of the embodiment of the invention; In the frame head position that can not identify data code flow or confirm under the incorrect situation of the check information that obtains; Can obtain the number of cycles value that data code flow comprises in count cycle of current preset earlier; Obtain numerical value normal period of signal mode coupling pre-configured and data code flow again; A compare cycle numerical value and normal period a numerical value difference; In difference during less than preset threshold value; Confirm that clock reference is the HZ clock; When if this difference is not less than threshold value, can continue then to judge that current clock reference is the BPS clock.
In another preferred implementation of the embodiment of the invention; Be not less than in above-mentioned difference under the situation of threshold value; Can judge LIU (Line Interface Unit; Line interface unit) LOS (Lost Of Signal; Dropout) whether the read clock benchmark is not lost; If confirm that then clock reference is the BPS clock.
In another preferred implementation of the embodiment of the invention, after identifying the clock reference type, can further extract operation to the clock reference of confirming, for example:
If 1 confirms that current clock reference is that circuit extracts clock, the frequency that can also produce signal in the frame head position equals the pulse signal of the frame rate of data code flow;
If 2 confirm that current clock reference is the HZ clock, can also select and the corresponding divide ratio of the signal mode of clock reference; Produce the 8KHZ clock according to divide ratio from the HZ clock division;
If 3 confirm that the present clock benchmark is the BPS clock, LIU can go out the HZ clock from the BPS clock recovery, and produces the 8KHZ clock through frequency division.
In practical application; Before the data code flow of input is resolved; At first to encode to the clock reference of input; For example; Can use following coded system that clock reference is encoded; Obtain data code flow: data 0 are sent with two identical data b it, and data 1 are sent with two different data b it.Adopt the advantage of such coded system to be; Data code flow behind the coding does not have DC component; And can the company of assurance 0 or connect at 1 o'clock the level upset is arranged, can transmit through transformer; And; Follow-up decoding is also fairly simple; Only need to confirm that which two bit is data,, confirm that if these two bit are different the actual reception data are 1 if judge that again these two bit are identical then definite actual reception data are 0.Generally speaking, can adopt frame structure that the data code stream is sent, wherein, the frequency of frame structure is 8KHZ.
With the preferred implementation among Fig. 2 said method is described in detail below:
Fig. 2 is the identification process figure of clock reference type according to the preferred embodiment of the invention, and as shown in Figure 2, this flow process mainly may further comprise the steps:
S201; Mode with data code flow after the benchmark input clock system is sent to logical block through comparator or LIU; The decoder module that is provided with in the logical block is at first decoded to the data of comparator input, resolves and obtains frame head position and check information (check register);
S202, logical block judges whether to discern the frame head positional information, if can not discern, execution in step S206 then, if can discern, execution in step S203 then;
S203 judges whether check information is correct, if correct, execution in step S204 then, if incorrect, execution in step S206 then;
S204, discerning this benchmark is that circuit extracts clock;
S205, and produce the pulse output that frequency equals Frame frequency (8KHZ) in the frame head position, as the benchmark of next stage phase-locked loop;
S206, whether the inner count value in decision logic unit meets preset range, if meet, execution in step S207 then, if do not meet, execution in step S209 then;
For example; In practical application; The cycle count value that two kinds of input references under the pattern are confirmed according to the E1 pattern (clock signal of input is 2.048MHZ) or the T1 pattern (clock signal of input is 1.544MHZ) of inside setting in the decision logic unit; For example; Count cycle is when being 250us; Cycle count value under the E1 pattern is 512, and the cycle count value under the T1 pattern is 386, and whether count value and 512 or 386 the difference in cycle of judging current benchmark be less than threshold value.
S207, discerning this benchmark is the HZ clock;
Generally speaking; Because frequency difference between local crystal oscillator and the input reference and circuit disturb; Allow the error in several cycles; Count value all can be thought the HZ clock within right value positive and negative deviation several values, certainly; Count cycle can be selected voluntarily; Judge that count value is to judge that continuously arbitrary count cycle inside counting value judges that then this benchmark is not the HZ clock not in claimed range.
S208 when this benchmark of identification is the HZ clock, again according to E1/T1 pattern position, selects suitable divide ratio, and frequency division produces the 8KHZ clock from the HZ clock, as the benchmark of next stage phase-locked loop;
S209 judges whether the LOS signal detect LIU shows that input signal do not lose, if, execution in step S210 then, if not, process ends then;
S210, discerning this benchmark is the BPS clock;
S211 uses 256 (E1 patterns) or 193 (T1 patterns), and as the divide ratio of LIU line-recovered clock, frequency division produces the benchmark of 8KHZ clock as the next stage phase-locked loop.
When above condition does not all satisfy, illustrate that outside no benchmark input or input reference do not meet system requirements, logical block will not exported the 8KHZ benchmark and give the next stage phase-locked loop.
In practical application, during the more benchmark type of input, the present invention also can do suitable function expansion in the system, like the data code flow of compatibility input several data form, and identification automatically; Increase the HZ clock of other frequencies of input, the counting criterion of corresponding another scope of increase; Import the BPS clock of other frequencies, select corresponding LIU chip etc.
Adopt the recognition methods of the clock reference type that the foregoing description provides, need not carry out under the situation that artificial wire jumper is provided with identification reference type automatically.
Fig. 3 is the structural representation according to the recognition device of the clock reference type of the embodiment of the invention; As shown in Figure 3; This device is in order to realize the recognition methods of the clock reference type that the foregoing description provides, and this device mainly comprises: the decoder module 10 and first comparison module 20.Wherein, decoder module 10 is used for the data code flow of input is resolved, and under the situation of the frame head position of identifying data code flow, obtains the check information that data code flow carries; First comparison module 20 is connected to decoder module 10, and the check information that is used for obtaining compares with preset check information, and under the correct situation of the check information of confirming to obtain, the clock reference in the specified data code stream is that circuit extracts clock.The said apparatus that provides through present embodiment; The frame head of data code flow that can be through 10 pairs of inputs of decoder module is discerned; Under the situation that identifies the frame head position; Obtain checking information; Differentiate through 20 pairs of check informations of first comparison module; Under the correct situation of check information, the clock reference that can identify the data code flow employing of input is that circuit extracts clock, thereby can realize that circuit extracts the automatic identification of clock.
Fig. 4 is the structural representation according to a preferred embodiment of the embodiment of the invention, and as shown in Figure 4, this device can also comprise: first acquisition module 30, second acquisition module 40 and second comparison module 50.Wherein, first acquisition module 30 is connected to first comparison module 20, is used to obtain the number of cycles value that data code flow comprises in count cycle of current preset; Second acquisition module 40 is connected to first acquisition module 30, is used to obtain numerical value normal period of signal mode coupling pre-configured and data code flow; Second comparison module 50 is connected to second acquisition module 40, be used for a compare cycle numerical value and normal period a numerical value difference, during less than preset threshold value, confirm that clock reference is the HZ clock in difference.Through the preferred embodiment, can further automatically identify the HZ clock.
Fig. 5 is the structural representation according to another preferred embodiment of the embodiment of the invention; As shown in Figure 5; This device can also comprise: judge module 60; Be connected to second comparison module 50; Be used to judge whether the read clock benchmark is not lost for the synchronization loss LOS of line interface unit LIU; If confirm that then clock reference is the BPS clock.Through the preferred embodiment, can further automatically identify the BPS clock.
The preferred circuit block diagram that the clock reference types of devices of the embodiment of the invention of showing Fig. 6 can adopt need to prove that in practical application, said apparatus all can adopt circuit as shown in Figure 6.In this circuit diagram, reference signal can divide two-way to import LIU and comparator simultaneously through behind the transformer, and LIU and comparator export reference signal to logical block again.LIU can recover output HZ clock through circuit with the E1/T1 BPS clock of input; Comparator can change into the differential signal of input the output of TTL signal; Make input reference meet the requirement of logical block to incoming level, logical block inside carries out type identification to reference signal and produces the 8KHZ benchmark exporting the next stage phase-locked loop to and advancing horizontal lock then.Wherein, the resistance of comparator front end plays the main buffer action that rises.
The clock reference types of devices that adopts the foregoing description to provide need not carried out artificial jumper switch setting, can automatic identification reference type.
From above description, can find out that the present invention has realized following technique effect: need not carry out artificial jumper switch setting; Get final product automatic identification reference type, do not need the wire jumper setting, automatically the identification reference type; Thereby reached the saving human cost, the effect of increasing work efficiency.
Obviously; Those skilled in the art should be understood that; Above-mentioned each module of the present invention or each step can realize with the general calculation device; They can concentrate on the single calculation element; Perhaps be distributed on the network that a plurality of calculation element forms; Alternatively; They can be realized with the executable program code of calculation element; Thereby; They can be stored in the storage device and carry out by calculation element; And in some cases; Can carry out step shown or that describe with the order that is different from here; Perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the recognition methods of a clock reference type is characterized in that, comprising:
Data code flow to input is resolved, and under the situation of the frame head position of identifying said data code flow, obtains the check information that said data code flow carries;
The said check information that obtains is compared with preset check information, under the correct situation of the said check information of confirming to obtain, confirm that the clock reference in the said data code flow is that circuit extracts clock.
2. method according to claim 1 is characterized in that, in the said frame head position that can not identify said data code flow or under the incorrect situation of confirming to obtain of said check information, also comprises:
Obtain the number of cycles value that said data code flow comprises in count cycle of current preset;
Obtain numerical value normal period of signal mode coupling pre-configured and said data code flow;
More said number of cycles value and said normal period a numerical value difference, during less than preset threshold value, confirm that said clock reference is the HZ clock in said difference.
3. method according to claim 2 is characterized in that, is not less than in said difference under the situation of said threshold value, and said method also comprises:
Whether the dropout LOS that judges line interface unit LIU shows that said clock reference do not lose, if confirm that then said clock reference is the BPS clock.
4. method according to claim 1 is characterized in that, the clock reference in confirming said data code flow is that circuit extracts after the clock, also comprises:
Produce pulse signal in said frame head position, wherein, the frequency of said pulse signal equals the frame rate of said data code flow.
5. method according to claim 2 is characterized in that, after definite said clock reference is said HZ clock, also comprises:
Select the corresponding divide ratio of signal mode with said clock reference;
Produce the 8KHZ clock according to said divide ratio from said HZ clock division.
6. method according to claim 3 is characterized in that, after definite said clock reference is said BPS clock, also comprises:
Said LIU goes out the HZ clock from said BPS clock recovery, and produces the 8KHZ clock through frequency division.
7. according to each described method among the claim 1-6, it is characterized in that before the said data code flow of input was resolved, said method also comprised: use following coded system that said clock reference is encoded, obtain said data code flow:
Data 0 are sent with two identical data b it, and data 1 are sent with two different data b it.
8. the recognition device of a clock reference type is characterized in that, comprising:
Decoder module is used for the data code flow of input is resolved, and under the situation of the frame head position of identifying said data code flow, obtains the check information that said data code flow carries;
First comparison module, the said check information that is used for obtaining compares with preset check information, under the correct situation of the said check information of confirming to obtain, confirms that the clock reference in the said data code flow is that circuit extracts clock.
9. device according to claim 8 is characterized in that, also comprises:
First acquisition module is used to obtain the number of cycles value that said data code flow comprises in count cycle of current preset;
Second acquisition module is used to obtain numerical value normal period that signal mode pre-configured and said data code flow mates;
Second comparison module, be used for more said number of cycles value and said normal period a numerical value difference, during less than preset threshold value, confirm that said clock reference is the HZ clock in said difference.
10. device according to claim 9 is characterized in that, also comprises:
Whether judge module, the dropout LOS that is used to judge line interface unit LIU show that said clock reference do not lose, if confirm that then said clock reference is the BPS clock.
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| CN103532695A (en) * | 2012-06-28 | 2014-01-22 | 特拉博斯股份有限公司 | A method and a device for controlling a clock signal generator |
| CN105553596A (en) * | 2015-12-22 | 2016-05-04 | 大唐电信（成都）信息技术有限公司 | Synchronous clock device output interface and type configuration method thereof |
| CN106559156A (en) * | 2015-09-29 | 2017-04-05 | 中兴通讯股份有限公司 | The method and apparatus of clock frequency identification |
| CN112910902A (en) * | 2021-02-04 | 2021-06-04 | 浙江大华技术股份有限公司 | Data analysis method and device, electronic equipment and computer readable storage medium |
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| CN106559156A (en) * | 2015-09-29 | 2017-04-05 | 中兴通讯股份有限公司 | The method and apparatus of clock frequency identification |
| CN105553596A (en) * | 2015-12-22 | 2016-05-04 | 大唐电信（成都）信息技术有限公司 | Synchronous clock device output interface and type configuration method thereof |
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