CN106558622A - A kind of STI diodes for ESD protection - Google Patents
A kind of STI diodes for ESD protection Download PDFInfo
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- CN106558622A CN106558622A CN201510615429.6A CN201510615429A CN106558622A CN 106558622 A CN106558622 A CN 106558622A CN 201510615429 A CN201510615429 A CN 201510615429A CN 106558622 A CN106558622 A CN 106558622A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 74
- 239000000463 material Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000407 epitaxy Methods 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- SKYGTJFKXUWZMD-UHFFFAOYSA-N ac1l2n4h Chemical compound [Co].[Co] SKYGTJFKXUWZMD-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- UPIXZLGONUBZLK-UHFFFAOYSA-N platinum Chemical compound [Pt].[Pt] UPIXZLGONUBZLK-UHFFFAOYSA-N 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of STI diodes for ESD protection, is related to technical field of semiconductors.Including：Semiconductor substrate, the well region with the first conduction type in the Semiconductor substrate；Multiple first fins for extending in a first direction in the Semiconductor substrate, are formed with each described first fin and extend along the first direction and the first doped region with the first conduction type；Some second fins extended between the plurality of first fin and along the first direction, are formed with each described second fin and extend along the first direction and the second doped region with the second conduction type；The isolation structure in the Semiconductor substrate between the plurality of first fin and some second fins.The STI diodes of the present invention, which raises the area efficiency of device so that metal silicide uniformity is more preferable, so that ESD device has higher secondary breakdown current and less conducting resistance (Ron).
Description
Technical field
The present invention relates to technical field of semiconductors, is used for ESD protection in particular to a kind of
STI diodes.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is not mainly by
What the disconnected size for reducing IC-components was realized with improving its speed.At present, due to
In pursuing high device density, high-performance and low cost, semi-conductor industry has advanced to nanotechnology
Process node.However, this progressive trend can produce unfavorable shadow to the reliability of end product
Ring：In technical field of semiconductors, static discharge (ESD) phenomenon is to integrated circuit one
Big to threaten, which can puncture integrated circuit and semiconductor element, promote component ageing, reduce life
Finished products rate.Therefore, with the continuous reduction of manufacture of semiconductor process, ESD protection sets
Meter becomes more and more challenging and difficulty in nano level CMOS technology.
The capacity load of ESD device is a basic design parameters.With gate control diode (such as
Shown in Figure 1A) to compare, the parasitic capacitance of STI diodes (as shown in Figure 1B) reduces 50%,
So that STI diodes become the preferred diode type for frequency applications.
At present, as shown in Figure 2 A and 2 B, its subject matter is leakage to the structure of STI diodes
, in epitaxial layer bottom, fin is very little with the land of epitaxial layer for the current crowding of pole side,
Therefore discharge capability is by being limited.STI diodes are only in contact groove as shown in Figure 2 A
(CCT) metal silicide (not shown) is formed below on exposed part fin top surface, because
The shared area on fin of this metal silicide is less than very so that conducting resistance (Ron)
It is too big, and the device secondary breakdown current (It2) that TLP is measured is too little.
In order to obtain larger discharge current, a kind of method is to improve the number of fin, and this
Defect produced by method is, if the uniformity of fin is bad and the uniformity of silicide not
Good, device is easy to puncture on some or some fins.Failure is usually located at Li definition
Local silicide regions.The little silicide regions limited by Li generate higher spreading resistance
Higher electric current heterogeneity, these cause the local damage under high-current pressure.And
Electric current in device with wide metal suicide structure is more uniform than meeting.
Before local temperature is significantly increased, the tool of the STI diodes with wide silicide structural
There is the critical diode current that comparison is high.Due to high with more uniform CURRENT DISTRIBUTION and comparison
Critical diode current, wide silicide structural can strengthen the two of ESD protection diodes
Secondary breakdown current (It2).
Therefore, it is necessary to a kind of new STI diodes are proposed, to strengthen FinFET
Electrostatic discharge (ESD) protection performance.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be concrete real
Further describe in applying mode part.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme required for protection, less
Mean the protection domain for attempting to determine technical scheme required for protection.
For the deficiencies in the prior art, the embodiment of the present invention one provides a kind of for ESD protection
STI diodes, including：
Semiconductor substrate, the trap with the first conduction type in the Semiconductor substrate
Area；
Multiple first fins for extending in a first direction in the Semiconductor substrate, each
It is formed with first fin and extends and with the first conduction type along the first direction
First doped region；
Some second extended between the plurality of first fin and along the first direction
Fin, is formed with each described second fin and extend along the first direction and have second to lead
Second doped region of electric type；
The quasiconductor between the plurality of first fin and some second fins
Fleet plough groove isolation structure on substrate.
Further, it is formed with outside first that the first direction extends on first fin
Prolong layer, the second epitaxial layer extended along the first direction is formed with second fin.
Further, first epitaxial layer is completely covered the top surface of first fin, and described
Two epitaxial layers are completely covered the top surface of second fin.
Further, first conduction type is p-type, and second conduction type is N-type,
First epitaxial layer is SiGe, and second epitaxial layer is silicon epitaxy layer.
Further, first conduction type is N-type, and second conduction type is p-type,
First epitaxial layer is silicon epitaxy layer, and second epitaxial layer is SiGe.
Further, on whole top surfaces of each described first fin and each second fin
It is formed with the metal silicide extended along the first direction.
Further, the material of the fleet plough groove isolation structure includes silica material.
Further, also include distinguishing with the first doped region each described and each described second doping
The multiple contacts not being connected.
Further, interlayer dielectric layer is formed between the plurality of contact.
In sum, the STI for FinFET ESD-protection structure of the invention
Diode, which raises the area efficiency (area efficient) of device so that metal silicide
Uniformity more preferably so that ESD device have higher secondary breakdown current (It2) and
Less conducting resistance (Ron), further increases the ESD protection performance of device.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A is a kind of generalized section of existing gate control diode；
Figure 1B is a kind of generalized section of existing STI diodes；
Fig. 2A is a kind of plane figure of existing STI diodes；
Existing a kind of STI diodes that Fig. 2 B are obtained by correspondence Fig. 2A section lines
Generalized section；
A kind of STI diodes for ESD protection of Fig. 3 A for one embodiment of the present of invention
Plane figure；
The one of one embodiment of the present of invention that Fig. 3 B are obtained by corresponding diagram 3A section line
Plant the generalized section of the STI diodes for ESD protection.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without the need for one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, for some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments
Entirely, and those skilled in the art be will fully convey the scope of the invention to.In the accompanying drawings,
In order to clear, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from start to finish
Icon note represents identical element.
It should be understood that work as element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, and
It is adjacent, be connected or coupled to other elements or layer, or there may be element between two parties or layer.
Conversely, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then there is no element between two parties or layer.Should
Understand, although can using term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, without departing from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience here and used from
And an element or feature shown in figure are described with other elements or the relation of feature.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and operate
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under which " element or feature will be orientated
Be other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " may include upper and lower two orientations.Device can additionally be orientated and (be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When here is used, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " including ", when using in this specification, determine the feature,
The presence of integer, step, operation, element and/or part, but be not excluded for it is one or more its
The presence or addition of its feature, integer, step, operation, element, part and/or group.
When here is used, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view is describing inventive embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or the change caused by tolerance from shown shape.Therefore, embodiments of the invention should not limit to
In the given shape in area shown here, but including inclined due to for example manufacturing caused shape
Difference.For example, be shown as the injection region of rectangle its edge generally there is circle or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
The surface passed through when carrying out by the disposal area and injection can be caused by injecting the disposal area for being formed
Between area in some injection.Therefore, the area for showing in figure is substantially schematic, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, so
And in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Below, reference picture 3A and Fig. 3 B are describing the one of one embodiment of the present of invention proposition
Plant the STI diodes for ESD protection.Wherein, Fig. 3 A are one embodiment of the present of invention
A kind of STI diodes for ESD protection plane figure；Fig. 3 B are corresponding diagram
One embodiment of the present of invention that 3A section lines are obtained it is a kind of for ESD protection
The generalized section of STI diodes.
Exemplarily, the STI diodes for ESD protection of one embodiment of the present of invention,
Including：
Semiconductor substrate 100, specifically, the Semiconductor substrate 100 can be following being carried
To material at least one：Silicon is laminated on silicon, silicon-on-insulator (SOI), insulator
(SSOI) SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator,
And germanium on insulator (GeOI) etc. (SiGeOI).
It is also formed with the well region with the first conduction type in Semiconductor substrate 100, described first
Conduction type is N-type or p-type, for example, as shown in Figure 3A, in Semiconductor substrate 100
It is formed with P type trap zone.
As shown in Figure 3A, also include in the Semiconductor substrate 100 in the first direction
The multiple first fin 101a for extending, are formed with along described in each described first fin 101a
First direction extends and the first doped region with the first conduction type.Exemplarily, described
One conduction type is p-type, and first doped region is p-type doped region, it is preferred that first mixes
Miscellaneous area is P+ doped regions.Wherein, the area of the first doped region is interior with the first fin in a first direction
The area of piece 101a overlaps, and whole first fin 101a is used as the first doped region.
If also including between the plurality of first fin 101a and extending in a first direction
Dry second fin 101b, is formed with along the first direction in each described second fin 101b
Extend and the second doped region with the second conduction type.Exemplarily, second conductive-type
Type is N-type, and second doped region is n-type doping area, it is preferred that the second doped region is
N+ doped regions.Wherein, the area of the second doped region is interior with the second fin 101b in a first direction
Area overlap, whole second fin 101b be used as the second doped region.
Wherein, the material of the first fin 101a and the second fin 101b can be silicon, germanium
Or the semi-conducting material such as germanium silicon.Its shape can approximate ground be the length vertical with Semiconductor substrate
Cube structure or other stereochemical structures.Exemplarily, the first fin 101a and the second fin
The forming method of piece 101b can be：Form semiconductor material layer first on a semiconductor substrate,
The well region with the first conduction type, the semiconductor material layer have been formed in Semiconductor substrate
Then can be formed on the semiconductor material layer with Si, SiGe, Ge or III-V material
The mask layer of patterning, such as photoresist mask layer, the photoresist mask layer define described
The width of the first fin 101a and the second fin 101b, length and position etc., then with institute
It is semiconductor material layer described in mask etch to state photoresist mask layer, to form first fin
101a and the second fin 101b, then removes the photoresist mask layer, removes the photoetching
The method of glue mask layer can be oxidative ashing method.
In another example, the formation side of the first fin 101a and the second fin 101b
Method can also be：Semiconductor substrate is provided, is formed with Semiconductor substrate conductive with first
The well region of type, forms the mask layer of patterning, such as photoresist mask on a semiconductor substrate
Layer, the photoresist mask layer define the first fin 101a's and the second fin 101b
Width, length and position etc., then with the photoresist mask layer as mask etch described in half
Conductor substrate, to form the first fin 101a and the second fin 101b, then removes institute
State photoresist mask layer.
It should be noted that the forming method of the first fin 101a and the second fin 101b
It is merely exemplary, it is not limited to said method.Each first fin and the second fin tool
There is the width and length being substantially the same.
Exemplarily, two the second fin 101b are located between four the first fin 101a, example
Such as, every side of two the second fin 101b is two the first fin 101a, naturally it is also possible to
For side be first fin, opposite side be three the first fins, above-mentioned first fin and
Putting in order for second fin be only exemplarily, as long as so that the both sides of the second fin are respectively formed
Other for having the first fin are suitably sequentially readily adaptable for use in the present invention.
Can be by carrying out different types of mixing to the first fin 101a and the second fin 101b respectively
The ion implanting of impurity (p type impurity or N-type impurity), forms the first doped region and
Two doped regions, therefore not to repeat here.
The STI diodes of the present invention are also included positioned at the plurality of first fin 101a and described
The isolation structure 102 in the Semiconductor substrate 100 between some second fin 101b.
Fleet plough groove isolation structure (STI) 102 is formed with Semiconductor substrate 100.Usual shallow trench
The material of isolation structure 102 mainly includes silica material, can pass through chemical vapor deposition, thing
The methods such as physical vapor deposition, magnetron sputtering are formed, exemplarily, fleet plough groove isolation structure 102
Top surface can be less than fin top surface.
Further, it is formed with the first fin 101a and extends along the first direction
The first epitaxial layer 103a, be formed with along the first direction on the second fin 101b
The the second epitaxial layer 103b for extending.It is preferred that the first epitaxial layer 103a is completely covered institute
The top surface of the first fin 101a is stated, the second epitaxial layer 103b is completely covered second fin
The top surface of piece 101b.By epitaxial layer being formed on whole fin, can dramatically increase epitaxial layer
With the contact area of fin, increase the relieving capacity of its electrostatic induced current.
In one example, as shown in Figure 3 B, first conduction type is p-type, described
It is P+ doped regions that second conduction type is N-type, i.e. the first doped region, and the second doped region is N+
Doped region, correspondingly, the first epitaxial layer 103a is SiGe, and SiGe is used as compressive stress layer.
The second epitaxial layer 103b be silicon epitaxy layer, such as SiC, SiC is used as tension layer etc..
In another example, first conduction type be N-type, second conductive-type
Type is p-type, first epitaxial layer be silicon epitaxy layer, such as SiC, SiC is used as tension
Layer etc., second epitaxial layer are SiGe, and SiGe is used as compressive stress layer.
Further, in each described first fin 101a and each described second fin 101b
Whole top surfaces on be formed with along the first direction extend metal silicide 105.Due to
Metal silicide is formed on whole fin, therefore, the uniformity of metal silicide is more preferable so that
Conducting resistance (Ron) is less.And then prevent device from puncturing on some or some fins,
Improve the reliability of device.
The metal silicide 105 can be formed using any method well known to those skilled in the art
(silicide) region.For example, first, as shown in Figure 3A, the first fin of exposure and the are formed
The contact groove 104 (CCT) of the top surface of two fins, then to deposited metal in contact groove 104
Layer, which can include the material of nickel (nickel), titanium, cobalt (cobalt) and platinum (platinum) or its combination
Material.Then substrate is heated, causes metal level that silicification, the first fin occur with the silicon layer under which
105 region of metal silicide on piece and the second fin surface thus formed.It is then used by erodable
Metal level, but the not etchant in attack metal disilicide layer region, unreacted metal level is removed
Go.Further, the metal silicide 105 is located at the first epitaxial layer 103a and institute
State on the surface of the second epitaxial layer 103b, its forming method can be：Form contact groove 104
The surface of the first epitaxial layer 103a and the second epitaxial layer 103b is exposed, in contact groove
In 104 after filler metal layer, under conditions of heating, metal and the first epitaxial layer 103a and
There is silicification in the second epitaxial layer 103b, and form metal silicide 105.
In one example, STI diodes of the invention also include and the first doping each described
Multiple contacts 106 that area and each described second doped region are respectively connected with.The plurality of contact
Can by being formed to filler metal material in contact groove (CCT) 104, or can also be
Other methods are formed, the plurality of contact 106 can for copper metal interconnection structure, tungsten plug etc.,
Interlayer dielectric layer is also formed between 100, multiple contacts 106 on the semiconductor substrate
107, interlayer dielectric layer 107 can use such as SiO2, fluorocarbon (CF), carbon dope oxygen
SiClx (SiOC), or carbonitride of silicium (SiCN) etc..
As shown in the arrow in Fig. 3 B, for the STI diodes of the present invention, its electric current can be with
The P+ doped regions of its both sides are separately flowed into from N+ doped regions and releasing for ESD electric currents is realized.
In sum, the STI for FinFET ESD-protection structure of the invention
Diode, which raises the area efficiency (area efficient) of device so that metal silicide
Uniformity more preferably so that ESD device have higher secondary breakdown current (It2) and
Less conducting resistance (Ron), further increases the ESD protection performance of device.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, teaching of the invention can also be made more kinds of modifications and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (9)
1. a kind of STI diodes for ESD protection, including：
Semiconductor substrate, the trap with the first conduction type in the Semiconductor substrate
Area；
Multiple first fins for extending in a first direction in the Semiconductor substrate, each
It is formed with first fin and extends and with the first conduction type along the first direction
First doped region；
Some second extended between the plurality of first fin and along the first direction
Fin, is formed with each described second fin and extend along the first direction and have second to lead
Second doped region of electric type；
The quasiconductor between the plurality of first fin and some second fins
Fleet plough groove isolation structure on substrate.
2. STI diodes according to claim 1, it is characterised in that described
The first epitaxial layer extended along the first direction is formed with one fin, in second fin
On be formed with along the first direction extend the second epitaxial layer.
3. STI diodes according to claim 2, it is characterised in that described first
Epitaxial layer is completely covered the top surface of first fin, and second epitaxial layer is completely covered described
The top surface of the second fin.
4. STI diodes according to claim 2, it is characterised in that described first
Conduction type is p-type, and second conduction type is N-type, and first epitaxial layer is SiGe,
Second epitaxial layer is silicon epitaxy layer.
5. STI diodes according to claim 2, it is characterised in that described first
Conduction type is N-type, and second conduction type is p-type, and first epitaxial layer is silicon
Epitaxial layer, second epitaxial layer are SiGe.
6. STI diodes according to claim 1, it is characterised in that in each institute
It is formed with along the first party on the whole top surfaces for stating the first fin and each second fin
To the metal silicide for extending.
7. STI diodes according to claim 1, it is characterised in that the shallow ridges
The material of recess isolating structure includes silica material.
8. STI diodes according to claim 1, it is characterised in that also include with
Multiple contacts that each described first doped region and each described second doped region are respectively connected with.
9. STI diodes according to claim 1, it is characterised in that described many
Interlayer dielectric layer is formed between individual contact.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510615429.6A CN106558622B (en) | 2015-09-24 | 2015-09-24 | STI diode for ESD protection |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510615429.6A CN106558622B (en) | 2015-09-24 | 2015-09-24 | STI diode for ESD protection |
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| CN106558622A true CN106558622A (en) | 2017-04-05 |
| CN106558622B CN106558622B (en) | 2020-04-07 |
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| CN201510615429.6A Active CN106558622B (en) | 2015-09-24 | 2015-09-24 | STI diode for ESD protection |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878541A (en) * | 2017-05-08 | 2018-11-23 | 中芯国际集成电路制造(上海)有限公司 | Fin type diode and its manufacturing method |
| CN109216470A (en) * | 2017-07-03 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110518008A (en) * | 2018-05-22 | 2019-11-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD protective device and preparation method thereof, electronic device |
| CN114709210A (en) * | 2022-06-07 | 2022-07-05 | 深圳市晶扬电子有限公司 | Low clamping voltage electrostatic protection device suitable for nanoscale FinFET (field effect transistor) process |
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| KR20130081184A (en) * | 2012-01-06 | 2013-07-16 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Io esd device and methods for forming the same |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
| EP2770538A1 (en) * | 2013-02-25 | 2014-08-27 | Imec | Fin type semiconductor structure suitable for producing esd protection device |
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2015
- 2015-09-24 CN CN201510615429.6A patent/CN106558622B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20130081184A (en) * | 2012-01-06 | 2013-07-16 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Io esd device and methods for forming the same |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
| EP2770538A1 (en) * | 2013-02-25 | 2014-08-27 | Imec | Fin type semiconductor structure suitable for producing esd protection device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878541A (en) * | 2017-05-08 | 2018-11-23 | 中芯国际集成电路制造(上海)有限公司 | Fin type diode and its manufacturing method |
| CN109216470A (en) * | 2017-07-03 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109216470B (en) * | 2017-07-03 | 2021-08-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110518008A (en) * | 2018-05-22 | 2019-11-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD protective device and preparation method thereof, electronic device |
| CN114709210A (en) * | 2022-06-07 | 2022-07-05 | 深圳市晶扬电子有限公司 | Low clamping voltage electrostatic protection device suitable for nanoscale FinFET (field effect transistor) process |
| CN114709210B (en) * | 2022-06-07 | 2022-09-02 | 深圳市晶扬电子有限公司 | Low clamping voltage electrostatic protection device suitable for nanoscale FinFET (field effect transistor) process |
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| Publication number | Publication date |
|---|---|
| CN106558622B (en) | 2020-04-07 |
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