CN106558571A - A kind of ESD layout structures, electronic installation - Google Patents
A kind of ESD layout structures, electronic installation Download PDFInfo
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Abstract
The present invention relates to a kind of ESD layout structures, electronic installation.The ESD layout structures, including：First doping type well region；First doping type fin array, above the first doping type well region, including some rows the first doping type fin；Fin diode array, above the first doping type well region, including some row fin diodes, in the fin diode, the bottom of fin is the first doping type, and the top of the fin is the second doping type；Wherein, the first doping type fin array and fin diode array interval setting arranged side by side, and the first doping type fin and the interlaced setting of fin diode described in every a line described in per a line.ESD layout structures of the present invention can further improve the robustness of the ESD structures, reduce the generation of defect.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of ESD layout structures, electronics
Device.
Background technology
With the continuous development of semiconductor technology, in order to improve the performance of device, need constantly to reduce integrated
The size of circuit devcie, with the continuous diminution of cmos device size, promotes three dimensional design such as fin
The development of field-effect transistor (FinFET).
Relative to existing planar transistor, the FinFET is in raceway groove control and reduces short channel
The aspects such as effect have more superior performance；Planar gate is arranged above the raceway groove, and
Grid described in FinFET is arranged around the fin, therefore can control electrostatic from three faces, in electrostatic
The performance of control aspect is also more prominent.
But internal structure is caused in electrostatic leakage ESD while integrated morphology performance and integrated level is improved
Impact to be easier temporarily to be damaged, ESD refers to static discharge (Electrostatic Discharge, abbreviation
ESD)。
The purpose of design of esd protection structure seek to the discharge path for avoiding work structuring from becoming ESD and
Damaged, it is ensured that the ESD occurred between any two chip pin, having suitable low-resistance to bypass will
ESD electric currents introduce power line.This low-resistance bypass not only will can absorb ESD electric currents, will also clamper work
Make the voltage of structure, prevent work structuring to be damaged due to voltage overload.This structure path has been also needed to
Good job stability, can when ESD occurs quick response, but also can not be to chip normal work
Structure has an impact.
ESD generally from shallow trench isolating diode type in FinFET is protected as ESD
Structure.Fin is degenerated due to fin structure with reference to the performance of ESD, wherein ESD electric currents need through
The fin structure of these narrow in cross-section and realize electric discharge, this is easy to cause local defect, so that ESD
Robustness be deteriorated, reduce device performance.
Therefore need to be improved the current ESD, to solve exist in current FinFET
Problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be in specific embodiment
Further describe in part.The Summary of the present invention is not meant to attempt to limit institute
The key feature and essential features of claimed technical scheme, more do not mean that attempt determine it is wanted
Seek the protection domain of the technical scheme of protection.
The invention provides a kind of ESD layout structures, including：
First doping type well region；
First doping type fin array, above the first doping type well region, including some rows
First doping type fin；
Fin diode array, above the first doping type well region, including some row fins two
Pole pipe, in the fin diode, the bottom of fin is the first doping type, and the top of the fin is the
Two doping types；
Wherein, the first doping type fin array and fin diode array interval setting arranged side by side,
And the first doping type fin and the interlaced setting of fin diode described in every a line described in per a line.
Alternatively, the ESD layout structures still further comprise fleet plough groove isolation structure, the shallow trench
Isolation structure is located at the top of the first doping type well region and partly covers the first doping type fin
Chip arrays and the fin diode array.
Alternatively, the height of the fleet plough groove isolation structure is completely covered described in the fin diode
The part of one doping type.
Alternatively, often go the fin diode centrage and the first doping type fin described in two rows it
Between fleet plough groove isolation structure centrage on the same line.
Alternatively, in the lower section of the first doping type fin array and the fin diode array also
Contact hole array is respectively formed with, to form electrical connection respectively.
Alternatively, the ESD layout structures still further comprise Semiconductor substrate, mix positioned at described first
The lower section of miscellaneous type well region.
Alternatively, first doping type adulterates for p-type, and second doping type is n-type doping.
Alternatively, first doping type is n-type doping, and second doping type is that p-type is adulterated.
Present invention also offers a kind of electronic installation, including above-mentioned ESD layout structures.
In order to solve problems of the prior art, there is provided a kind of present invention is in order to solve prior art
Present in problem, there is provided a kind of ESD layout structures, the ESD structures be fin diode-like
Type, wherein, the ESD structures include the first doping type fin and fin diode array and each
Row the first doping type fin and the interlaced setting of fin diode described in every a line, by described
Need from fin diode (N+/PW) to the first doping type fin when ESD current discharges are set
(P+/PW) robustness of the ESD structures through longer distance, can be further improved, is reduced
The generation of defect.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Show in accompanying drawing
Embodiments of the invention and its description are gone out, for explaining the device and principle of the present invention.In the accompanying drawings,
Fig. 1 is that the structure of ESD layout structures in FinFET described in embodiments of the present invention is shown
It is intended to；
Profiles of the Fig. 2 for ESD layout structures in another FinFET in embodiments of the present invention,
Wherein A is the structural representation of the first doping type fin；Structural representations of the A for fin diode.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more thoroughly
Understand.It is, however, obvious to a person skilled in the art that the present invention can be without the need for one
Or multiple these details and be carried out.In other examples, in order to avoid obscuring with the present invention,
For some technical characteristics well known in the art are not described.
It should be appreciated that the present invention can be implemented in different forms, and should not be construed as being limited to this
In the embodiment that proposes.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will be originally
The scope of invention fully passes to those skilled in the art.In the accompanying drawings, in order to clear, Ceng He areas
Size and relative size may be exaggerated.Same reference numerals represent identical element from start to finish.
It should be understood that work as element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " coupling
Close " other elements or during layer, which can directly on other elements or layer, adjacent thereto, connection
Or other elements or layer are coupled to, or there may be element between two parties or layer.Conversely, when element is claimed
For " on directly existing ... ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other units
When part or layer, then there is no element between two parties or layer.Although it should be understood that can using term first, the
2nd, the various elements of the third description, part, area, floor and/or part, these elements, part, area,
Layer and/or part should not be limited by these terms.These terms be used merely to distinguish element, part,
Area, floor or part and another element, part, area, floor or part.Therefore, without departing from the present invention
Under teaching, the first element discussed below, part, area, floor or part be represented by the second element,
Part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ",
" ... on ", " above " etc., can describe for convenience here and be used so as to describe in figure
A shown element or feature and other elements or the relation of feature.It should be understood that except shown in figure
Orientation beyond, spatial relationship term be intended to also include using and operating in device different orientation.Example
Such as, if the device upset in accompanying drawing, then, it is described as " below other elements " or " its it
Under " or " under which " element or feature will be oriented to other elements or feature " on ".Therefore, example
Property term " ... below " and " ... under " may include it is upper and lower two orientation.Device additionally can take
To (be rotated by 90 ° or other orientation) and spatial description language as used herein is correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and the limit not as the present invention
System.When here is used, " one " of singulative, " one " and " described/should " be also intended to include plural number
Form, unless context is expressly noted that other mode.It is also to be understood that term " composition " and/or " including ",
When using in this specification, the feature, integer, step, operation, element and/or part are determined
Presence, but be not excluded for one or more other features, integer, step, operation, element, part
And/or the presence or addition of group.When here is used, term "and/or" includes any of related Listed Items
And all combinations.
Embodiment one
The present invention is in order to solve problems of the prior art, there is provided ESD in a kind of FinFET
Layout structure, the measurement structure is as shown in figure 1, wherein Fig. 2 is another in embodiments of the present invention
The profile of ESD layout structures in FinFET, wherein A are the structure of the first doping type fin
Schematic diagram；Structural representations of the A for fin diode.
As shown in figure 1, the ESD layout structures include：
First doping type well region 12；
First doping type fin array 11, above the first doping type well region 12, including
The first doping type of some rows fin 111；
Fin diode array 10, above the first doping type well region 12, including some rows
Fin diode 101, in the fin diode 101, the bottom 1012 of fin is the first doping type,
The top 1011 of the fin is the second doping type；
Wherein, the first doping type fin array 11 is with the fin diode array 10 and in the ranks
Every setting, and the first doping type fin described in per a line is mutually handed over fin diode described in every a line
It is wrong to arrange.
Further, the ESD layout structures still further comprise Semiconductor substrate (not shown),
Positioned at the lower section of the first doping type well region.
Wherein, the Semiconductor substrate can be at least one in the following material being previously mentioned：Silicon, absolutely
Be laminated on silicon (SOI), insulator on edge body silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Alternatively, the Semiconductor substrate can select N-type or p-type, and described in this embodiment half
Conductor substrate selects p-type.
Wherein, the first doping type well region 12 is located in the Semiconductor substrate, first doping
Type well region 12 can be N traps or p-well, and the first doping type well region 12 is in this embodiment
P-well, for example, form p-well in the semiconductor substrate, for example, p-type be lightly doped in the Semiconductor substrate
Impurity, such as B, Ga, so that p type island region is spread in N-type substrate, form the p-well region.Wherein,
The ion injection method, energy, dosage can select method commonly used in the art, will not be described here.
First doping type fin array 11 is N-type or p-type fin, in this embodiment, described
First doping type fin array 11 is p-type fin.
Wherein, the first doping type fin array includes the first doping type of some rows fin 111, institute
State some rows the first doping type fin (p-type fin) 111 to be parallel to each other and interval setting, such as Fig. 1 institutes
Show.
The first doping type fin 111 is located in the p-well, and specific forming method includes：
Hard mask layer (not shown) is formed in p-well, the hard mask layer is formed and can be adopted art technology
The various suitable technique are familiar with by personnel, such as chemical vapor deposition method, the hard mask layer can be with
For the oxide skin(coating) that is laminated from bottom to top and silicon nitride layer；The hard mask layer is patterned, is formed for losing
Semiconductor substrate is carved to be formed on multiple masks being isolated from each other of fin, in one embodiment,
Using patterning process described in self-aligned double patterning case (SADP) process implementing；Etching p-well is with shape thereon
Into fin structure.
Wherein, the ESD layout structures still further comprise fleet plough groove isolation structure, the shallow trench every
It is located above the first doping type well region from structure and partly covers the first doping type fin battle array
Row and the fin diode array.
Specifically, the fleet plough groove isolation structure is also formed with spacer material layer in the p-well, described
Spacer material layer fills the gap around the first doping type fin and part covers described first and mixes
The bottom of miscellany type fin, to form the fin of object height, as shown in A in Fig. 2.
Specifically, the forming method of the depositing isolation material layer can include：Depositing isolation material layer,
With the gap being filled up completely between the first doping type fin structure.In one embodiment, adopt and have
The chemical vapor deposition method of flowable implements the deposition.The material of spacer material layer can select oxygen
Compound, such as HARP.Then spacer material layer described in etch-back, to the object height of the fin.
Specifically, spacer material layer described in etch-back, with fin described in exposed portion, and then forms with specific
The fin of height.
Wherein, the top of the first doping type fin 111 can be with bigger than p-well doping content
P-type doping, concrete doping content is not limited to a certain numerical range, can enter according to specific needs
Row is arranged.
Wherein, the structure of the fin diode is similar with the first doping type fin with formation,
Different is, in the fin diode, fin has two kinds of different doping, for example the fin two
In pole pipe 101, the bottom 1012 of fin is the first doping type, and the top 1011 of the fin is second
Doping type, to form fin transistors.
Specifically, in this embodiment, in the fin diode 101, the bottom 1012 of fin is p-type,
The top 1011 of the fin is N-type.
More specifically, wherein, the height of the fleet plough groove isolation structure is completely covered the fin diode
Described in fin bottom be the first doping type part, additionally, the fleet plough groove isolation structure may be used also
The top 1011 of the fin is covered with part, as shown in B in Fig. 2.
Further, in order to change problems of the prior art, in this application it is described first doping class
The overall parallel interval setting overall with the fin diode array 10 of type fin array 11, such as Fig. 1 institutes
Show, but the first doping type fin described in each of which row is mutually handed over fin diode described in every a line
Wrong to arrange, i.e., described first doping type fin is with fin diode described in every a line in the extension side of fin
Not alignment is arranged upwards, and it is interlaced, and stagger a certain distance, by the setting ESD
Need to wear from fin diode (N+/PW) to the first doping type fin (P+/PW) during current discharge
Longer distance is crossed, the robustness of the ESD structures can be further improved, reduces ESD defects
Occur.
Specifically, the shallow trench isolation junction between the first doping type fin and the fin diode
Structure is mutually aligned setting, more specifically, the centrage of the fin diode and first doping type
Fleet plough groove isolation structure centrage between fin in a straight line, shown in dotted line as shown in Figure 1, institute
It is mutually to hand on the bearing of trend of fin that the first doping type fin is stated with fin diode described in every a line
Wrong.
Alternatively, in the lower section of the first doping type fin array and the fin diode array also
Contact hole array is respectively formed with, to form electrical connection respectively.
The contact hole can select conventional conductive material, be electrically connected with being formed with the lifting source and drain,
The less metal material of contact resistance can be for example selected, copper, aluminum etc. can be such as selected.
In order to solve problems of the prior art, there is provided a kind of present invention is in order to solve prior art
Present in problem, there is provided a kind of ESD layout structures, the ESD structures be fin diode-like
Type, wherein, the ESD structures include the first doping type fin and fin diode array and each
Row the first doping type fin and the interlaced setting of fin diode described in every a line, by described
Need from fin diode (N+/PW) to the first doping type fin when ESD current discharges are set
(P+/PW) robustness of the ESD structures through longer distance, can be further improved, is reduced
The generation of defect.
Embodiment two
The present invention is in order to solve problems of the prior art, there is provided ESD in a kind of FinFET
Layout structure, the measurement structure is as shown in figure 1, wherein Fig. 2 is another in embodiments of the present invention
The profile of ESD layout structures in FinFET, wherein A are the structure of the first doping type fin
Schematic diagram；Structural representations of the A for fin diode.
As shown in figure 1, the ESD layout structures include：
First doping type well region 12；
First doping type fin array 11, above the first doping type well region 12, including
The first doping type of some rows fin 111；
Fin diode array 10, above the first doping type well region 12, including some rows
Fin diode 101, in the fin diode 101, the bottom 1012 of fin is the first doping type,
The top 1011 of the fin is the second doping type；
Wherein, the first doping type fin array 11 is with the fin diode array 10 and in the ranks
Every setting, and the first doping type fin described in per a line is mutually handed over fin diode described in every a line
It is wrong to arrange.
Further, the ESD layout structures still further comprise Semiconductor substrate (not shown),
Positioned at the lower section of the first doping type well region.
Wherein, the Semiconductor substrate can be at least one in the following material being previously mentioned：Silicon, absolutely
Be laminated on silicon (SOI), insulator on edge body silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Alternatively, the Semiconductor substrate can select N-type or p-type, and described in this embodiment half
Conductor substrate selects N-type.
Wherein, the first doping type well region 12 is located in the Semiconductor substrate, first doping
Type well region 12 can be N traps or p-well, and the first doping type well region 12 is in this embodiment
N traps, for example, form N traps, such as lightly doped n type in the Semiconductor substrate in the semiconductor substrate
Impurity, such as P, As, so that N-type region is spread in P type substrate, form the N well regions.Wherein,
The ion injection method, energy, dosage can select method commonly used in the art, will not be described here.
First doping type fin array 11 is N-type or p-type fin, in this embodiment, described
First doping type fin array 11 is N-type fin.
Wherein, the first doping type fin array includes the first doping type of some rows fin 111, institute
State some rows the first doping type fin (N-type fin) 111 to be parallel to each other and interval setting, such as Fig. 1
It is shown.
The first doping type fin 111 is located on the N traps, and specific forming method includes：
Hard mask layer (not shown) is formed on N traps, the hard mask layer is formed and can be adopted art technology
The various suitable technique are familiar with by personnel, such as chemical vapor deposition method, the hard mask layer can be with
For the oxide skin(coating) that is laminated from bottom to top and silicon nitride layer；The hard mask layer is patterned, is formed for losing
Semiconductor substrate is carved to be formed on multiple masks being isolated from each other of fin, in one embodiment,
Using patterning process described in self-aligned double patterning case (SADP) process implementing；Etching N traps are with thereon
Form fin structure.
Wherein, the ESD layout structures still further comprise fleet plough groove isolation structure, the shallow trench every
It is located above the first doping type well region from structure and partly covers the first doping type fin battle array
Row and the fin diode array.
Specifically, the fleet plough groove isolation structure is also formed with spacer material layer on the N traps, described
Spacer material layer fills the gap around the first doping type fin and part covers described first and mixes
The bottom of miscellany type fin, to form the fin of object height, as shown in A in Fig. 2.
Specifically, the forming method of the depositing isolation material layer can include：Depositing isolation material layer,
With the gap being filled up completely between the first doping type fin structure.In one embodiment, adopt and have
The chemical vapor deposition method of flowable implements the deposition.The material of spacer material layer can select oxygen
Compound, such as HARP.Then spacer material layer described in etch-back, to the object height of the fin.
Specifically, spacer material layer described in etch-back, with fin described in exposed portion, and then forms with specific
The fin of height.
Wherein, the top of the first doping type fin 111 can be with bigger than N trap doping contents
N-type doping, concrete doping content is not limited to a certain numerical range, can enter according to specific needs
Row is arranged.
Wherein, the structure of the fin diode is similar with the first doping type fin with formation,
Different is, in the fin diode, fin has two kinds of different doping, for example the fin two
In pole pipe 101, the bottom 1012 of fin is the first doping type, and the top 1011 of the fin is second
Doping type.
Specifically, in this embodiment, in the fin diode 101, the bottom 1012 of fin is N
Type, the top 1011 of the fin is p-type.
More specifically, wherein, the height of the fleet plough groove isolation structure is completely covered the fin diode
Described in the bottom of fin be the first doping type part, additionally, the fleet plough groove isolation structure can be with
Part covers the top 1011 of the fin, as shown in B in Fig. 2.
Further, in order to change problems of the prior art, in this application it is described first doping class
The overall parallel interval setting overall with the fin diode array 10 of type fin array 11, such as Fig. 1 institutes
Show, but the first doping type fin described in each of which row is mutually handed over fin diode described in every a line
Wrong to arrange, i.e., described first doping type fin is with fin diode described in every a line in the extension side of fin
Not alignment is arranged upwards, and it is interlaced, and stagger a certain distance, by the setting ESD
Need to wear from fin diode (P+/NW) to the first doping type fin (N+/NW) during current discharge
Longer distance is crossed, the robustness of the ESD structures can be further improved, reduces ESD defects
Occur.
Specifically, the shallow trench isolation junction between the first doping type fin and the fin diode
Structure is mutually aligned setting, more specifically, the centrage of the fin diode and first doping type
Fleet plough groove isolation structure centrage between fin in a straight line, shown in dotted line as shown in Figure 1, institute
It is mutually to hand on the bearing of trend of fin that the first doping type fin is stated with fin diode described in every a line
Wrong.
Alternatively, in the lower section of the first doping type fin array and the fin diode array also
Contact hole array is respectively formed with, to form electrical connection respectively.
The contact hole can select conventional conductive material, be electrically connected with being formed with the lifting source and drain,
The less metal material of contact resistance can be for example selected, copper, aluminum etc. can be such as selected.
In order to solve problems of the prior art, there is provided a kind of present invention is in order to solve prior art
Present in problem, there is provided a kind of ESD layout structures, the ESD structures be fin diode-like
Type, wherein, the ESD structures include the first doping type fin and fin diode array and each
Row the first doping type fin and the interlaced setting of fin diode described in every a line, by described
Need from fin diode (P+/NW) to the first doping type fin when ESD current discharges are set
(N+/NW) robustness of the ESD structures through longer distance, can be further improved, is reduced
The generation of defect.
Embodiment three
Present invention also offers a kind of electronic installation, including the ESD structures described in embodiment one or two.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book,
Game machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen, MP3,
Any electronic product such as MP4, PSP or equipment, it is alternatively any including product in the middle of the ESD structures
Product.The electronic installation of the embodiment of the present invention, due to having used above-mentioned ESD structures, thus has more preferable
Performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment
Citing and descriptive purpose are only intended to, and are not intended to limit the invention to described scope of embodiments
It is interior.In addition it will be appreciated by persons skilled in the art that the invention is not limited in above-described embodiment, root
More kinds of variants and modifications can also be made according to the teachings of the present invention, these variants and modifications all fall within this
Within inventing scope required for protection.Protection scope of the present invention is by the appended claims and its waits
Effect scope is defined.
Claims (9)
1. a kind of ESD layout structures, including：
First doping type well region；
First doping type fin array, above the first doping type well region, including some rows
First doping type fin；
Fin diode array, above the first doping type well region, including some row fins two
Pole pipe, in the fin diode, the bottom of fin is the first doping type, and the top of the fin is the
Two doping types；
Wherein, the first doping type fin array and fin diode array interval setting arranged side by side,
And the first doping type fin and the interlaced setting of fin diode described in every a line described in per a line.
2. ESD layout structures according to claim 1, it is characterised in that the ESD layouts
Structure still further comprises fleet plough groove isolation structure, and the fleet plough groove isolation structure is positioned at the described first doping
The top of type well region simultaneously partly covers the first doping type fin array and the fin diode battle array
Row.
3. ESD layout structures according to claim 2, it is characterised in that the shallow trench every
Height from structure is completely covered the part of the first doping type described in the fin diode.
4. ESD layout structures according to claim 1, it is characterised in that often go the fin
The center of the fleet plough groove isolation structure described in the centrage of diode and two rows between the first doping type fin
Line is on the same line.
5. ESD layout structures according to claim 1, it is characterised in that mix described first
The lower section of miscellany type fin array and the fin diode array is also respectively formed with contact hole array, with
Electrical connection is formed respectively.
6. ESD layout structures according to claim 1, it is characterised in that the ESD layouts
Structure still further comprises Semiconductor substrate, positioned at the lower section of the first doping type well region.
7. ESD layout structures according to claim 1, it is characterised in that first doping
Type is adulterated for p-type, and second doping type is n-type doping.
8. ESD layout structures according to claim 1, it is characterised in that first doping
Type is n-type doping, and second doping type adulterates for p-type.
9. the ESD layout structures described in a kind of one of electronic installation, including claim 1 to 8.
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|---|---|
| CN106558571B (en) | 2019-05-17 |
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