CN106558622B - STI diode for ESD protection - Google Patents
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- CN106558622B CN106558622B CN201510615429.6A CN201510615429A CN106558622B CN 106558622 B CN106558622 B CN 106558622B CN 201510615429 A CN201510615429 A CN 201510615429A CN 106558622 B CN106558622 B CN 106558622B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 85
- 239000000463 material Substances 0.000 claims description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an STI diode for ESD protection, and relates to the technical field of semiconductors. The method comprises the following steps: the semiconductor device comprises a semiconductor substrate, a well region with a first conduction type and a second conduction type, wherein the well region is positioned in the semiconductor substrate; the semiconductor device comprises a semiconductor substrate, a plurality of first fins and a plurality of second fins, wherein the plurality of first fins are positioned on the semiconductor substrate and extend along a first direction, and a first doping region which extends along the first direction and is provided with a first conductivity type is formed in each first fin; a plurality of second fins located between the plurality of first fins and extending along the first direction, wherein a second doped region extending along the first direction and having a second conductivity type is formed in each second fin; an isolation structure on the semiconductor substrate between the plurality of first fins and the number of second fins. The STI diode of the invention improves the area efficiency of the device, and leads the uniformity of the metal silicide to be better, thus leading the ESD device to have higher secondary breakdown current and smaller on-resistance (Ron).
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an STI diode for ESD protection.
Background
With the continuous development of semiconductor technology, the performance of integrated circuits is improved mainly by the continuous reduction of the size of integrated circuit devices to increase the speed thereof. Currently, the semiconductor industry has progressed to nanotechnology process nodes as a result of pursuit of high device density, high performance, and low cost. However, this trend of progress has a negative impact on the reliability of the end product: in the field of semiconductor technology, the electrostatic discharge (ESD) phenomenon is a great threat to integrated circuits, and can break down the integrated circuits and semiconductor elements, promote element aging, and reduce production yield. Accordingly, as semiconductor process dimensions continue to decrease, ESD protection designs become increasingly challenging and difficult in CMOS technologies on the nanometer scale.
The capacitive loading of the ESD device is a fundamental design parameter. The parasitic capacitance of the STI diode (shown in fig. 1B) is reduced by 50% compared to the gated diode (shown in fig. 1A), making the STI diode a preferred diode type for high frequency applications.
Currently, the STI diode structure is shown in fig. 2A and fig. 2B, and the main problem is that the current on the drain side is crowded at the bottom of the epitaxial layer, and the junction area between the fin and the epitaxial layer is very small, so the discharge capability is limited. The STI diode forms a metal silicide (not shown) only on the exposed portion of the top surface of the fin below the contact trench (CCT) as shown in fig. 2A, so the ratio of the area occupied by the metal silicide on the fin is very small, making the on-resistance (Ron) too large and the device second breakdown current (It2) measured by TLP too small.
One approach to achieving a larger discharge current is to increase the number of fins, and this approach suffers from the drawback that if the fins are not uniform and the silicide is not uniform, the device can easily break down on one or some of the fins. The failure is typically located in the Li-defined locally suicided region. The small silicide regions defined by Li produce higher spreading resistance and higher current non-uniformity, which lead to localized damage at high current pressures. While the current ratio in a device with a wide metal silicide structure will be more uniform.
STI diodes with wide silicide structures have a relatively high critical diode current before the local temperature is greatly increased. The wide silicide structure can enhance the second breakdown current (It2) of the ESD protection diode due to more uniform current distribution and relatively high critical diode current.
Therefore, it is necessary to provide a new STI diode to enhance the esd protection performance of the FinFET device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the deficiencies of the prior art, an embodiment of the present invention provides an STI diode for ESD protection, including:
the semiconductor device comprises a semiconductor substrate, a well region with a first conduction type and a second conduction type, wherein the well region is positioned in the semiconductor substrate;
the semiconductor device comprises a semiconductor substrate, a plurality of first fins and a plurality of second fins, wherein the plurality of first fins are positioned on the semiconductor substrate and extend along a first direction, and a first doping region which extends along the first direction and is provided with a first conductivity type is formed in each first fin;
a plurality of second fins located between the plurality of first fins and extending along the first direction, wherein a second doped region extending along the first direction and having a second conductivity type is formed in each second fin;
shallow trench isolation structures on the semiconductor substrate between the plurality of first fins and the plurality of second fins.
Further, a first epitaxial layer extending in the first direction is formed on the first fin, and a second epitaxial layer extending in the first direction is formed on the second fin.
Further, the first epitaxial layer completely covers the top surfaces of the first fins, and the second epitaxial layer completely covers the top surfaces of the second fins.
Further, the first conductivity type is P-type, the second conductivity type is N-type, the first epitaxial layer is SiGe, and the second epitaxial layer is a silicon epitaxial layer.
Further, the first conductivity type is N-type, the second conductivity type is P-type, the first epitaxial layer is a silicon epitaxial layer, and the second epitaxial layer is SiGe.
Further, a metal silicide extending in the first direction is formed on all top surfaces of each of the first fins and each of the second fins.
Further, the material of the shallow trench isolation structure comprises a silicon oxide material.
Further, the semiconductor device further comprises a plurality of contacts respectively connected with each first doping region and each second doping region.
Further, an interlayer dielectric layer is formed between the plurality of contacts.
In summary, the STI diode for an electrostatic discharge protection structure of a FinFET device of the present invention improves the area efficiency (area efficiency) of the device, so that the uniformity of the metal silicide is better, and thus the ESD device has a higher second breakdown current (It2) and a smaller on-resistance (Ron), and the ESD protection performance of the device is further improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1A is a schematic cross-sectional view of a conventional gated diode;
FIG. 1B is a schematic cross-sectional view of a conventional STI diode;
FIG. 2A is a plan view of a conventional STI diode;
FIG. 2B is a cross-sectional view of a conventional STI diode taken along the cross-sectional line of FIG. 2A;
FIG. 3A is a layout plan view of an STI diode for ESD protection according to one embodiment of the present invention;
fig. 3B is a schematic cross-sectional view of an STI diode for ESD protection according to an embodiment of the invention, taken corresponding to the cross-sectional line in fig. 3A.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
An STI diode for ESD protection according to an embodiment of the present invention is described below with reference to fig. 3A and 3B. Fig. 3A is a plan layout view of an STI diode for ESD protection according to an embodiment of the present invention; fig. 3B is a schematic cross-sectional view of an STI diode for ESD protection according to an embodiment of the invention, taken corresponding to the cross-sectional line in fig. 3A.
Illustratively, an STI diode for ESD protection of an embodiment of the present invention includes:
A well region having a first conductivity type, which is N-type or P-type, is also formed in the semiconductor substrate 100, for example, as shown in fig. 3A, a P-type well region is formed in the semiconductor substrate 100.
As shown in fig. 3A, the semiconductor device further includes a plurality of first fins 101a extending along a first direction on the semiconductor substrate 100, and a first doped region extending along the first direction and having a first conductivity type is formed in each of the first fins 101 a. Illustratively, the first conductive type is a P-type, the first doped region is a P-type doped region, and preferably, the first doped region is a P + doped region. Wherein the area of the first doped region coincides with the area of the first fin 101a in the first direction, and the entire first fin 101a serves as the first doped region.
The fin structure further comprises a plurality of second fins 101b which are located between the plurality of first fins 101a and extend along a first direction, and a second doped region which extends along the first direction and is of a second conductive type is formed in each second fin 101 b. Illustratively, the second conductivity type is N-type, the second doped region is an N-type doped region, and preferably, the second doped region is an N + doped region. Wherein the area of the second doped region coincides with the area of the second fin 101b in the first direction, and the entire second fin 101b serves as the second doped region.
The first fin 101a and the second fin 101b may be made of a semiconductor material such as silicon, germanium, or silicon germanium. The shape thereof may be approximately a rectangular parallelepiped structure or other three-dimensional structure perpendicular to the semiconductor substrate. For example, the forming method of the first fin 101a and the second fin 101b may be: firstly, a semiconductor material layer is formed on a semiconductor substrate, a well region with a first conduction type is formed in the semiconductor substrate, the semiconductor material layer can be made of Si, SiGe, Ge or III-V materials, then a patterned mask layer, such as a photoresist mask layer, is formed on the semiconductor material layer, the photoresist mask layer defines the width, the length, the position and the like of the first fin 101a and the second fin 101b, then the semiconductor material layer is etched by taking the photoresist mask layer as a mask to form the first fin 101a and the second fin 101b, then the photoresist mask layer is removed, and the method for removing the photoresist mask layer can be an oxidation ashing method.
In another example, the method for forming the first fin 101a and the second fin 101b may further include: providing a semiconductor substrate, forming a well region with a first conductivity type in the semiconductor substrate, forming a patterned mask layer, such as a photoresist mask layer, on the semiconductor substrate, wherein the photoresist mask layer defines the width, the length, the position and the like of the first fin 101a and the second fin 101b, then etching the semiconductor substrate by using the photoresist mask layer as a mask to form the first fin 101a and the second fin 101b, and then removing the photoresist mask layer.
It should be noted that the forming method of the first fin 101a and the second fin 101b is merely exemplary and is not limited to the above method. Each of the first fins and the second fins have substantially the same width and length.
Illustratively, two second fins 101b are located between four first fins 101a, for example, two first fins 101a are located on each side of the two second fins 101b, but it is also possible to have one first fin on one side and three first fins on the other side, and the arrangement order of the first fins and the second fins is merely exemplary, so long as other suitable order that the first fins are formed on both sides of the second fins can be applied to the present invention.
The first doping region and the second doping region may be formed by performing ion implantation of different types of doping impurities (P-type impurities or N-type impurities) to the first fin 101a and the second fin 101b, respectively, which will not be described herein.
The STI diode of the present invention further includes an isolation structure 102 on the semiconductor substrate 100 between the plurality of first fins 101a and the number of second fins 101 b. A shallow trench isolation Structure (STI)102 is formed in the semiconductor substrate 100. Generally, the material of the shallow trench isolation structure 102 mainly includes a silicon oxide material, and may be formed by chemical vapor deposition, physical vapor deposition, magnetron sputtering, and the like, and exemplarily, the top surface of the shallow trench isolation structure 102 may be lower than the top surface of the fin.
Further, a first epitaxial layer 103a extending in the first direction is formed on the first fin 101a, and a second epitaxial layer 103b extending in the first direction is formed on the second fin 101 b. Preferably, the first epitaxial layer 103a completely covers the top surface of the first fin 101a, and the second epitaxial layer 103b completely covers the top surface of the second fin 101 b. By forming the epitaxial layer on the whole fin, the contact area between the epitaxial layer and the fin can be obviously increased, and the electrostatic current discharge capacity of the fin can be increased.
In one example, as shown in fig. 3B, the first conductivity type is P-type, the second conductivity type is N-type, that is, the first doped region is a P + doped region, the second doped region is an N + doped region, correspondingly, the first epitaxial layer 103a is SiGe, and the SiGe is used as a compressive stress layer. The second epitaxial layer 103b is a silicon epitaxial layer, for example, SiC, which is a tensile stress layer, and the like.
In another example, the first conductivity type is N-type, the second conductivity type is P-type, the first epitaxial layer is a silicon epitaxial layer, for example, SiC is used as a tensile stress layer, and the like, the second epitaxial layer is SiGe is used as a compressive stress layer.
Further, a metal silicide 105 extending in the first direction is formed on all top surfaces of each of the first fins 101a and each of the second fins 101 b. Since the metal silicide is formed on the entire fin, the uniformity of the metal silicide is better, so that the on-resistance (Ron) is smaller. Thereby preventing the device from being broken down on one or more fins and improving the reliability of the device.
The metal silicide 105(silicide) region may be formed using any method known to those skilled in the art. For example, as shown in fig. 3A, a contact trench 104(CCT) exposing the top surfaces of the first fin and the second fin is formed, and then a metal layer, which may include nickel (nickel), titanium (titanium), cobalt (cobalt), and platinum (platinum) or a combination thereof, is deposited into the contact trench 104. The substrate is then heated, causing the metal layer to silicidize with the underlying silicon layer, thereby forming metal silicide 105 regions on the surfaces of the first fin and the second fin. An etchant that attacks the metal layer, but not the silicide region, is then used to remove the unreacted metal layer. Further, the metal silicide 105 is located on the surfaces of the first epitaxial layer 103a and the second epitaxial layer 103b, and the forming method may be: a contact trench 104 is formed to expose the surfaces of the first epitaxial layer 103a and the second epitaxial layer 103b, and after the contact trench 104 is filled with a metal layer, the metal is silicided with the first epitaxial layer 103a and the second epitaxial layer 103b under a heating condition to form a metal silicide 105.
In one example, the STI diode of the present invention further includes a plurality of contacts 106 respectively connected to each of the first doped regions and each of the second doped regions. The contacts may be formed by filling a metal material into a contact trench (CCT)104, or may be formed by other methods, the contacts 106 may be copper metal interconnection structures, tungsten plugs, etc., an interlayer dielectric layer 107 is further formed on the semiconductor substrate 100 between the contacts 106, and the interlayer dielectric layer 107 may be, for example, SiO, and may be used as the interlayer dielectric layer 1072Fluorocarbon (CF), silicon oxide doped with carbon (SiOC), silicon carbonitride (SiCN), or the like.
As shown by arrows in fig. 3B, for the STI diode of the present invention, the current can flow from the N + doped region into the P + doped regions on both sides of the N + doped region respectively to realize the ESD current discharge.
In summary, the STI diode for an electrostatic discharge protection structure of a FinFET device of the present invention improves the area efficiency (area efficiency) of the device, so that the uniformity of the metal silicide is better, and thus the ESD device has a higher second breakdown current (It2) and a smaller on-resistance (Ron), and the ESD protection performance of the device is further improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. An STI diode for ESD protection, comprising:
the semiconductor device comprises a semiconductor substrate, a well region with a first conduction type and a second conduction type, wherein the well region is positioned in the semiconductor substrate;
the semiconductor device comprises a semiconductor substrate, a plurality of first fins and a plurality of second fins, wherein the plurality of first fins are positioned on the semiconductor substrate and extend along a first direction, a first doping region which extends along the first direction and is provided with a first conductive type is formed in each first fin, the area of the first doping region is overlapped with that of the first fin in the first direction, and the whole first fin is used as the first doping region;
a plurality of second fins located between the plurality of first fins and extending along the first direction, wherein a second doped region extending along the first direction and having a second conductivity type is formed in each second fin, the area of the second doped region is overlapped with the area of the second fin in the first direction, and the whole second fin is used as the second doped region;
a first epitaxial layer on the first fin and extending along the first direction;
a second epitaxial layer on the second fin and extending along the first direction;
forming a metal silicide extending along the first direction on all top surfaces of each first fin and each second fin, wherein the metal silicide is positioned on the surfaces of the first epitaxial layer and the second epitaxial layer;
shallow trench isolation structures on the semiconductor substrate between the plurality of first fins and the plurality of second fins.
2. The STI diode of claim 1, wherein the first epitaxial layer completely covers a top surface of the first fin and the second epitaxial layer completely covers a top surface of the second fin.
3. The STI diode of claim 1, wherein the first conductivity type is P-type, the second conductivity type is N-type, the first epitaxial layer is SiGe, and the second epitaxial layer is a silicon epitaxial layer.
4. The STI diode of claim 1, wherein the first conductivity type is N-type, the second conductivity type is P-type, the first epitaxial layer is a silicon epitaxial layer, and the second epitaxial layer is SiGe.
5. The STI diode of claim 1, wherein the material of the shallow trench isolation structure comprises a silicon oxide material.
6. The STI diode of claim 1, further comprising a plurality of contacts respectively connected to each of the first doped regions and each of the second doped regions.
7. The STI diode of claim 1, wherein an interlayer dielectric layer is formed between the plurality of contacts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510615429.6A CN106558622B (en) | 2015-09-24 | 2015-09-24 | STI diode for ESD protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510615429.6A CN106558622B (en) | 2015-09-24 | 2015-09-24 | STI diode for ESD protection |
Publications (2)
| Publication Number | Publication Date |
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| CN106558622A CN106558622A (en) | 2017-04-05 |
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| CN108878541B (en) * | 2017-05-08 | 2021-07-02 | 中芯国际集成电路制造(上海)有限公司 | Fin type diode and manufacturing method thereof |
| CN109216470B (en) * | 2017-07-03 | 2021-08-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110518008A (en) * | 2018-05-22 | 2019-11-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD protective device and preparation method thereof, electronic device |
| CN114709210B (en) * | 2022-06-07 | 2022-09-02 | 深圳市晶扬电子有限公司 | Low clamping voltage electrostatic protection device suitable for nanoscale FinFET (field effect transistor) process |
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| KR20130081184A (en) * | 2012-01-06 | 2013-07-16 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Io esd device and methods for forming the same |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
| EP2770538A1 (en) * | 2013-02-25 | 2014-08-27 | Imec | Fin type semiconductor structure suitable for producing esd protection device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20130081184A (en) * | 2012-01-06 | 2013-07-16 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Io esd device and methods for forming the same |
| CN103489863A (en) * | 2012-06-12 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Homo-junction diode structures using fin field effect transistor processing |
| EP2770538A1 (en) * | 2013-02-25 | 2014-08-27 | Imec | Fin type semiconductor structure suitable for producing esd protection device |
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