CN106558496A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- CN106558496A CN106558496A CN201510634782.9A CN201510634782A CN106558496A CN 106558496 A CN106558496 A CN 106558496A CN 201510634782 A CN201510634782 A CN 201510634782A CN 106558496 A CN106558496 A CN 106558496A
- Authority
- CN
- China
- Prior art keywords
- layer
- high mobility
- mobility layer
- fin
- sti
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims abstract description 9
- 230000004888 barrier function Effects 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 229910052731 fluorine Inorganic materials 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims description 5
- 229910021478 group 5 element Inorganic materials 0.000 claims description 3
- 230000007480 spreading Effects 0.000 claims description 2
- 238000003892 spreading Methods 0.000 claims description 2
- 229910052717 sulfur Inorganic materials 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 6
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 53
- 230000037230 mobility Effects 0.000 description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- -1 oxygen alkane Chemical class 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 101000658644 Homo sapiens Tetratricopeptide repeat protein 21A Proteins 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910020211 SiOxHy Inorganic materials 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 102100034913 Tetratricopeptide repeat protein 21A Human genes 0.000 description 1
- TZHYBRCGYCPGBQ-UHFFFAOYSA-N [B].[N] Chemical compound [B].[N] TZHYBRCGYCPGBQ-UHFFFAOYSA-N 0.000 description 1
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor device manufacturing method, comprising: etching the substrate to form a plurality of fins; forming STI between the fins; forming a first high mobility layer on the fin portion exposing the STI; an oxidation and/or nitridation process is performed to convert the first high mobility layer into a dielectric layer and simultaneously convert the exposed STI fin portion into a second high mobility layer. According to the manufacturing method of the semiconductor device, the high mobility material serving as the sacrificial layer is oxidized, ions are driven to diffuse, so that the fins formed by the substrate material are converted into the high mobility material, the process is simplified, the cost is low, the performance of the device is improved, and the device is beneficial to device miniaturization.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, more particularly to a kind of to have little chi
The FinFET manufacture methods of very little mobility channel.
Background technology
Move ahead to continue to press on Moore's Law, the driving current of device needs to get a greater increase
And need to control short-channel effect.It is integrated with the body silicon fin gate fin-fet of mobility channel
(finfet) device is considered as the device of the most potential development for promoting Moore's Law.
The preparation method of mobility channel finfet devices usually grows high mobility on a silicon substrate
Channel material.The raceway groove of high mobility is generally made up of high mobility material, such as germanium, germanium silicon, III--V
Race's material, II--VI races material etc..By taking SiGe as an example, high mobility material is re-formed after the growth was completed
The fin of composition.A kind of Integrated Solution is one layer of germanium of extension after conventional method forms silicon fin and STI
Silicon is used as high mobility material.
But the integrated technique of routine faces problems with：
1) whole fin is made up of silicon fin and germanium silicon epitaxial layer, due to being made up of this two parts, institute
It is difficult to do thin with whole fin, this is unfavorable for the further size reduction of device.It is in raceway groove simultaneously
The fin mobilities in portion are not high, are unfavorable for the performance of boost device.
2) when the concentration of germanium is higher, carrier mobility is higher.But with the rising of germanium concentration,
(critical thickness, i.e., will more than this thickness for the crucial thickness of the extension of germanium silicon or germanium
Produce more defect) diminish.When defect is more, the carrier mobility of the material will be moved back
Change, so as to hinder to improve the performance of device.
The content of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, propose that one kind can
The FinFET manufacture methods of the small size mobility channel of Simplified flowsheet reduces cost.
For this purpose, the invention provides a kind of method, semi-conductor device manufacturing method, including：Etched substrate
Form multiple fins；STI is formed between fin；Is formed on the fin portion for expose STI
One high mobility layer；Oxidation and/or nitriding process are performed, the first high mobility layer is changed into into Jie
The fin portion for exposing STI is simultaneously changed into the second high mobility layer by matter layer simultaneously.
Wherein, perform oxidation and/or nitriding process causes the non-Si in the first high mobility layer first
Element is diffused to the fin portion that exposes STI and is reconfigured to form the second high migration with fin material
Rate layer.
Wherein, before or after the first high mobility layer is formed, an independent or similar shape
Stop into non-element silicon is spread to substrate in high mobility layer barrier layer and anti-break-through is prevented
Layer.
Wherein, inject in preventing the barrier layer that non-element silicon in high migrating layer spread to substrate from
The atomic number of son is less than the non-Si elements in the first high mobility layer, to prevent non-Si elements from expanding
It is dissipated to substrate.Wherein, any one and its group of the ion of injection selected from C, N, O, F, S
Close.
Wherein, the doped chemical on anti-break-through barrier layer according to device different type select three races or
Simple substance or compound of the group-v element with itself or with other race's element compositions.
Wherein, the material of the first high mobility layer is selected from III--V races, II--VI races, V compounds of group
Any one of semiconductor and combinations thereof.
Wherein, the size of the fin for being smaller in size than etched substrate formation of the second high mobility layer.
Wherein, in the first high mobility layer, non-Si elements will in the concentration with fin portion interface
Less than the concentration in outer surface.
Wherein, further include after forming the second high mobility layer, be developed across high second
Gate stack on mobility layer, forms source in the second high mobility layer of gate stack both sides
Drain region.
Wherein, doped region also serves as break-through barrier layer.
According to the method, semi-conductor device manufacturing method of the present invention, by aoxidizing the Gao Qian as sacrifice layer
Shifting rate material, orders about ion and spreads so that the fin that backing material is constituted is converted to high mobility material
Material, improves device performance and beneficial to device micro with Simplified flowsheet and low cost.
Description of the drawings
Referring to the drawings describing technical scheme in detail, wherein：
Fig. 1 to Fig. 3 is the sectional view of each step of FinFET manufacture methods according to the present invention；And
Fig. 4 is the indicative flowchart of the FinFET manufacture method according to the present invention.
Specific embodiment
The technology of the present invention side is described in detail referring to the drawings and with reference to schematic embodiment
The feature and its technique effect of case, discloses small size Gao Qian for being capable of Simplified flowsheet reduces cost
The FinFET manufacture methods of shifting rate raceway groove.It is pointed out that similar reference represents class
As structure, term " first " use herein, " second ", " on ", D score
Etc. can be used to modify various device architectures or manufacturing process.These modifications are unless stated otherwise simultaneously
Non- space, order or the hierarchical relationship for implying institute's modification device architecture or manufacturing process.
As shown in Fig. 4 and Fig. 1, etched substrate forms multiple fins.
Substrate 1 is provided, its material can be monocrystalline silicon, SOI, monocrystalline germanium, GeOI, strain
Silicon (Strained Si), germanium silicon (SiGe), or compound semiconductor materials, such as nitrogen
Change gallium (GaN), GaAs (GaAs), indium phosphide (InP), indium antimonide (InSb),
And carbon-based semiconductors such as Graphene, SiC, carbon nanotube etc..It is preferred in the present invention one
In embodiment, substrate 1 be monocrystalline silicon, in order to it is compatible with CMOS technology and reduce make
Cause this.
Using mask graph (it is not shown, can be photoresist soft mask or dielectric material it is hard
Mask) etched substrate 1, the multiple fin structure 1F for extending in a first direction are defined, and
Groove (not shown) between adjacent fin structure.Etching technics preferably anisotropic dry method
Etching, such as dry plasma etch or RIE, etching gas such as carbon fluorine base gas is (at least
Containing carbon, fluorine atom, can also also have other atoms such as hydrogen, nitrogen, oxygen), chlorine, bromine steam
Vapour, HCl, HBr etc., can also add the oxidants such as oxygen, CO, ozone to adjust etching
Speed.
In groove between fin structure 1F, fill insulant forms shallow trench isolation (STI)
2.For example by techniques such as thermal oxide, LPCVD, PECVD, between fin structure 1F
Groove in define the STI 2 of insulating materials.In a preferred embodiment of the invention, STI
2 materials are silica or nitrogenize silicon substrate matter, such as SiOx、SiNx、SiOxNy、SiOxCy、
SiOxFy、SiOxHy、SiNxCy、SiNxFy(each xy is not necessarily integer).Expose STI 2
The part 1C of the fin 1F on top will act as the source-drain area and channel region of FinFET.
In another preferred embodiment of the present invention, the material of STI 2 is low-k materials to reduce device
Parasitic capacitance, formation process be spin coating, spraying, serigraphy, wherein low-k materials include but
It is not limited to organic low-k materials (such as the organic polymer containing aryl or many yuan of rings), inorganic
Low-k materials (for example amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG,
PSG, BPSG), (three oxygen alkane (SSQ) Quito hole of such as two silicon is low for porous low k material
K materials, porous silica, porous SiOCH, mix C silica, mix F porous without
Setting carbon, porous diamond, porous organic polymer).In another preferred embodiment of the present invention
In, the material of STI2 also includes negative expansion dielectric material or positive thermal expansion dielectric material (preferably
Ground, at a temperature of 100K, the absolute value of the linear coefficient of cubical expansion is more than 10-- 4/ K) son
Layer, to further enhance channel region stress, negative expansion dielectric material is to include being selected from
Bi0..95La0..05NiO3、BiNiO3、ZrW2O8Any one and combinations thereof Ca-Ti ore type oxidation
Thing, positive thermal expansion dielectric material is to include Ag3[Co(CN)6] frame material.
Optionally or preferably, the ion implanting, (example below the channel region 1C of fin 1F are performed
Such as 2 near tops of STI) doped region 3 is formed, the ion as follow-up high mobility material expands
Scattered barrier layer.Implantation Energy such as 500eV～500KeV preferably 20KeV～80KeV,
Implantation dosage such as 1012～1016And preferably 5 × 1012～1014Atom/cm3, the element of injection
Atomic number (will expand in a preferred embodiment of the invention less than the element that will subsequently spread
Scattered element is Ge), the element for for example injecting is preferably chosen from C, N, O, F, S
Any one and combinations thereof, and most preferably C (C and Si, Ge are all IV races element, atom
Structure is similar to, and barrier layer can be regarded as the network structure that Si and C forms, if will prevent
The high mobility materials such as Ge spread or migrate, select the less purpose of atomic number be exactly in order to
So that mesh size reduces, the material of larger atomic number so can be effectively prevented to migrate).
Ion implanting can be that vertical injection, or inclination are injected (towards channel region 1C),
The angle for inclining injection is, for example, 5～15 degree.Annealing, the injection for making can be performed after injection
Impurity activation and redistribute, precise control causes the peak concentration of doped region 3 in STI 2
At top or nearby (namely in the lower section of fin 1F top channels area 1C, such as with STI 2
Top flushes or lower slightly 1～3nm).Such as 550～1050 DEG C of annealing temperature, preferably
650～900 DEG C, optimal 700～800 DEG C, annealing time 1s～10min, 10s～5min,
1～3min.Further, these Doped ions can also cause 3 conductive-type of doped region simultaneously
Type it is contrary with channel region or directly as dielectric so as to define anti-break-through barrier layer,
Effect is dielectrically separated between substrate and raceway groove so as to improve, eliminate or reduces substrate and let out
Leakage current.In addition before or after the first high mobility layer is formed, extraly individually or
Together form the barrier layer that prevents non-element silicon in high mobility layer from spread to substrate and prevent wearing
Logical barrier layer, namely barrier layer 3 and anti-break-through barrier layer (not shown) can be formed together
Can be formed step by step.The doped chemical on anti-break-through barrier layer selects three races according to device different type
Or simple substance or compound of the group-v element with itself or with other race's element compositions.
As shown in fig. 4 and fig. 2, the fin 1F exposed at the top of STI 2 part (namely
Following channel region 1C) on form first high mobilities different from fin 1F/ 1 materials of substrate
Layer 4, namely the carrier mobility of layer 4 is more than 1/ fin 1F of substrate.By MOCVD,
The epitaxial growth of the technique such as MBE, ALD is partly led selected from III--V races, II--VI races, V compounds of group
The high mobility material of body, such as SiGe, SiC, SiGeC, SiGeSn, SiGaN,
SiGaP, SiGaAs, InSiN, InSiP, InSiAs, InSiSb any one and combinations thereof
High mobility material or their component proportion material, such as SiGeSn, SiInGaAs.At this
In one preferred embodiment of invention, adjust deposition process parameters, be particularly unstripped gas proportioning, make
The content for obtaining the non-Si elements (such as Ge) on close fin 1F surfaces in layer 4 is relatively low, excellent
Select less than 30%, less than 20% even below 10%, so that from the exposed surface of layer 4
The 1C interfaces descending concentrations to layer 4 and fin 1F/ and there is larger concentration gradient,
It is easy to further element thermal diffusion.
As shown in Fig. 4 and Fig. 3, oxidation and/or nitriding process are performed, by the first high mobility layer 4
It is partly or completely oxidized into dielectric layer 5, while so that 1C is changed into the second Gao Qian at the top of fin 1F
Shifting rate layer 6.Oxidation and/or nitridation (in the heat treatment of the atmosphere high temperature comprising oxygen or nitrogen)
Such as 800～1300 DEG C, preferably 900～1100 DEG C of technological temperature, optimal 1000 DEG C, when
Between such as 10min～2h, preferred 20min～1h, optimal 30min.Oxidation and/or nitridation make
The Si elements obtained in layer 4 combine to form silica or nitridation silicon-based dielectric material, rather than Si with O/N
Element due to concentration gradient presence and spreading to 1C at the top of fin 1F, and in the 1C of top
Redistribute and combine, define the second high mobility layer 6.Second high mobility layer, 6 material can
With same or like with the first high mobility layer material 4.In the process, due to optionally depositing
In doped region 3 and in doped region 3, the atomic number of doped chemical is less than the first high mobility
(namely element is bigger with the bond strength of Si in doped region 3, formation for non-Si elements in layer 4
Cancellated mesh size is less, beneficial to entirely prevent atomic number it is big (correspondingly size compared with
Elements Diffusion migration greatly)), therefore the diffusion of non-Si elements will be stopped on doped region 3,
Prevent bottom break-through, reduce substrate leakage.Furthermore it is noted that working as 4 quilt of layer
When complete oxidation and/or nitridation, the interface at the top of layer 4 and fin 1F between 1C also simultaneously can be by portion
Divide oxidation and/or nitrogenize, so as to further reduce the live width of channel region 1C, be conducive to into one
Step improves device integration.
Hereafter, can etch and remove 6 at the top of the fin of the exposure high mobility material of dielectric layer 5, sink
Product is developed across the gate stack of channel region, in the fin of gate stack both sides forms source and drain
Area, forms the interlayer dielectric layer (ILD) for covering whole chip, and etching ILD forms contact hole simultaneously
Filling metal realizes that source and drain is interconnected, and is finally completed FinFET manufacture.
According to the method, semi-conductor device manufacturing method of the present invention, by aoxidizing the Gao Qian as sacrifice layer
Shifting rate material, orders about ion and spreads so that the fin that backing material is constituted is converted to high mobility material
Material, improves device performance and beneficial to device micro with Simplified flowsheet and low cost.
Although with reference to one or more exemplary embodiments explanation present invention, people in the art
Member could be aware that and various suitable changes are made without departing from the scope of the invention and to device architecture
And equivalents.Additionally, by disclosed teaching can make many can be adapted to particular condition or
The modification of material is without deviating from the scope of the invention.Therefore, the purpose of the present invention does not lie in and is limited to
It is as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed
Device architecture and its manufacture method will include all embodiments for falling within the scope of the present invention.
Claims (8)
1. a kind of method, semi-conductor device manufacturing method, including：
Etched substrate forms multiple fins；
STI is formed between fin；
The first high mobility layer is formed on the fin portion for expose STI；
Perform oxidation and/or nitriding process, by the first high mobility layer be changed into dielectric layer and while
The fin portion for exposing STI is changed into into the second high mobility layer.
2. method as claimed in claim 1, wherein, perform oxidation and/or nitriding process cause it is first high
Non- Si Elements Diffusions in mobility layer are to the fin portion for exposing STI and fin material
Reconfigure to form the second high mobility layer.
3. method as claimed in claim 1, wherein, before the first high mobility layer is formed or it
Afterwards, individually or together being formed prevents what non-element silicon in high mobility layer from spreading to substrate
Barrier layer and anti-break-through barrier layer.
4. method as claimed in claim 3, wherein, in preventing high migrating layer, non-element silicon expands to substrate
The atomic number of ion is injected in scattered barrier layer less than non-in the first high mobility layer
Si elements, to prevent non-Si Elements Diffusions to substrate.
5. method as claimed in claim 4, wherein, the ion of injection is selected from C, N, O, F, S
Any one and combinations thereof.
6. method as claimed in claim 3, wherein, the doped chemical on anti-break-through barrier layer is according to device
Different type select three races or group-v element with itself or with other race's elements compositions
Simple substance or compound.
7. method as claimed in claim 1, wherein, the material of the first high mobility layer selected from III--V races,
Any one of II--VI races, V compound semiconductors and combinations thereof.
8. method as claimed in claim 1, wherein, further wrap after forming the second high mobility layer
Include, the gate stack being developed across on the second high mobility layer, in gate stack both sides
The second high mobility layer in form source-drain area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510634782.9A CN106558496B (en) | 2015-09-29 | 2015-09-29 | Semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510634782.9A CN106558496B (en) | 2015-09-29 | 2015-09-29 | Semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106558496A true CN106558496A (en) | 2017-04-05 |
| CN106558496B CN106558496B (en) | 2019-09-24 |
Family
ID=58414918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510634782.9A Active CN106558496B (en) | 2015-09-29 | 2015-09-29 | Semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106558496B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080237575A1 (en) * | 2007-03-29 | 2008-10-02 | Been-Yih Jin | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications |
| CN104701168A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field-effect transistor |
| US20150194525A1 (en) * | 2014-01-03 | 2015-07-09 | Qualcomm Incorporated | Silicon germanium finfet formation by ge condensation |
-
2015
- 2015-09-29 CN CN201510634782.9A patent/CN106558496B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080237575A1 (en) * | 2007-03-29 | 2008-10-02 | Been-Yih Jin | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications |
| CN104701168A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin field-effect transistor |
| US20150194525A1 (en) * | 2014-01-03 | 2015-07-09 | Qualcomm Incorporated | Silicon germanium finfet formation by ge condensation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106558496B (en) | 2019-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4847152B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9023715B2 (en) | Methods of forming bulk FinFET devices so as to reduce punch through leakage currents | |
| KR100855977B1 (en) | Semiconductor device and methods for manufacturing the same | |
| JP5728444B2 (en) | Semiconductor device and manufacturing method thereof | |
| US9548387B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN105280707A (en) | Semiconductor structure and manufacturing method thereof | |
| US7888194B2 (en) | Method of fabricating semiconductor device | |
| JP2007258485A (en) | Semiconductor device and its manufacturing method | |
| TW201010059A (en) | Integrated circuits | |
| CN103928518A (en) | Finfet Device And Method Of Fabricating Same | |
| KR20120035699A (en) | Semiconductor devices including source/drain regions with abrupt junction profiles and methods of fabricating the same | |
| JP2009010111A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN105448834B (en) | The different semiconductor structure bodies of transistor channels strain regime and its manufacturing method | |
| US8847224B2 (en) | Fin-based bipolar junction transistor and method for fabrication | |
| TWI708372B (en) | Semiconductor memory structure and method of manufacturing the same | |
| CN104037083B (en) | Manufacture method of semiconductor device | |
| KR100864631B1 (en) | Transistor of semiconductor device and method for fabricating the same | |
| JPS62155552A (en) | Simultaneous manufacture of bipolar transistor and cmos transistor | |
| CN106816467A (en) | Semiconductor device and its manufacture method | |
| EP1225624A3 (en) | A method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) | |
| CN106549016A (en) | Semiconductor device and method for manufacturing the same | |
| CN103367227B (en) | Semiconductor device manufacturing method | |
| CN101908485A (en) | Method for manufacturing vertical bipolar transistor by utilizing three mask plates | |
| CN106558496A (en) | Semiconductor device manufacturing method | |
| CN115332319A (en) | Method for manufacturing semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |