CN106558288B - Gate driving circuit, display device and gate pulse modulating method - Google Patents
Gate driving circuit, display device and gate pulse modulating method Download PDFInfo
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- CN106558288B CN106558288B CN201510619839.8A CN201510619839A CN106558288B CN 106558288 B CN106558288 B CN 106558288B CN 201510619839 A CN201510619839 A CN 201510619839A CN 106558288 B CN106558288 B CN 106558288B
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Abstract
A kind of gate driving circuit, comprising: multiple gate drivers interconnected；First discharge circuit, multiple gate drivers are grounded through first discharge circuit；Each gate drivers include the second discharge circuit, which is connected between the gate drivers and a gate off voltage；When the gate driving circuit executes top rake movement, which is discharged by first discharge circuit with second discharge circuit simultaneously.By setting, the first discharge circuit and the second discharge circuit discharge gate driving circuit of the invention simultaneously on a printed circuit when executing top rake movement, reduce top rake amplitude difference between adjacent gate drivers so as to imitate.
Description
Technical field
The present invention relates to a kind of gate driving circuits, use the display device and gate pulse modulation of the gate driving circuit
Method.
Background technique
Existing Thin Film Transistor-LCD (TFT-LCD) is by carrying out top rake modulation to grid impulse signal, to subtract
Film flicker (flicker) phenomenon caused by scanning line back end feedthrough (Feed Through) voltage is different less.So due to liquid
The continuous increase of crystal display size needs to export grid impulse signal using multiple gate drivers, and adjacent grid drives
Top rake amplitude between dynamic device causes to differ greatly due to component self character difference.
Summary of the invention
In view of this, it is necessary to provide gate driving circuit, display device and gate pole arteries and veins that one kind can promote top rake amplitude
Rush modulating method.
A kind of gate driving circuit, comprising: multiple gate drivers interconnected；Each gate drivers include grid
Pulse modulation main circuit；The grid-pulse modulation main circuit exports grid voltage by output end；First discharge circuit, it is multiple
Gate drivers are grounded through first discharge circuit；Each gate drivers include the second discharge circuit, second discharge circuit
It is connected between the discharge end of the gate drivers and a gate off voltage；When the gate driving circuit executes top rake movement
When, which is discharged with second discharge circuit simultaneously by first discharge circuit, with to the grid voltage into
Row top rake；
Each gate drivers further include being connected between gate turn-on voltage and the discharge end of the gate drivers
Precharge switch；The discharge end of multiple gate drivers is interconnected through electrically conducting transparent route, the every two adjacent grid
The equivalent resistance of the opaque line between the discharge end of driver generates parasitic capacitance；In first time period, the gate driving
Circuit is discharged by first discharge circuit, while the precharge switch is closed, so that the grid voltage is to the parasitism
Capacitor charging；Second time period after the first time period, which disconnects, while the gate driving circuit passes through
First discharge circuit and second discharge circuit discharge simultaneously.
A kind of grid-pulse modulation method, applied to the gate driving circuit of output grid control signal, the gate driving
Circuit includes multiple gate drivers interconnected；Each gate drivers include grid-pulse modulation main circuit；The grid
Pulse modulation main circuit exports grid voltage by output end；First discharge circuit, multiple gate drivers first are put through this
Electric circuit ground；Each gate drivers include the second discharge circuit, which is connected to the gate drivers
Between discharge end and gate off voltage；The grid-pulse modulation method includes: when the gate driving circuit starts to execute top rake
When movement, which discharges simultaneously through first discharge circuit and second discharge circuit, to the grid voltage
Carry out top rake；
Each gate drivers further include being connected between gate turn-on voltage and the discharge end of the gate drivers
Precharge switch；The discharge end of multiple gate drivers is interconnected through electrically conducting transparent route, the every two adjacent grid
The equivalent resistance of the opaque line between the discharge end of driver generates parasitic capacitance；In first time period, the gate driving
Circuit is discharged by first discharge circuit, while the precharge switch is closed, so that the grid voltage is to the parasitism
Capacitor charging；Second time period after the first time period, which disconnects, while the gate driving circuit passes through
First discharge circuit and second discharge circuit discharge simultaneously.
A kind of display device, comprising: display panel；Gate driving circuit exports grid control signal to the display panel,
The gate driving circuit is connect through flexible circuit board with the display panel；The gate driving circuit includes: multiple interconnected
Gate drivers；The gate drivers include grid-pulse modulation main circuit；The grid-pulse modulation main circuit passes through output end
Export grid voltage；First discharge circuit, multiple gate drivers are grounded through first discharge circuit；Each gate drivers
Including the second discharge circuit, second discharge circuit be connected to the gate drivers discharge end and a gate off voltage it
Between；When the gate driving circuit executes top rake movement, which second is put by first discharge circuit with this
Circuit discharges simultaneously, to carry out top rake to the grid voltage；
Each gate drivers further include being connected between gate turn-on voltage and the discharge end of the gate drivers
Precharge switch；The discharge end of multiple gate drivers is interconnected through electrically conducting transparent route, the every two adjacent grid
The equivalent resistance of the opaque line between the discharge end of driver generates parasitic capacitance；In first time period, the gate driving
Circuit is discharged by first discharge circuit, while the precharge switch is closed, so that the grid voltage is to the parasitism
Capacitor charging；Second time period after the first time period, which disconnects, while the gate driving circuit passes through
First discharge circuit and second discharge circuit discharge simultaneously.
Compared to the prior art, gate driving circuit of the invention is when executing top rake movement by being arranged in printed circuit
The first discharge circuit and the second discharge circuit discharge simultaneously on plate, reduce top rake amplitude between adjacent gate drivers so as to imitate
Difference.
Detailed description of the invention
Fig. 1 is one embodiment structure schematic diagram of display device of the invention.
Fig. 2 is the gate driving circuit schematic equivalent circuit of display device shown in Fig. 1.
Fig. 3 is the physical circuit schematic diagram of grid impulse tune main circuit shown in Fig. 2.
Fig. 4 is signal timing diagram when grid-pulse modulation main circuit shown in Fig. 3 works.
Fig. 5 is gate driving circuit control signal timing diagram shown in Fig. 2.
Main element symbol description
The present invention that the following detailed description will be further explained with reference to the above drawings.
Specific embodiment
Referring to Fig. 1, Fig. 1 is 10 1 embodiment structure schematic diagram of display device of the invention.The display device 10 packet
Include display panel 110, gate driving circuit 122 and data driver 130.The gate driving circuit 122 passes through GOA (Gate on
Array) technology setting is in 110 side of display panel, the data driver 130 setting with 122 phase of gate driving circuit
Adjacent side.The gate driving circuit 122 exports grid control signal to the display panel 110.The data driver 130 exports number
According to driving signal to the display panel 110.The gate driving circuit 122 includes multiple gate drivers.In the present embodiment,
The gate driving circuit 122 tool is respectively designated as being illustrated for 122a, 122b, 122c there are three gate drivers, can be with
Understand, the quantity of multiple gate drivers 122a-122c can be changed with the need, is not limited thereto.Multiple gate driving
Through conducting wire in array (Wire On Array, WOA), be one another in series device 122a-122c (Cascade).Each gate drivers
122a, 122b, 122c drive a region of the display panel 110.
Referring to Figure 2 together, Fig. 2 is the schematic equivalent circuit of gate drivers 122a-122c shown in Fig. 1.Each should
Gate drivers 122a-122c further comprises the first discharge circuit 123.First discharge circuit 123 includes discharge resistance
Rex, one end of discharge circuit Rex are connected to multiple gate drivers 122a, 122b, 122c, other end ground connection.It is multiple
Gate drivers 122a-122c is grounded through first discharge circuit 123.
Each gate drivers 122a-122c includes a discharge end DX, grid-pulse modulation main circuit 20, precharge switch
1221 and second discharge circuit 1223.The precharge switch 1221 is connected to gate turn-on voltage VGH and drives with the corresponding grid
Between the discharge end DX of dynamic device 122a-122c, which is connected to corresponding gate drivers 122a-
Between the discharge end DX and gate off voltage VGL of 122c.Second discharge circuit 1223 includes discharge control switch S, when this
When gate drivers 122a-122c executes top rake movement, discharge control switch S closure.In the present embodiment, the low-voltage
Level is earthing potential.The discharge end DX of multiple gate drivers 122a-122c is interconnected through electrically conducting transparent route, and every two
Electrically conducting transparent route between the discharge end DX of adjacent gate drivers 122a-122c has equivalent resistance 124.Due to the grid
The electric discharge of driver 122a-122c top rake needs, and the resistance setting of second discharge circuit 1223 is sufficiently large, i.e. second electric discharge
The resistance value of circuit 1223 is greater than the resistance value of first discharge circuit 123.In the present embodiment, the electricity of second discharge circuit 1223
Resistance is 12K Ω or 19K Ω, and the resistance value of first discharge circuit 123 is 4K Ω.
It is the physical circuit schematic diagram of grid impulse tune main circuit 20 shown in Fig. 2 also referring to Fig. 3, Fig. 3.The grid
Pulse modulation main circuit 20 is for exporting grid voltage to display panel 110.The grid-pulse modulation main circuit 20 includes one defeated
Outlet OT, logic control gate 210, switch on the bridge 220, bridge switch 230 and reverser 240.The logic control gate
210, the switch on the bridge 220 and bridge switch 230 are sequentially connected in series between gate turn-on voltage VGH and gate off voltage VGL.
The reverser 240 is for receiving conductivity control signal CT to control the conducting and shutdown of the upper and lower bridge switch 220,230.From this
The intermediate node LX of switch on the bridge 220 and bridge switch 230 draws output end OT, and the grid-pulse modulation main circuit 20 is defeated from this
Outlet OT exports grid pulse modulation signal to display panel 110.
The logic control gate 210 includes grid power supply input terminal L, electric discharge output end H, first control signal input terminal
IN1, second control signal input terminal IN2 and power supply signal output end vo.One grid of grid power supply input terminal L connection opens electricity
VGH, the electric discharge output end H is pressed to connect gate off voltage VGL through discharge resistance Rex, first control signal input terminal IN1
For receiving clock signal clk, the second control signal input terminal IN2 is for receiving enable signal OE, power supply signal output
Vo is held to export grid voltage for selectivity.
In the present embodiment, which is a PMOS (P-Metal Oxide Semiconductor) crystal
Pipe, the bridge switch 230 are a NMOS (N-Metal Oxide Semiconductor) transistor.The source of the switch on the bridge 220
Pole is connect with the power supply signal output end vo, and the drain of the switch on the bridge 220 is electrically connected with the drain of the bridge switch 230, should
The source electrode of bridge switch 230 is grounded, the switch on the bridge 220, bridge switch 230 grid be electrically connected with the reverser 240.It should
Node LX is located between the drain of the switch on the bridge 220 and the drain of the bridge switch 230.
Referring to Figure 4 together, Fig. 4 is signal timing diagram when grid-pulse modulation main circuit 20 shown in Fig. 3 works.?
First time period T1, the reverser 240 receive conductivity control signal CT and control the switch on the bridge 220 conducting, bridge switch 230
Shutdown, in the present embodiment, conductivity control signal CT are high levle signal, after the reverser 240 is reversed, the conducting control
Signal CT processed controls the switch on the bridge 220 conducting, bridge switch 230 turns off.Meanwhile the logic control gate 210 to this when
Clock signal CLK and enable signal OE do logical operation, and in the present embodiment, in first time period, which is
High levle signal, enable signal OE are low level signal.The logic control gate 210 is to the clock signal clk and enables
Signal OE does or non-operation, and when operation result is the first numerical value, in the present embodiment, which is logical value " 1 "
When, which makes real between the grid power supply input terminal L and the two ports of power supply signal output end vo
It now conducts, being electrically connected between shutdown the grid power supply input terminal L and the electric discharge output end H of simultaneous selection.At this time should
Gate turn-on voltage VGH exports grid pulse modulation signal through the power supply signal output end vo, switch on the bridge 220 and node LX
Gout is to display panel 110.
In second time period T2, the reverser 240 receive conductivity control signal CT control the switch on the bridge 220 conducting,
Bridge switch 230 turns off.Meanwhile the logic control gate 210 does or non-operation to the clock signal clk and enable signal,
When operation result is second value, in the present embodiment, when which is logical value " 0 ", logic control gating
Device 210 turns off being electrically connected between the grid power supply input terminal L and the power supply signal output end vo, while keeping the grid power supply defeated
Enter to hold that realizes between L and electric discharge output end H to conduct.In the present embodiment, in second time period, the clock signal
CLK is low level signal, and enable signal OE is low level signal.At this time display panel 110 through the switch on the bridge 220, this puts
Electricity output end H, discharge resistance Rex discharge, and grid pulse modulation signal Gout, which is dragged down, makes the grid impulse tune
Signal Gout processed forms a top rake.
It is low level signal in third period T3, conductivity control signal CT, the reverser 240 receives the conducting at this time
Control signal CT controls the switch on the bridge 220 shutdown, bridge switch 230 is connected, and the display panel 110 is through the bridge switch 230
Electric discharge completely.
The mathematical analysis of variables separation is done to the first discharge circuit 123 and the second discharge circuit 1223 below.When this second
When the discharge control switch S of discharge circuit 1223 is opened, discharge resistance Rex resistance value is 4K Ω, i.e. gate drivers 122a,
122b and 122c only passes through first discharge circuit 123 electric discharge.Equivalent resistance through second discharge circuit 1223 is denoted as R1, warp
The equivalent resistance of first discharge circuit 123 is denoted as R2, the grid impulse tune of the gate drivers 122a, 122b and 122c output
Varying signal is denoted as G1, G2, G3 respectively, and the resistance value of the equivalent resistance 124 is 160 Ω, and associated calculated values please join table 1.
Table 1
| 122a | 122b | 122c | R1 | R2 | 16V/R2 | Gn/G3 | G(n-1)-Gn | |
| 122c | ∞ | ∞ | ∞ | ∞ | 4570 | 5579.87uA | 100% | -- |
| 122b | ∞ | ∞ | ∞ | ∞ | 4410 | 5782.31uA | 103.63% | 3.63% |
| 122a | ∞ | ∞ | ∞ | ∞ | 4250 | 6000uA | 107.53% | 3.90% |
When the discharge control switch S of second discharge circuit 1223 is closed, discharge resistance Rex resistance value is infinity, i.e.,
The gate drivers 122a, 122b and 122c only pass through first discharge circuit 123 electric discharge.Through second discharge circuit 1223
Equivalent resistance is denoted as R1=12k Ω, and the equivalent resistance through first discharge circuit 123 is denoted as R2, gate drivers 122a,
The grid-pulse modulation signal of 122b and 122c output is denoted as G1, G2, G3 respectively, and the resistance value of the equivalent resistance 124 is 160 Ω,
Associated calculated values please join table 2.
Table 2
| 122a | 122b | 122c | R1 | R2 | 16V/R2 | Gn/G3 | G(n-1)-Gn | |
| 122c | 12480 | 12320 | 12000 | 4087.8 | 4087.8 | 6849.65uA | 100% | -- |
| 122b | 12160 | 12000 | 12160 | 4035.4 | 4035.4 | 6938.60uA | 101.3% | 1.3% |
| 122a | 12000 | 12320 | 12480 | 4087.8 | 4087.8 | 6849.65uA | 100.% | - 1.3% |
When the discharge control switch S of second discharge circuit 1223 is closed, the resistance value of discharge resistance Rex is 4K Ω, i.e.,
Gate drivers 122a, 122b and 122c passes through first discharge circuit 123 simultaneously and second discharge circuit 1223 discharges
When.Equivalent resistance through second discharge circuit 1223 is denoted as R1=12k Ω, the equivalent resistance through first discharge circuit 123
It is denoted as R2, the grid-pulse modulation signal of the gate drivers 122a, 122b and 122c output is denoted as G1, G2, G3 respectively, this etc.
The resistance value for imitating resistance 124 is 160 Ω, and associated calculated values please join table 3.
Table 3
| 122a | 122b | 122c | R1 | R2 | 16V/R2 | Gn/G3 | G(n-1)-Gn | |
| 122c | 19646 | 19486 | 19166 | 6476.87 | 2679.43 | 5971.42uA | 100% | -- |
| 122b | 19326 | 19166 | 19326 | 6424.12 | 2614.92 | 6118.73uA | 102.47% | 2.47% |
| 122a | 19166 | 19486 | 19646 | 6476.87 | 2566.14 | 6235.04uA | 104.41% | 1.95% |
By known to table 1- table 3 gate drivers 122a, 122b and 122c pass through simultaneously first discharge circuit 123 with
When second discharge circuit 1223 discharges, the top rake amplitude between adjacent gate drivers 122a-122c, which changes, to be reduced.
Please refer to fig. 5, Fig. 5 is gate driving circuit control signal timing diagram shown in Fig. 2.The gate driving circuit
The clock signal clk of 122 reception sequence controller (not shown) outputs controls the gate driving circuit 122 and grid unlatching electricity
Control signal VGH_EN that whether pressure VGH connects, whether the gate driving circuit 122 is controlled by first discharge circuit 123
The control signal ERC_EN of electric discharge, it controls the control signal GLO_P of the precharge switch 1221 and controls the discharge control switch
Control signal GLO_N.
In the P1 period, control first discharge circuit 123 electric discharge control signal ERC_EN by low potential transition for height
Current potential, the control signal GLO_P for controlling the precharge switch 1221 are established by cable by high potential transition for low potential with controlling the preliminary filling
Close 1221 closures.The gate driving circuit 122 discharges through first discharge circuit 123 at this time, while gate turn-on voltage VGH
The parasitic capacitance generated to the equivalent resistance 124 between every two gate drivers 122a-122c is pre-charged.In this embodiment party
In formula, which is a PMOS (P-Metal Oxide Semiconductor) transistor.
The discharge control switch is controlled when the gate driving circuit 122 starts to execute top rake movement in the P2 period
Control signal GLO_N by low potential transition be high potential, at this time the gate driving circuit 122 through first discharge circuit 123 with
Second discharge circuit 1223 discharges simultaneously.Period P2 includes aforementioned second time period T2.
In the P3 period, control first discharge circuit 123 electric discharge control signal ERC_EN by high potential transition be it is low
Current potential, the gate driving circuit 122 is only discharged by second discharge circuit 1223 at this time.
Gate driving circuit 122 above-mentioned is when executing top rake movement by the way that the first electric discharge electricity on a printed circuit is arranged
Road 123 and the second discharge circuit 1223 discharge simultaneously, reduce top rake width between adjacent gate drivers 122a-122c so as to imitate
Spend difference.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the invention, when can make it is a little change and retouch, therefore it is of the invention
Protection scope after view subject to attached claim institute defender.
Claims (7)
1. a kind of gate driving circuit, comprising:
Multiple gate drivers interconnected；Each gate drivers include grid-pulse modulation main circuit；The grid impulse
Modulation main circuit exports grid voltage by output end；
First discharge circuit, multiple gate drivers are grounded through first discharge circuit；
Each gate drivers include the second discharge circuit, second discharge circuit be connected to the discharge ends of the gate drivers with
Between one gate off voltage；
When the gate driving circuit executes top rake movement, which second is put by first discharge circuit with this
Circuit discharges simultaneously, to carry out top rake to the grid voltage；
Each gate drivers further include the preliminary filling being connected between gate turn-on voltage and the discharge end of the gate drivers
Electric switch；The discharge end of multiple gate drivers is interconnected through electrically conducting transparent route, the every two adjacent gate driving
The equivalent resistance of the electrically conducting transparent route between the discharge end of device generates parasitic capacitance；In first time period, the gate driving
Circuit is discharged by first discharge circuit, while the precharge switch is closed, so that the grid voltage is to the parasitism
Capacitor charging；Second time period after the first time period, which disconnects, while the gate driving circuit passes through
First discharge circuit and second discharge circuit discharge simultaneously.
2. gate driving circuit as described in claim 1, which is characterized in that it is needed since the gate drivers top rake discharges,
The resistance value of second discharge circuit is greater than the resistance value of first discharge circuit.
3. gate driving circuit as described in claim 1, which is characterized in that second discharge circuit includes that control of discharge is opened
It closes, when the gate driving circuit executes top rake movement, discharge control switch closure.
4. gate driving circuit as described in claim 1, which is characterized in that multiple gate drivers through conducting wire in array that
This series connection.
5. gate driving circuit as described in claim 1, which is characterized in that first discharge circuit includes discharge resistance, should
Discharge resistance is connected between the discharge end and ground of multiple gate drivers.
6. a kind of grid-pulse modulation method, applied to the gate driving circuit of output grid control signal, gate driving electricity
Road includes multiple gate drivers interconnected；Each gate drivers include grid-pulse modulation main circuit；The grid arteries and veins
It reconstitutes change main circuit and grid voltage is exported by output end；First discharge circuit, multiple gate drivers first discharge through this
Circuit ground；Each gate drivers include the second discharge circuit, which is connected to putting for the gate drivers
Between electric end and gate off voltage；The grid-pulse modulation method includes:
When the gate driving circuit start execute top rake movement when, the gate driving circuit through first discharge circuit and this second
Discharge circuit discharges simultaneously, to carry out top rake to the grid voltage；
Each gate drivers further include the preliminary filling being connected between gate turn-on voltage and the discharge end of the gate drivers
Electric switch；The discharge end of multiple gate drivers is interconnected through electrically conducting transparent route, the every two adjacent gate driving
The equivalent resistance of the electrically conducting transparent route between the discharge end of device generates parasitic capacitance；In first time period, the gate driving
Circuit is discharged by first discharge circuit, while the precharge switch is closed, so that the grid voltage is to the parasitism
Capacitor charging；Second time period after the first time period, which disconnects, while the gate driving circuit passes through
First discharge circuit and second discharge circuit discharge simultaneously.
7. a kind of display device, comprising:
Display panel；
Gate driving circuit exports grid control signal to the display panel, and the gate driving circuit is aobvious with this through flexible circuit board
Show that panel connects；
The gate driving circuit includes:
Multiple gate drivers interconnected；Each gate drivers include grid-pulse modulation main circuit；The grid impulse
Modulation main circuit exports grid voltage by output end；
First discharge circuit, multiple gate drivers are grounded through first discharge circuit；
Each gate drivers include the second discharge circuit, second discharge circuit be connected to the discharge ends of the gate drivers with
Between one gate off voltage；
When the gate driving circuit executes top rake movement, which second is put by first discharge circuit with this
Circuit discharges simultaneously, to carry out top rake to the grid voltage；
Each gate drivers further include the preliminary filling being connected between gate turn-on voltage and the discharge end of the gate drivers
Electric switch；The discharge end of multiple gate drivers is interconnected through electrically conducting transparent route, the every two adjacent gate driving
The equivalent resistance of the electrically conducting transparent route between the discharge end of device generates parasitic capacitance；In first time period, the gate driving
Circuit is discharged by first discharge circuit, while the precharge switch is closed, so that the grid voltage is to the parasitism
Capacitor charging；Second time period after the first time period, which disconnects, while the gate driving circuit passes through
First discharge circuit and second discharge circuit discharge simultaneously.
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| CN201510619839.8A CN106558288B (en) | 2015-09-25 | 2015-09-25 | Gate driving circuit, display device and gate pulse modulating method |
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| CN201510619839.8A CN106558288B (en) | 2015-09-25 | 2015-09-25 | Gate driving circuit, display device and gate pulse modulating method |
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| TWI616860B (en) * | 2017-06-27 | 2018-03-01 | 友達光電股份有限公司 | Gate driving circuit and operating method thereof |
| CN108416980A (en) * | 2018-05-10 | 2018-08-17 | 广州爱关怀信息科技有限公司 | Abnormal monitoring alarm system and method based on intelligent decision behavioral data |
| CN109272958A (en) * | 2018-11-09 | 2019-01-25 | 重庆先进光电显示技术研究院 | The driving circuit and its method and display device of display panel |
| CN111681582B (en) | 2020-06-02 | 2021-08-24 | Tcl华星光电技术有限公司 | Scanning driving method, scanning driving device, electronic apparatus, and storage medium |
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|---|---|---|---|---|
| CN101699552A (en) * | 2009-11-16 | 2010-04-28 | 友达光电股份有限公司 | Grid output control method and corresponding grid pulse modulator |
| CN101937640A (en) * | 2010-08-30 | 2011-01-05 | 友达光电股份有限公司 | Grid pulse wave modulation circuit and modulation method thereof |
| CN103247280A (en) * | 2013-05-14 | 2013-08-14 | 深圳市华星光电技术有限公司 | Chamfering circuit and control method thereof |
| CN104575408A (en) * | 2013-10-16 | 2015-04-29 | 天钰科技股份有限公司 | Grid pulse modulation circuit and corner-undercutting modulation method thereof |
| KR20150073544A (en) * | 2013-12-23 | 2015-07-01 | 엘지디스플레이 주식회사 | Gate shift register and and driving method the same |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101699552A (en) * | 2009-11-16 | 2010-04-28 | 友达光电股份有限公司 | Grid output control method and corresponding grid pulse modulator |
| CN101937640A (en) * | 2010-08-30 | 2011-01-05 | 友达光电股份有限公司 | Grid pulse wave modulation circuit and modulation method thereof |
| CN103247280A (en) * | 2013-05-14 | 2013-08-14 | 深圳市华星光电技术有限公司 | Chamfering circuit and control method thereof |
| CN104575408A (en) * | 2013-10-16 | 2015-04-29 | 天钰科技股份有限公司 | Grid pulse modulation circuit and corner-undercutting modulation method thereof |
| KR20150073544A (en) * | 2013-12-23 | 2015-07-01 | 엘지디스플레이 주식회사 | Gate shift register and and driving method the same |
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