CN106549087A - A kind of preparation method of high brightness LED chip - Google Patents
A kind of preparation method of high brightness LED chip Download PDFInfo
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- CN106549087A CN106549087A CN201610963089.0A CN201610963089A CN106549087A CN 106549087 A CN106549087 A CN 106549087A CN 201610963089 A CN201610963089 A CN 201610963089A CN 106549087 A CN106549087 A CN 106549087A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 230000008020 evaporation Effects 0.000 claims abstract description 20
- 238000001704 evaporation Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 18
- 239000001301 oxygen Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000002161 passivation Methods 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 238000000407 epitaxy Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical group [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 2
- 229910052738 indium Inorganic materials 0.000 claims 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 2
- 241001062009 Indigofera Species 0.000 claims 1
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- 238000005516 engineering process Methods 0.000 description 11
- 229910052594 sapphire Inorganic materials 0.000 description 8
- 239000010980 sapphire Substances 0.000 description 8
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- 238000000605 extraction Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
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- 238000005566 electron beam evaporation Methods 0.000 description 5
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- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 206010040844 Skin exfoliation Diseases 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
A kind of preparation method of high brightness LED chip, the crystalline quality of thin film is controlled by the evaporation environment of control ITO conductive extension layers, so as to improve the resistivity of thin film, the square resistance of control thin film, during evaporation ITO, cavity temperature is maintained at 290～310 DEG C, oxygen flow is 5～15sccm, and chamber vacuum degree is maintained at 5 × 10‑4～1 × 10‑5, the effect of piece ITO sheet resistances while can reach thinning ITO conductive extensions layer with this understanding, will not be changed again, i.e., the running voltage of LED chip will not be made to increase.Through experimental verification, the LED chip that the inventive method makes can greatly improve LED chip luminosity and efficiency compared with conventional LED chip.
Description
Technical field
The present invention relates to semiconductor LED field, particularly, is related to a kind of preparation method of high brightness LED chip.
Background technology
GaN material numerous advantages such as have broad stopband, high electronics drift saturated velocity, high heat conductance, chemical stability good,
But due to seldom to GaN body monocrystalline, epitaxial layer dislocation density is big, there is higher N-type concentration of background carriers and p-type is adulterated
The factors such as effect on driving birds is not good limit its development, and recently as the progress of technology, internal quantum efficiency has been achieved for larger entering
Step, but external quantum efficiency is not high.In order to improve the external quantum efficiency of luminous tube, high-performance light emitting diode is obtained, from chip
From the point of view of technical standpoint, following chip technology has been occurred in that.
1st, change the technology of chip profile：When light launch point is in the center of ball, angle of total reflection problem disappears, spherical core
Piece can obtain optimal light extraction efficiency.Change chip geometries carry out the idea of improving extraction efficiency to be just used for early in 20th century
Diode chip for backlight unit, but as cost reason cannot be realized always.Until 1999, hewlette-packard developed truncation golden word
Tower technology, makes the external quantum efficiency of LED reach 55%.
2nd, bonding techniques：In order to more effectively radiate and reduce junction temperature, grown epitaxial layer can be originally used for by removing
Substrate, epitaxial layer bonding is transferred on the conductive and good substrate of heat conductivility.Calendar year 2001, the XBTM series back ofs the body that Cree is released
Face light power cake core, using bonding techniques, under 400mA operating currents, the Output optical power of wavelength 405nm and 470nm
Respectively 250mW, 150mW.
3rd, flip chip technology (fct)：Face-down bonding technique can not only increase chip output, improve light extraction efficiency, moreover it is possible to reduce
Thermal resistance, makes luminous PN junction near heat sink, improves device reliability.Calendar year 2001 U.S. lumileds, company adopted face-down bonding technique
Application on high-power AlINGaN bases chip, external quantum efficiency reach 21%, and power conversion efficiency reaches 20%.
4th, comprehensive reflectance coating/micro mirror：The comprehensive reflectance coating of Metal Substrate can be applicable to positive cartridge chip and also apply be applicable to upside-down mounting
Chip, all can effective improving extraction efficiency.It is 4% or so that ODR mirror structures improve reflection efficiency than flat reflective mirror, right
For the light of wide-angle, reflection efficiency improves 10%-20%.
5th, metal bonding lift-off technology：Hewlett-Packard Corporation of the U.S. using big substrate desquamation technology earliest, by GaAs substrates with
Epitaxial wafer is peeled off, and then epitaxial wafer is bonded on transparent GaP substrates, and luminous efficiency can improve nearly twice.
5 kinds of chip technologies of the above are by changing the contour structures of chip, changing substrate, change chip package knot respectively
Structure, increase reflectance coating and peeling liner bottom mode to improve the light extraction efficiency of LED chip, but while light extraction efficiency is improved,
Other techniques are increased again, do not simplify the structure and processing technology of LED chip.
In addition, Chinese patent 200910202034.8 discloses a kind of method for improving LED chip brightness, the program is also only
Need to scratch the chip unit of formation with laserscribing, draw to Sapphire Substrate, then to road plan side wall solution corrosion,
Gradual change inverted triangle structure is formed in N-GaN layers, program procedure of processing is more, complex procedures.
Separately there is Chinese patent 201010120594.1 to disclose a kind of method of evaporation ITO, the program is by making change ITO
Thickness make the resistance of ITO and epitaxial layer match to make current expansion uniform, and then improve LED chip brightness, in the program
ITO resistances need to be changed according to epitaxial layer, are unfavorable for a large amount of productions；In addition, the evaporation condition in the program is needed in vacuum
Spend up to 5 × 10-6Carry out under conditions of the condition of high vacuum degree of more than Torr, it is high to equipment requirements, it is unfavorable for cost control.
Accordingly, it would be desirable to a kind of scheme, while the light emission rate of LED chip is improved, the resistance of ITO will not change,
And and LED chip manufacturing process will not be increased.
The content of the invention
Present invention aim at a kind of preparation method of high brightness LED chip is provided, to solve what is proposed in background technology
Problem.
For achieving the above object, the invention provides a kind of preparation method of high brightness LED chip, comprises the following steps：
1) epitaxial layer is made on substrate；
2) on epitaxial layer, evaporation thickness isITO conductive extension layers, the composition of ITO conductive extension layers is indium
Tin-oxide, evaporation condition is：Cavity temperature is maintained at 290～310 DEG C, oxygen flow be 5～15sccm, chamber vacuum degree protect
Hold 5 × 10-4～1 × 10-5Torr；
3) grain pattern and structure according to required acquisition, unwanted ITO conductive extensions layer is etched away with epitaxial layer；
4) electrode and passivation layer are made；
5) wafer to carrying the LED chip carries out thinning, back of the body plating, sliver, sorting process and obtains crystal grain.
The epitaxy layer thickness made on substrate in step 1 is 3～8 μm.
It is deposited with using electron beam evaporation equipment in step 2.
The substrate can be the material of sapphire, carborundum, silicon or other suitable grown epitaxial layers.
In the indium tin oxide, indium tin atom quantity ratio is 95：5.
Further, the step that width is 10～30 μm, platform are etched with by step 3 on conductive extension layer with epitaxial layer
The depth of rank is 1～2 μm, and exposes the N-type GaN layer in epitaxial layer, and step 3 is also etched with use on ITO conductive extension layers
In the hole for making electrode, the p-type GaN layer of the last layer of epitaxial layer is exposed by hole, two electrodes, one making of LED chip
On step, another is produced in hole.
Preferably, the passivation layer is using any one in the silicon oxide of insulation transparent, silicon nitride, aluminium oxide.
The thickness of the passivation layer is
Beneficial effect：It is indium tin oxide films (i.e. ITO conductive extensions that the present invention is deposited with a composition of layer in epi-layer surface
Layer), by ITO conductive extension layers are thinned toTo improve the light extraction efficiency of LED chip, due to simple thinning
The square resistance of thin film can be caused to rise, cause the running voltage of LED chip to rise, and the running voltage of LED chip rises meeting
The luminous efficiency of LED chip is caused to reduce, (cavity temperature keeps the present invention by controlling the evaporation environment of ITO conductive extension layers
At 290～310 DEG C, oxygen flow is 5～15sccm, and chamber vacuum degree is maintained at 5 × 10-4～1 × 10-5) controlling thin film
Crystalline quality, so as to improve the resistivity of thin film, controls the square resistance of thin film, reaches in the same of thinning ITO conductive extensions layer
When, the running voltage of LED chip will not be made again to increase.Through experimental verification, the inventive method makes LED chip and tradition LED
Chip is compared, and can greatly improve LED chip luminosity.
In addition, thinning with ITO conductive extension layers, absorption of the thin film to light is decreased obviously, while board run time
Also substantially shorten, improving productivity is had clear improvement, be suitable to a large amount of productions, advantageously reduce cost.
In addition to objects, features and advantages described above, the present invention also has other objects, features and advantages.
Below with reference to figure, the present invention is further detailed explanation.
Description of the drawings
The accompanying drawing for constituting the part of the application is used for providing a further understanding of the present invention, the schematic reality of the present invention
Apply example and its illustrate, for explaining the present invention, not constituting inappropriate limitation of the present invention.In the accompanying drawings：
Fig. 1 is the LED chip interlayer structure figure of the preferred embodiment of the present invention.
In figure：11- Sapphire Substrates, 22- cushions, 33-N type GaN layers, 44- multi layer quantum wells, 55-P type GaN layers,
66-ITO conductive extension layers, 661- holes, 88-P type electrodes, 99-N type electrodes, 100- steps.
Specific embodiment
Embodiments of the invention are described in detail below in conjunction with accompanying drawing, but the present invention can be limited according to claim
Multitude of different ways that is fixed and covering is implemented.
In following examples and comparative example with sapphire as substrate make GaN base LED blue chip, each embodiment and
Comparative example makes 1000 wafer (wafer) samples, and 1000 crystal grain, every crystallite dimension are made on every wafer piece
For 18mil*35mil.
Referring to the high brightness LED chip of Fig. 1, the present invention has following several specific implementation process：
Embodiment one
In 11 grown epitaxial layer of Sapphire Substrate, epitaxial layer includes cushion 22, the N-type GaN layer 33, multilamellar for growing successively
SQW 44 and p-type GaN layer 55,6 μm of epitaxy layer thickness, deposited by electron beam evaporation board are deposited with one layerThe ITO of thickness leads
Electric extension layer 66, evaporation condition：290 DEG C of cavity temperature, oxygen flow 5sccm, coating process chamber vacuum degree 5.0 × 10-5~
7.0×10-5Torr, 150min (heating-up time containing filament heating, pumpdown time, other necessary preparation times and steaming when sharing
The plating time), then unnecessary ITO conductive extension layers are exposed with photoetching process, use FeCl3Lose with the mixed solution wet method of HCl
Carve exposed ITO conductive extensions layer, expose step 100 and N-type GaN layer, etching depth with ICP etching machine bench etching epitaxial wafer
1.3-1.5 μm, P-type electrode 88 is made in the hole 661 of ITO conductive extension layers, make N-type electrode on N-type GaN step
99, then passivation layer is made with PECVD (plasma enhanced chemical vapor deposition method) deposition SiO2, then test metal electrode
With the adhesion between conductive extension layer, then after the completion of processing step wafer is thinning, back silver-plated reflecting layer, cutting splitting, point are surveyed
Sorting etc..Test electric current 150mA, chip light emitting brightness 170mW, positive running voltage 3.025V, 135 minutes pumpdown times,
2050 hour/of heat filament average life.
Embodiment two
Grown epitaxial layer on a sapphire substrate, 6 μm of epitaxy layer thickness, deposited by electron beam evaporation board are deposited with one layer
The ITO conductive extension layers of thickness, evaporation condition：300 DEG C of cavity temperature, oxygen flow 10sccm, coating process chamber vacuum degree
1.0×10-5～3.0 × 10-5Torr, 152min when sharing, then carries out photoetching process and exposes unnecessary ITO conductive extensions
Layer, uses FeCl3Fall exposed ITO conductive extensions layer with the mixed solution wet etching of HCl, and carve on ITO conductive extension layers
Pit hole, exposes step and N-type GaN layer with ICP etching machine bench etching epitaxial wafer, and 1.3-1.5 μm of etching depth is conductive in ITO
P-type electrode is made on extension layer, N-type electrode is made in N-type GaN, then passivation layer is made with PECVD deposition SiO2, then
Adhesion between test metal electrode and conductive extension layer, then after the completion of processing step wafer is thinning, back silver-plated reflecting layer, cut
Isolate piece, point and survey sorting etc..Test electric current 150mA chip light emitting brightness 175mW, positive running voltage 3.027V, during evacuation
Between 140 minutes, 2000 hour/of heat filament average life.
Embodiment three
Grown epitaxial layer on a sapphire substrate, 6 μm of epitaxy layer thickness, deposited by electron beam evaporation board are deposited with one layer
The ITO conductive extension layers of thickness, evaporation condition：300 DEG C of cavity temperature, oxygen flow 12sccm, coating process chamber vacuum degree
6.0×10-5～7.0 × 10-5Torr, 145min when sharing, then carries out photoetching process and exposes unnecessary ITO conductive extensions
Layer, uses FeCl3Fall exposed conductive extension layer, and the etched hole on ITO conductive extension layers with the mixed solution wet etching of HCl
Hole, exposes step and N-type GaN layer, 1.3-1.5 μm of etching depth, in ITO conductive extensions with ICP etching machine bench etching epitaxial wafer
P-type electrode is made in the hole of layer, N-type electrode is made in N-type GaN, then passivation layer is made with PECVD deposition SiO2, so
The adhesion tested between metal electrode and conductive extension layer afterwards, then after the completion of processing step wafer is thinning, back silver-plated reflecting layer,
Cutting splitting, point survey sorting etc..Test electric current 150mA, chip light emitting brightness 178mW, positive running voltage 3.028V, evacuation
132 minutes time, 2050 hour/of heat filament average life.
Example IV
Grown epitaxial layer on a sapphire substrate, 6 μm of epitaxy layer thickness, deposited by electron beam evaporation board are deposited with one layer
The ITO conductive extension layers of thickness, evaporation condition：310 DEG C of cavity temperature, oxygen flow 15sccm, coating process chamber vacuum degree
4.0×10-4～5.0 × 10--4Torr, 120min when sharing, then carries out photoetching process and exposes redundance conductive extension
Layer, uses FeCl3Fall exposed conductive extension layer, and the etched hole on ITO conductive extension layers with the mixed solution wet etching of HCl
Hole, exposes step and N-type GaN layer, 1.3-1.5 μm of etching depth, on conductive extension layer with ICP etching machine bench etching epitaxial wafer
P-type electrode is made, N-type electrode is made in N-type GaN, then passivation layer is made with PECVD deposition SiO2, then test metal
Adhesion between electrode and conductive extension layer, then after the completion of processing step wafer is thinning, back silver-plated reflecting layer, cutting splitting,
Point surveys sorting etc..Test electric current 150mA, chip light emitting brightness 185mW, positive running voltage 3.032V, 110 points of pumpdown time
Clock, 1950 hour/of heat filament average life.
Comparative example one
One evaporation condition of comparative example：310 DEG C of cavity temperature, oxygen flow 16sccm, coating process chamber vacuum degree 4.0 ×
10-4～5.0 × 10--4Torr, remaining parameter are identical with example IV, 120min when sharing.Test electric current 150mA, chip light emitting
Brightness 187mW, positive running voltage 3.102V, 110 minutes pumpdown times, 1950 hour/of heat filament average life.
Comparative example two
Two evaporation condition of comparative example：290 DEG C of cavity temperature, oxygen flow 4sccm, coating process chamber vacuum degree 5.0 ×
10-5～7.0 × 10-5Torr, remaining parameter are identical with embodiment one, 160min when sharing.Test electric current 150mA, chip light emitting
Brightness 160mW, positive running voltage 3.001V, 135 minutes pumpdown times, 2050 hour/of heat filament average life.
Comparative example three
Three evaporation condition of comparative example：310 DEG C of cavity temperature, oxygen flow 15sccm, coating process chamber vacuum degree 6.0 ×
10-4～7.0 × 10-4Torr, remaining parameter are identical with example IV, 110min when sharing.Test electric current 150mA, chip light emitting
Brightness 175mW, positive running voltage 3.092V, 100 minutes pumpdown times, 1950 hour/of heat filament average life.
Comparative example four
Four evaporation condition of comparative example：300 DEG C of cavity temperature, oxygen flow 10sccm, coating process chamber vacuum degree 8.0 ×
10-6～9.0 × 10-6Torr, remaining parameter are identical with embodiment two, 177min when sharing.Test electric current 150mA, chip light emitting
Brightness 172mW, positive running voltage 3.053V, 165 minutes pumpdown times, 2000 hour/of heat filament average life.
Comparative example five
Five evaporation condition of comparative example：285 DEG C of cavity temperature, oxygen flow 5sccm, coating process chamber vacuum degree 5.0 ×
10-5～7.0 × 10-5Torr, remaining parameter are identical with embodiment one, 150min when sharing.Test electric current 150mA, chip light emitting
Brightness 165mW, positive running voltage 3.121V, 135 minutes pumpdown times, 2100 hour/of heat filament average life.
Comparative example six
Six evaporation condition of comparative example：315 DEG C of cavity temperature, oxygen flow 15sccm, coating process chamber vacuum degree 4.0 ×
10-4～5.0 × 10-4Torr, remaining parameter are identical with example IV, 120min when sharing.Test electric current 150mA, chip light emitting
Brightness 187mW, positive running voltage 3.045V, 110 minutes pumpdown times, 1500 hour/of heat filament average life.
The Contrast on effect such as table 1 of each embodiment and comparative example.
Table 1
Can be seen that when oxygen flow is between 5～15sccm from embodiment one to the example IV of table 1, and cavity
Temperature is maintained at 290～310 DEG C, and chamber vacuum degree is maintained at 5 × 10-4～1 × 10-5During Torr, ITO thickness fromSubtract
It is as thin asThe luminosity of chip is gradually increasing, while running voltage is remained unchanged substantially, running voltage is remained unchanged substantially
React ITO square resistances also to remain unchanged substantially, i.e., the preparation method of this patent is while thinning ITO thickness, moreover it is possible to base
This maintenance square resistance is constant, that is, while improving the luminosity of chip, do not increase energy consumption, lift chip efficiency.
From comparative example one as can be seen that when oxygen flow is more than 15sccm, chip light emitting brightness only has small elevation, but
The amplitude that running voltage increases is larger；From comparative example two as can be seen that when oxygen flow is less than 5sccm, although running voltage
Reduce, but the amplitude that the luminosity of LED chip reduces becomes big；From comparative example three as can be seen that when vacuum is less than 5 × 10-4
When, relative to example IV, voltage rises and brightness is also greatly reduced；From comparative example four as can be seen that when vacuum more than 1 ×
10-5When, voltage only slightly rises with respect to embodiment two, but the pumpdown time is significantly increased, and is unfavorable for the raising of production efficiency
With a large amount of productions；From comparative example five as can be seen that when temperature is less than 290 DEG C, voltage is substantially increased with respect to embodiment one；From right
Ratio six is as can be seen that when temperature is higher than 310 DEG C, burn-out life is substantially reduced relative to example IV.Therefore, present invention choosing
Take most suitable 5～15sccm of oxygen flow interval, 290～310 DEG C of temperature range, vacuum 5 × 10-4～1 × 10-5With reality
Now improve LED luminance and and do not increase the technique effect of sheet resistance, and do not increase cost, be adapted to a large amount of production.
The preferred embodiments of the present invention are the foregoing is only, the present invention is not limited to, for the skill of this area
For art personnel, the present invention can have various modifications and variations.It is all within the spirit and principles in the present invention, made any repair
Change, equivalent, improvement etc., should be included within the scope of the present invention.
Claims (9)
1. a kind of preparation method of high brightness LED chip, it is characterised in that comprise the following steps：
1) epitaxial layer is made on substrate；
2) on epitaxial layer, evaporation thickness isITO conductive extension layers, the composition of ITO conductive extension layers is indium stannum
Oxide, evaporation condition is：Cavity temperature is maintained at 290～310 DEG C, and 5～15sccm of oxygen flow, chamber vacuum degree are maintained at
5×10-4～1 × 10-5Torr；
3) grain pattern and structure according to required acquisition, unwanted ITO conductive extensions layer is etched away with epitaxial layer；
4) electrode and passivation layer are made；
5) wafer to carrying the LED chip carries out thinning, back of the body plating, sliver, sorting process and obtains crystal grain.
2. the preparation method of a kind of high brightness LED chip according to claim 1, it is characterised in that in step 1 on substrate
The epitaxy layer thickness of making is 3～8 μm.
3. the preparation method of a kind of high brightness LED chip according to claim 1, it is characterised in that using electricity in step 2
Beamlet evaporation equipment is deposited with.
4. the preparation method of a kind of high brightness LED chip according to claim 1, it is characterised in that the substrate is indigo plant
Any one in gem, carborundum, silicon.
5. a kind of preparation method of high brightness LED chip according to claim 1, it is characterised in that the indium stannum oxidation
In thing, indium tin atom quantity ratio is 95：5.
6. the preparation method of a kind of high brightness LED chip according to claim 1, it is characterised in that led by step 3
The step that width is 10～30 μm is etched with electric extension layer and epitaxial layer, the depth of step is 1～2 μm, and in making epitaxial layer
N-type GaN layer expose, step 3 is also etched with ITO conductive extension layers for making the hole of electrode, and hole is by epitaxial layer
The p-type GaN layer of the last layer is exposed, and one, two electrodes of LED chip are produced on step, and another is produced in hole.
7. the preparation method of a kind of high brightness LED chip according to claim 1, it is characterised in that the passivation layer is adopted
With any one in the silicon oxide of insulation transparent, silicon nitride, aluminium oxide.
8. the preparation method of a kind of high brightness LED chip according to claim 7, it is characterised in that the passivation layer
Thickness is
9. the preparation method of a kind of high brightness LED chip according to claim 1, it is characterised in that be deposited with step 2
ITO conductive extension thickness degree is
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| CN106784198A (en) * | 2017-01-26 | 2017-05-31 | 湘能华磊光电股份有限公司 | A kind of preparation method of semiconductor chip |
| CN107706277A (en) * | 2017-09-18 | 2018-02-16 | 厦门三安光电有限公司 | The preparation method and its light emitting diode of a kind of transparency conducting layer |
| CN108063175A (en) * | 2017-12-18 | 2018-05-22 | 佛山市国星半导体技术有限公司 | A kind of high brightness LED chip and preparation method thereof |
| CN109950378A (en) * | 2017-12-20 | 2019-06-28 | 大连德豪光电科技有限公司 | LED chip and preparation method thereof |
| CN114242849A (en) * | 2021-11-25 | 2022-03-25 | 福建兆元光电有限公司 | ITO annealing method for improving LED brightness |
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| CN106784198A (en) * | 2017-01-26 | 2017-05-31 | 湘能华磊光电股份有限公司 | A kind of preparation method of semiconductor chip |
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| CN114242849B (en) * | 2021-11-25 | 2023-06-16 | 福建兆元光电有限公司 | ITO annealing method for improving brightness of LED |
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