CN106548953A - The alignment methods of wafer, system and wafer during wafer sort - Google Patents
The alignment methods of wafer, system and wafer during wafer sort Download PDFInfo
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- CN106548953A CN106548953A CN201510600978.6A CN201510600978A CN106548953A CN 106548953 A CN106548953 A CN 106548953A CN 201510600978 A CN201510600978 A CN 201510600978A CN 106548953 A CN106548953 A CN 106548953A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses the alignment methods of wafer, system and wafer during a kind of wafer sort.Wherein, the method is comprised the following steps：Wafer to be tested is loaded, wherein, wafer to be tested is with the mark array being made up of multiple alignment marks, and the width of multiple alignment marks is different；Test wafer is treated by test device to be scanned；And when any one in multiple alignment marks is scanned, treat test wafer and be aligned.The alignment methods of wafer during wafer sort according to embodiments of the present invention, can reduce impact of the technological fluctuation to wafer alignment, improve the success rate of wafer alignment.
Description
Technical field
The present invention relates to the alignment methods of wafer, system and wafer during a kind of technical field of semiconductors, more particularly to wafer sort.
Background technology
During testing to wafer, for example, Defect Scanning and electrical characteristics test etc. are carried out, often needs to enter wafer
Row positioning and alignment.At present, more common method is that alignment mark is arranged on wafer, by the scanning to alignment mark and
Alignment, realizes the alignment of wafer.
However, can there is incompleteness or fuzzy because of the fluctuation of technique in the alignment mark of wafer.Therefore, by current alignment
Mark is aligned, and frequently results in wafer alignment failure in test, so as to affect the testing efficiency to wafer.
The content of the invention
It is contemplated that at least solving one of technical problem in correlation technique to a certain extent.
For this purpose, it is an object of the present invention to propose a kind of alignment methods of wafer during wafer sort, technique ripple can be reduced
The dynamic impact to wafer alignment, improves the success rate of wafer alignment, so as to improve the testing efficiency of wafer.
Second object of the present invention be propose a kind of wafer sort when wafer to Barebone.
Third object of the present invention is to propose a kind of wafer.
During wafer sort according to embodiments of the present invention, the alignment methods of wafer, comprise the following steps：Wafer to be tested is loaded,
Wherein, the wafer to be tested is with the mark array being made up of multiple alignment marks, and the width of the plurality of alignment mark
It is different；The wafer to be tested is scanned by test device；And work as scanning appointing in the plurality of alignment mark
When one, the wafer to be tested is aligned.
The alignment methods of wafer during wafer sort according to embodiments of the present invention, by multiple width are arranged on wafer to be tested
Different alignment marks, and test wafer can be treated by any one alignment mark for scanning and be aligned.Therefore, when
Indivedual or part in multiple alignment marks is affected by technological fluctuation and causes incompleteness, obscures, or even when etched,
Test wafer can be treated according to the alignment mark not affected by technological fluctuation to be aligned.Thus, technological fluctuation can be greatly reduced
Impact to wafer alignment, improves the success rate of wafer alignment, so as to improve the testing efficiency of wafer.
According to a second aspect of the present invention during the wafer sort of embodiment wafer to Barebone, including：Wafer to be tested, wherein,
The wafer to be tested is with the mark array being made up of multiple alignment marks, and the width of the plurality of alignment mark is different；
Test device, for being scanned to the wafer to be tested, and when any one in the plurality of alignment mark is scanned,
The wafer to be tested is aligned.
During wafer sort according to embodiments of the present invention wafer to Barebone, by multiple width are arranged on wafer to be tested
Different alignment marks, and test wafer can be treated by any one alignment mark for scanning and be aligned.Therefore, when
Indivedual or part in multiple alignment marks is affected by technological fluctuation and causes incompleteness, obscures, or even when etched,
Test wafer can be treated according to the alignment mark not affected by technological fluctuation to be aligned.Thus, technological fluctuation can be greatly reduced
Impact to wafer alignment, improves the success rate of wafer alignment, so as to improve the testing efficiency of wafer.
The wafer of embodiment according to a third aspect of the present invention, it is with the mark array being made up of individual alignment mark more and described many
The width of individual alignment mark is different.
Wafer according to embodiments of the present invention, the alignment mark different due to being provided with multiple width, when in multiple alignment marks
Indivedual or part be subject to technological fluctuation to be affected and cause incompleteness, fuzzy, or even when etched, can be according to not by technique
The alignment mark of influence of fluctuations is aligned to wafer.Thus, impact of the technological fluctuation to wafer alignment can be greatly reduced, is carried
The success rate of high wafer alignment.
The additional aspect and advantage of the present invention will be set forth in part in the description, and partly will become bright from the following description
It is aobvious, or recognized by the practice of the present invention.
Description of the drawings
The flow chart of the alignment methods of wafer when Fig. 1 is the wafer sort according to one embodiment of the invention；
Fig. 2 is the schematic diagram of the mark array according to one embodiment of the invention；And
The structured flowchart to Barebone of wafer when Fig. 3 is the wafer sort according to one embodiment of the invention.
Specific embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein identical from start to finish
Or similar label represents same or similar element or the element with same or like function.Retouch below with reference to accompanying drawing
The embodiment stated is exemplary, it is intended to for explaining the present invention, and be not considered as limiting the invention.
The alignment methods of wafer, system and wafer when describing the wafer sort of the embodiment of the present invention below in conjunction with the accompanying drawings.
The flow chart of the alignment methods of wafer when Fig. 1 is the wafer sort according to one embodiment of the invention.
As shown in figure 1, the alignment methods of wafer are comprised the following steps during the wafer sort of the embodiment of the present invention：
S101, loads wafer to be tested, wherein, wafer to be tested with the mark array being made up of multiple alignment marks, and
The width of multiple alignment marks is different.
In an embodiment of the present invention, wafer to be tested can be the wafer of Silicon Wafer or other materials.
Specifically, multiple alignment marks can be arranged on wafer to be tested using technologies such as photoetching, etchings by light shield, with
Constitute mark array.Wherein, the alignment mark can be located at the front of wafer, may be alternatively located at the back side of wafer.The present invention's
In embodiment, the alignment mark is formed when figure can be formed on wafer simultaneously, it is also possible to independently formed.
In one embodiment of the invention, as the width of multiple alignment marks is different, the mutual area of multiple alignment marks can be made
Point, such that it is able to be applied to different techniques.The width available pixel of generally multiple alignment marks is represented.The one of the present invention
In individual embodiment, the minimum widith of alignment mark can be 10-30 pixels.Certainly those skilled in the art will appreciate that
For different technique, the minimum widith of the alignment mark is also respective change.
In one embodiment of the invention, the shape all same of multiple alignment marks, meanwhile, the arrangement of multiple alignment marks
Direction can be different.Wherein, the shape all same of multiple alignment marks, refers to that an alignment mark can be arbitrary to fiducial mark by other
Note is passed through and is zoomed in or out, then is obtained through rotation and translation.In a particular embodiment of the present invention, multiple alignment marks
Shape can be " L " shape, " one " shape, " ︱ " shape or "+" shape.Certainly in other embodiments of the invention, alignment mark also may be used
To select other shapes, generally there is the figure of " " and " ︱ " in the alignment mark.
Certainly in other embodiments of the invention, the shape of multiple alignment marks can be differed, or part phase
Together, part is different, and these are should be included within the protection domain of our inventive embodiments.
In one embodiment of the present of invention, it is preferred to use the alignment mark of " L " shape, each can not only be better ensured that to fiducial mark
The uniqueness of note, and being capable of save space.As shown in Fig. 2 being showing for the mark array according to one embodiment of the invention
It is intended to.Include the mark array being made up of 4 alignment marks for being all " L " shape, the alignment of this 4 " L " shapes in fig. 2
Mark width is different, and orientation is different.It should be appreciated that due in an embodiment of the present invention, to fiducial mark
The shape of note be combine various factors after the optimal selection made, therefore, the shape of multiple alignment marks adopts " L " shape,
Can ensure that the shape of each alignment mark is optimal.
S102, treats test wafer by test device and is scanned.
Wherein, test device can have image scanner, and the alignment of wafer to be tested can be scanned by image scanner
Mark and be aligned.
S103, when any one in multiple alignment marks is scanned, treats test wafer and is aligned.
The graphical information of multiple alignment marks of wafer to be tested, such as shape of multiple alignment marks can be prestored in scanning device
The information such as shape, width, GTG, orientation and position.In one embodiment of the invention, test wafer can be treated to enter
Row scanning, and the alignment mark for scanning is compared with the alignment mark for prestoring.If consistent, test wafer is treated
It is aligned.
It should be appreciated that the multiple alignment marks in due to mark array mutually can be distinguished, and crystalline substance is disclosure satisfy that in shape
Justify the requirement of alignment, therefore test wafer can be treated according to the alignment mark of any one in mark array and be aligned.At this
In one embodiment of invention, in optional multiple alignment marks, an alignment mark set in advance treats test wafer is carried out
Alignment.Specifically, when the alignment mark set in advance for scanning graphical information and the alignment mark for prestoring figure
When information is identical, test wafer can be treated according to the alignment mark set in advance for scanning and be aligned.When because not sweeping
When retouching an alignment mark set in advance and being aligned unsuccessfully, other alignment marks can be scanned, and according to other alignment marks
Treat test wafer to be aligned.It should be appreciated that after according to an alignment mark set in advance failure, to other
The scanning of alignment mark can be carried out by the order of setting, until being aligned successfully.
For example, wafer to be tested has the mark array shown in Fig. 2, and the mark array includes alignment mark a-d.Its
In, as shown in Fig. 2 the width of the minimum alignment mark a of width is 20 pixels.When being aligned to the wafer to be tested,
Alignment mark a can be preselected, if alignment mark a has been arrived in scanning in scanning process, can be according to the scanned alignment for arriving
Mark a is aligned to the wafer to be tested.If alignment mark a because of the impact of processing quality with the alignment mark a for prestoring
When different, alignment mark b, c and d can be continued to scan on, until the wafer alignment success to be tested.Thus, of the invention real
Apply in example, when indivedual in multiple alignment marks or partially due to technological fluctuation and the problems such as cause figure fracture, obscurity boundary
When, can be aligned according to other alignment marks.
Additionally, in a preferred embodiment of the invention, to become apparent from alignment mark and the comparison of light and shade in other regions,
May be selected to arrange alignment mark in the higher film layer of the brightness such as polysilicon or metal.It is etched away due to polysilicon or metal
Regional luminance is relatively low, and the marked region brightness for staying is higher such that it is able to light and shade contrast's high requirement when meeting alignment.
The alignment methods of wafer during wafer sort according to embodiments of the present invention, by multiple width are arranged on wafer to be tested
Different alignment marks, and test wafer can be treated by any one alignment mark for scanning and be aligned.Therefore, when
Indivedual or part in multiple alignment marks is affected by technological fluctuation and causes incompleteness, obscures, or even when etched,
Test wafer can be treated according to the alignment mark not affected by technological fluctuation to be aligned.Thus, technological fluctuation can be greatly reduced
Impact to wafer alignment, improves the success rate of wafer alignment, so as to improve the testing efficiency of wafer.
To realize the alignment methods of wafer during the wafer sort of above-described embodiment, the present invention also proposes wafer during a kind of wafer sort
To Barebone.
The structured flowchart to Barebone of wafer when Fig. 3 is the wafer sort according to one embodiment of the invention.
As shown in figure 3, during the wafer sort of the embodiment of the present invention wafer to Barebone, including：Wafer to be tested 10 and survey
Trial assembly puts 20.
Wherein, wafer to be tested 10 is with the mark array being made up of multiple alignment marks, and the width of multiple alignment marks is not
Together.Test device 20 is scanned for treating test wafer, and when any one in multiple alignment marks is scanned, it is right
Wafer to be tested is aligned.
In an embodiment of the present invention, wafer to be tested 10 can be the wafer of Silicon Wafer or other materials.
Specifically, multiple alignment marks can be arranged on wafer to be tested 10 using technologies such as photoetching, etchings by light shield,
To constitute mark array.Wherein, the alignment mark can be located at the front of wafer, may be alternatively located at the back side of wafer.In the present invention
Embodiment in, formed when the alignment mark can form figure on wafer simultaneously, it is also possible to independently form.
In one embodiment of the invention, as the width of multiple alignment marks is different, the mutual area of multiple alignment marks can be made
Point, such that it is able to be applied to different techniques.The width available pixel of generally multiple alignment marks is represented.The one of the present invention
In individual embodiment, the minimum widith of alignment mark can be 10-30 pixels.Certainly those skilled in the art will appreciate that
For different technique, the minimum widith of the alignment mark is also respective change.
In one embodiment of the invention, the shape all same of multiple alignment marks, meanwhile, the arrangement of multiple alignment marks
Direction can be different.Wherein, the shape all same of multiple alignment marks, refers to that an alignment mark can be arbitrary to fiducial mark by other
Note is passed through and is zoomed in or out, then is obtained through rotation and translation.In a particular embodiment of the present invention, multiple alignment marks
Shape can be " L " shape, " one " shape, " ︱ " shape or "+" shape.Certainly in other embodiments of the invention, alignment mark also may be used
To select other shapes, generally there is the figure of " " and " ︱ " in the alignment mark.
Certainly in other embodiments of the invention, the shape of multiple alignment marks can be differed, or part phase
Together, part is different, and these are should be included within the protection domain of our inventive embodiments.
In one embodiment of the present of invention, it is preferred to use the alignment mark of " L " shape, each can not only be better ensured that to fiducial mark
The uniqueness of note, and being capable of save space.As shown in Fig. 2 being showing for the mark array according to one embodiment of the invention
It is intended to.Include the mark array being made up of 4 alignment marks for being all " L " shape, the alignment of this 4 " L " shapes in fig. 2
Mark width is different, and orientation is different.It should be appreciated that due in an embodiment of the present invention, to fiducial mark
The shape of note be combine various factors after the optimal selection made, therefore, the shape of multiple alignment marks adopts " L " shape,
Can ensure that the shape of each alignment mark is optimal.
Test device 20 can have image scanner, and the alignment mark of wafer to be tested can be scanned by image scanner
And be aligned.Wherein, the graphical information of multiple alignment marks of wafer to be tested 10 can be prestored in scanning device, for example
The information such as the shape of multiple alignment marks, width, GTG, orientation and position.In one embodiment of the invention,
Test wafer 10 can be treated to be scanned, and the alignment mark for scanning is compared with the alignment mark for prestoring.If one
Cause, then treat test wafer and be aligned.
It should be appreciated that the multiple alignment marks in due to mark array mutually can be distinguished, and crystalline substance is disclosure satisfy that in shape
Justify the requirement of alignment, therefore test wafer 10 can be treated according to the alignment mark of any one in mark array and be aligned.
In one embodiment of the present of invention, during multiple alignment marks may be selected, an alignment mark set in advance treats test wafer 10
It is aligned.Specifically, when the graphical information and the alignment mark for prestoring of the alignment mark set in advance for scanning
When graphical information is identical, test wafer 10 can be treated according to the alignment mark set in advance for scanning and be aligned.When
When being aligned unsuccessfully because not scanning an alignment mark set in advance, other alignment marks can be scanned, and it is right according to other
Fiducial mark note is treated test wafer 10 and is aligned.It should be appreciated that after according to an alignment mark set in advance failure,
Scanning to other alignment marks can be carried out by the order of setting, until being aligned successfully.
For example, with the mark array shown in Fig. 2, the mark array includes alignment mark a-d to wafer to be tested 10.
Wherein, as shown in Fig. 2 the width of the minimum alignment mark a of width is 20 pixels.The wafer to be tested is being aligned
When, alignment mark a can be preselected, if alignment mark a has been arrived in scanning in scanning process, can be arrived according to scan
Alignment mark a is aligned to the wafer to be tested 10.If alignment mark a is right with what is prestored because of the impact of processing quality
When fiducial mark note a is different, alignment mark b, c and d can be continued to scan on, until the wafer alignment success to be tested.Thus, exist
In the embodiment of the present invention, when indivedual in multiple alignment marks or partially due to technological fluctuation and cause figure fracture, module of boundary
During the problems such as paste, can be aligned according to other alignment marks.
Additionally, in a preferred embodiment of the invention, to become apparent from alignment mark and the comparison of light and shade in other regions,
May be selected to arrange alignment mark in the higher film layer of the brightness such as polysilicon or metal.It is etched away due to polysilicon or metal
Regional luminance is relatively low, and the marked region brightness for staying is higher such that it is able to light and shade contrast's high requirement when meeting alignment.
During wafer sort according to embodiments of the present invention wafer to Barebone, by multiple width are arranged on wafer to be tested
Different alignment marks, and test wafer can be treated by any one alignment mark for scanning and be aligned.Therefore, when
Indivedual or part in multiple alignment marks is affected by technological fluctuation and causes incompleteness, obscures, or even when etched,
Test wafer can be treated according to the alignment mark not affected by technological fluctuation to be aligned.Thus, technological fluctuation can be greatly reduced
Impact to wafer alignment, improves the success rate of wafer alignment, so as to improve the testing efficiency of wafer.
The alignment methods and system of wafer during the wafer sort of correspondence above-described embodiment, the present invention also propose a kind of wafer.
The wafer of the embodiment of the present invention, with the mark array being made up of multiple alignment marks, and the width of multiple alignment marks
It is different.
In an embodiment of the present invention, wafer to be tested can be the wafer of Silicon Wafer or other materials.
Specifically, multiple alignment marks can be arranged using technologies such as photoetching, etchings, on wafer to constitute mark by light shield
Note array.In an embodiment of the present invention, formed when the alignment mark can form figure on wafer simultaneously, also may be used
To independently form.
In one embodiment of the invention, as the width of multiple alignment marks is different, the mutual area of multiple alignment marks can be made
Point, such that it is able to be applied to different techniques.The width available pixel of generally multiple alignment marks is represented.The one of the present invention
In individual embodiment, the minimum widith of alignment mark can be 10-30 pixels.Certainly those skilled in the art will appreciate that
For different technique, the minimum widith of the alignment mark is also respective change.
In one embodiment of the invention, the shape all same of multiple alignment marks, meanwhile, the arrangement of multiple alignment marks
Direction can be different.Wherein, the shape all same of multiple alignment marks, refers to that an alignment mark can be arbitrary to fiducial mark by other
Note is passed through and is zoomed in or out, then is obtained through rotation and translation.In a particular embodiment of the present invention, multiple alignment marks
Shape can be " L " shape, " one " shape, " ︱ " shape or "+" shape.Certainly in other embodiments of the invention, alignment mark also may be used
To select other shapes, generally there is the figure of " " and " ︱ " in the alignment mark.
Certainly in other embodiments of the invention, the shape of multiple alignment marks can be differed, or part phase
Together, part is different, and these are should be included within the protection domain of our inventive embodiments.
In one embodiment of the present of invention, it is preferred to use the alignment mark of " L " shape, each can not only be better ensured that to fiducial mark
The uniqueness of note, and being capable of save space.With reference to Fig. 2, can be by the constituted mark battle array of 4 alignment marks for being all " L " shape
Row, the alignment mark width of this 4 " L " shapes is different, and orientation is different.It should be appreciated that due at this
In inventive embodiment, the shape of alignment mark be combine various factors after the optimal selection made, therefore, multiple alignments
The shape of mark adopts " L " shape, it is ensured that the shape of each alignment mark is optimal.
Wafer according to embodiments of the present invention, the alignment mark different due to being provided with multiple width, when in multiple alignment marks
Indivedual or part be subject to technological fluctuation to be affected and cause incompleteness, fuzzy, or even when etched, can be according to not by technique
The alignment mark of influence of fluctuations is aligned to wafer.Thus, impact of the technological fluctuation to wafer alignment can be greatly reduced, is carried
The success rate of high wafer alignment.
In describing the invention, it is to be understood that term " " center ", " longitudinal direction ", " horizontal ", " length ", " width ",
" thickness ", " on ", D score, "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outward ",
The orientation or position relationship of the instruction such as " clockwise ", " counterclockwise ", " axial direction ", " radial direction ", " circumference " is based on shown in the drawings
Orientation or position relationship, be for only for ease of description the present invention and simplify description, rather than indicate or imply indication device or
Element with specific orientation, with specific azimuth configuration and operation, therefore must be not considered as limiting the invention.
Additionally, term " first ", " second " be only used for describe purpose, and it is not intended that indicate or imply relative importance or
The implicit quantity for indicating indicated technical characteristic.Thus, define " first ", the feature of " second " can be expressed or hidden
Include at least one this feature containing ground.In describing the invention, " multiple " are meant that at least two, such as two, three
It is individual etc., unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the art such as term " installation ", " being connected ", " connection ", " fixation "
Language should be interpreted broadly, for example, it may be fixedly connected, or be detachably connected, or it is integral；Can be machinery
Connection, or electrical connection；Can be joined directly together, it is also possible to be indirectly connected to by intermediary, can be two units
The interaction relationship of connection or two elements inside part, unless otherwise clearly restriction.For the ordinary skill of this area
For personnel, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature " on " or D score can be
First and second feature directly contacts, or the first and second features are by intermediary mediate contact.And, first is special
Levy second feature " on ", " top " and " above " but fisrt feature directly over second feature or oblique upper, or only
Only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " lower section " and " below "
Can be fisrt feature immediately below second feature or obliquely downward, or be merely representative of fisrt feature level height less than second
Feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specific example ",
Or the description of " some examples " etc. means the specific features, structure, material or the feature bag that describe with reference to the embodiment or example
It is contained at least one embodiment or example of the present invention.In this manual, to the schematic representation of above-mentioned term necessarily
It is directed to identical embodiment or example.And, the specific features of description, structure, material or feature can be arbitrary
Combined in individual or multiple embodiments or example in an appropriate manner.Additionally, in the case of not conflicting, the skill of this area
The feature of the different embodiments or example described in this specification and different embodiments or example can be combined by art personnel
And combination.
Although embodiments of the invention have been shown and described above, it is to be understood that above-described embodiment be it is exemplary,
It is not considered as limiting the invention, one of ordinary skill in the art within the scope of the invention can be to above-described embodiment
It is changed, changes, replacing and modification.
Claims (9)
1. during a kind of wafer sort wafer alignment methods, it is characterised in that comprise the following steps：
Wafer to be tested is loaded, wherein, the wafer to be tested is with the mark array being made up of multiple alignment marks, and institute
The width for stating multiple alignment marks is different；
The wafer to be tested is scanned by test device；And
When any one in the plurality of alignment mark is scanned, the wafer to be tested is aligned.
2. during wafer sort as claimed in claim 1 wafer alignment methods, it is characterised in that the plurality of alignment mark
Orientation it is different.
3. during wafer sort as claimed in claim 1 wafer alignment methods, it is characterised in that the plurality of alignment mark
Be shaped as " L " shape, " one " shape, " ︱ " shape or "+" shape, and the shape all same of the plurality of alignment mark.
4. during a kind of wafer sort wafer to Barebone, it is characterised in that include：
Wafer to be tested, wherein, the wafer to be tested is with the mark array being made up of multiple alignment marks and described many
The width of individual alignment mark is different；
Test device, for being scanned to the wafer to be tested, and when scanning is arbitrary in the plurality of alignment mark
When individual, the wafer to be tested is aligned.
5. during wafer sort as claimed in claim 4 wafer to Barebone, it is characterised in that the plurality of alignment mark
Orientation it is different.
6. during wafer sort as claimed in claim 4 wafer to Barebone, it is characterised in that the plurality of alignment mark
Be shaped as " L " shape, " one " shape, " ︱ " shape or "+" shape, and the shape all same of the plurality of alignment mark.
7. a kind of wafer, it is characterised in that with the mark array being made up of multiple alignment marks, and it is the plurality of to fiducial mark
The width of note is different.
8. wafer as claimed in claim 7, it is characterised in that the orientation of the plurality of alignment mark is different.
9. wafer as claimed in claim 7, it is characterised in that the plurality of alignment mark is shaped as " L " shape, " "
Shape, " ︱ " shape or "+" shape, and the shape all same of the plurality of alignment mark.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510600978.6A CN106548953A (en) | 2015-09-18 | 2015-09-18 | The alignment methods of wafer, system and wafer during wafer sort |
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| CN201510600978.6A CN106548953A (en) | 2015-09-18 | 2015-09-18 | The alignment methods of wafer, system and wafer during wafer sort |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085545A (en) * | 2019-03-26 | 2019-08-02 | 上海华力微电子有限公司 | A kind of auxiliary alignment methods and system |
| CN113611650A (en) * | 2021-03-19 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Method for aligning wafer pattern |
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| CN110085545A (en) * | 2019-03-26 | 2019-08-02 | 上海华力微电子有限公司 | A kind of auxiliary alignment methods and system |
| CN110085545B (en) * | 2019-03-26 | 2021-07-23 | 上海华力微电子有限公司 | Auxiliary alignment method and system |
| CN113611650A (en) * | 2021-03-19 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Method for aligning wafer pattern |
| US11692946B2 (en) | 2021-03-19 | 2023-07-04 | United Semiconductor (Xiamen) Co., Ltd. | Method for aligning to a pattern on a wafer |
| CN113611650B (en) * | 2021-03-19 | 2024-02-27 | 联芯集成电路制造(厦门)有限公司 | Method for aligning wafer pattern |
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