CN106547937A - A kind of Digital Signal Processing dsp software checking system and method - Google Patents
A kind of Digital Signal Processing dsp software checking system and method Download PDFInfo
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- CN106547937A CN106547937A CN201510611543.1A CN201510611543A CN106547937A CN 106547937 A CN106547937 A CN 106547937A CN 201510611543 A CN201510611543 A CN 201510611543A CN 106547937 A CN106547937 A CN 106547937A
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Abstract
The present invention provides a kind of dsp software checking system and method, and the system includes：FPGA/CPLD, by the peripheral circuit of software emulation DSP veneers；Random access memory ram；DSP veneers, are connected with the RAM, for running dsp software and exporting operation result to verify whether dsp software is correct；In the DSP veneers operation dsp software running, the data is activation of peripheral circuit will be sent to the RAM, need to read from the RAM when reading data from peripheral circuit, peripheral circuits of the FPGA/CPLD by software emulation, the data that dsp software sends are read from RAM, need to be sent in RAM when data are sent to dsp software.The present invention is verified without the need for the expensive checking system of extra hardware cost and outsourcing, the Realization of Simulation dsp software accomplished closest to real system.
Description
Technical field
The present invention relates to software detection technical field, more particularly to a kind of Digital Signal Processing dsp software is tested
Card system and method.
Background technology
DSP (Digital Signal Processing, Digital Signal Processing) veneer is connected with peripheral circuit,
Dsp software is run on DSP veneers, various functions is realized by interacting with peripheral circuit.
In order to verify whether the dsp software run on DSP veneers is problematic, traditional dsp software (HIL,
Hardware-in-the-loop) proof scheme has two kinds：
1) Matlab softwares+emulator+DSP veneer modes
As shown in figure 1, Matlab softwares are run on PC, in Matlab softwares, have corresponding DSP's
Interface model, as the interface on PC cannot be with DSP veneer direction communications, therefore the interface model is negative
Duty carries out data exchange by emulator and DSP veneers, builds checking circuit (i.e. in Matlab softwares
The actual peripheral circuit with DSP single board communications), dsp software, DSP veneers are run on DSP veneers
By emulator and the checking circuit communication built, by the ruuning situation of dsp software, to dsp software
Verified.
Emulator can be JTAG (Joint Test Action Group, joint test working group) emulator.
The advantage of this method is that hardware only needs to DSP veneers and emulator, is easier to meet, and
The existing abundant model of Matlab softwares can easily build checking circuit, meet the checking of complex working condition.
But the data interaction between Matlab softwares and DSP veneers is the bottleneck of this verification mode, this data
Interactive mode causes emulator constantly to intervene the normal operation of dsp software, and simulation time is significantly longer than software
In logical time.
2) using system real-time simulation platform software kit RT_LAB or dSPACE system
RT_LAB or dSPACE systems be can bi-directional verification semi-physical emulation platform, such as Fig. 2 a institutes
Show, it is possible to use RT_LAB or dSPACE system simulation control objects, i.e., using RT_LAB or
The peripheral circuit of dSPACE system emulation DSP veneers, and dsp interface test system building, in DSP
Dsp software is run on veneer, in software running process, by with RT_LAB or dSPACE systems
Whether the peripheral circuit authentication dsp software of emulation is problematic.
As shown in Figure 2 b, it is also possible to allow RT_LAB or dSPACE system operation control softwares, that is, allow
RT_LAB or dSPACE systems emulate dsp software, with actual control object (DSP veneers periphery electricity
Road) test system building, in software running process, the DSP of RT_LAB or dSPACE system emulations
Whether software is problematic with peripheral circuit authentication dsp software.
The interface of RT_LAB or dSPACE systems be multi-channel high-speed digital interface can with flexible configuration, but
Building the analogue system needs very big workload, and expensive.
The content of the invention
The present invention provides a kind of dsp software checking system and method, without the need for extra hardware cost and outsourcing
Expensive checking system, the Realization of Simulation dsp software accomplished closest to real system are verified.
The present invention provides a kind of dsp software checking system, including：
On-site programmable gate array FPGA/complex programmable logic device (CPLD), by software emulation DSP
The peripheral circuit of veneer；
Random access memory ram；
DSP veneers, are connected with the RAM, for running dsp software and exporting operation result to verify
Whether dsp software is correct；
In the DSP veneers operation dsp software running, the data is activation of peripheral circuit will be sent to
To the RAM, need to read from the RAM when reading data from peripheral circuit, it is described
Peripheral circuits of the FPGA/CPLD by software emulation, reads the data that dsp software sends from RAM,
Need to be sent in RAM when sending data to dsp software.
Preferably, the peripheral circuit of DSP veneers of the FPGA/CPLD by software emulation includes as follows
Arbitrary or any number of circuits：
Signal sample circuit, signal deteching circuit, Switching Converter Topologies, passive filter circuit.
Preferably, inside external expansion interface and FPGA of the DSP veneers by DSP veneers
RAM/CPLD additional RAM connections.
Preferably, using the Fabric Interface XTINF modules of DSP realizing the outside of RAM connection
Expansion interface.
Preferably, TMS320F2823x DSP veneer of the DSP veneers using TI, the FPGA
Using the cyclone IV 4CE6FPGA of Altera.
Preferably, the system also includes：
Verification management module, for configuring the outer of DSP veneers of the FPGA/CPLD by software emulation
Circuit is enclosed, the dsp software operation result of DSP veneers output is received and record, according to the operation result
Whether checking dsp software is correct.
The present invention also provides a kind of Digital Signal Processing dsp software verification method, including：
By the software emulation on on-site programmable gate array FPGA/complex programmable logic device (CPLD)
The peripheral circuit of DSP veneers；
Dsp software is run on DSP veneers and operation result is exported to verify whether dsp software is correct,
In dsp software running, the data is activation of peripheral circuit will be sent to RAM, needed from peripheral electricity
Road is read when reading data from the RAM, periphery electricity of the FPGA/CPLD by software emulation
Road, reads the data that dsp software sends from RAM, needs to send when sending data to dsp software
To in RAM.
Preferably, it is by the peripheral circuit of the software emulation DSP veneers on FPGA/CPLD, concrete to wrap
Include：
The peripheral circuit that Hardware Description Language VHDL source code emulates DSP veneers is configured manually；
Or
By configuring Matlab softwares, by Matlab generate VHDL compilation of source code and download to FPGA/
On CPLD, the peripheral circuit of DSP veneers is emulated.
Preferably, the peripheral circuit of DSP veneers of the FPGA/CPLD by software emulation includes：
Signal sample circuit, signal deteching circuit, Switching Converter Topologies, LC filter circuits.
Preferably, the method also includes：
The dsp software operation result of DSP veneers output is received and recorded, is verified according to the operation result
Whether dsp software is correct.
The dsp software checking system provided using the present invention and method, are had the advantages that：
1) scheme of the invention directly can control veneer using ready-made DSP+FPGA/CPLD is minimum,
Without the need for the expensive checking system of extra hardware cost and outsourcing, for the only control system of DSP, adopt
Same effect can be reached with the mode for increasing by one piece of FPGA motherboards/CPLD；
2) DSP target softwares, the acquisition when being verified, only to peripheral circuit analog quantity are directly run
Address is altered, and other are not changed, and accomplishes the emulation closest to real system.
Description of the drawings
Fig. 1 is the dsp software checking system schematic diagram in prior art using scheme one；
Fig. 2 a are a kind of dsp software checking system schematic diagram of existing middle employing scheme two；
The existing middle another kind of dsp software checking system schematic diagrames for adopting scheme two of Fig. 2 b for；
The dsp software checking system schematic diagram that Fig. 3 is provided for the present invention；
The dsp software checking system schematic diagram that Fig. 4 is provided for specific embodiment of the present invention；
Fig. 5 illustrates for the dsp software checking system with management function that specific embodiment of the present invention is provided
Figure；
The dsp software verification method flow chart that Fig. 6 is provided for the present invention.
Specific embodiment
A kind of dsp software checking system and method for providing to the present invention with reference to the accompanying drawings and examples is entered
Row is illustrated in greater detail.
The present invention provides a kind of dsp software checking system, as shown in figure 3, including：
On-site programmable gate array FPGA/complex programmable logic device (CPLD), by software emulation DSP
The peripheral circuit of veneer；
Random access memory ram；
DSP veneers, are connected with the RAM, for running dsp software and exporting operation result to verify
Whether dsp software is correct；
In the DSP veneers operation dsp software running, the data is activation of peripheral circuit will be sent to
To the RAM, need to read from the RAM when reading data from peripheral circuit, it is described
Peripheral circuits of the FPGA/CPLD by software emulation, reads the data that dsp software sends from RAM,
Need to be sent in RAM when sending data to dsp software.
FPGA/CPLD, it is the product further developed on the basis of the programming devices such as PAL, GAL
Thing.It is as special IC (ASIC) field in a kind of semi-custom circuit and occur, both solved
Determine the deficiency of custom circuit, overcome the limited shortcoming of original programming device gate circuit number again.
The circuit design completed with hardware description language, can be through simple synthesis and layout, quickly
It is burned onto on FPGA/CPLD and is tested.
The embodiment of the present invention make use of this feature of FPGA/CPLD, design DSP with hardware description language
The peripheral circuit of veneer, is burned onto on FPGA/CPLD, so as to realize on FPGA/CPLD by soft
Part emulates the peripheral circuit of DSP veneers.
Specifically, Hardware Description Language VHDL source code emulation DSP veneers can manually be configured
Peripheral circuit.
Or, by configuring Matlab softwares, by Matlab generate VHDL compilation of source code and download
To on FPGA/CPLD, the peripheral circuit of DSP veneers is emulated.
Peripheral circuit as DSP veneers are emulated using FPGA/CPLD, is directly transported on DSP veneers
Row DSP target softwares, when being verified, for dsp software, only to peripheral circuit analog quantity
Acquisition address be altered, i.e., from original substantial periphery circuit obtain analog signalses be changed to RAM
In, other are not changed, and accomplish the emulation closest to real system；In addition, by the use of RAM as data
The communal space, the data of FPGA/CPLD and DSP single plate interactives are stored in RAM, DSP veneers
The data interactive mode of this employing shared drive can greatly improve system and FPGA/CPLD between
Simulation performance.
If adopting FPGA, the RAM carried inside FPGA can be adopted, it would however also be possible to employ FPGA
Additional RAM, during using CPLD, needs using additional RAM.
Current somewhat more complex DSP control system typically can place a piece of in DSP veneers periphery
FPGA/CPLD does the functions such as resource expansion, high-speed communication and secrecy.In this case, the present invention is real
Apply example can directly using the minimum control veneer of ready-made DSP+FPGA/CPLD, without the need for extra hardware into
This checking system expensive with outsourcing.In addition, DSP control system does not have FPGA/CPLD and only has immediately
DSP veneers realize that the embodiment of the present invention can increase by one piece on the basis of former DSP veneers
FPGA/CPLD motherboards, it is also possible to reach same simulated effect.
Preferably, the peripheral circuit of DSP veneer of embodiment of the present invention FPGA/CPLD by software emulation
Including following arbitrary or any number of circuits：
Signal sample circuit, signal deteching circuit, Switching Converter Topologies, passive filter circuit.
Certainly, the peripheral circuit not limited to this for being emulated using FPGA/CPLD, can also realize DSP
The circuit of other any functions of veneer periphery.
Preferably, DSP veneers are connected with RAM by the external expansion interface of DSP veneers.
It is further preferred that can be realized using XTINF (External Interface) modules of DSP
The external expansion interface of RAM connections.
For the DSP control system that a piece of FPGA/CPLD realizations can be placed in DSP veneers periphery, DSP
The analog-to-digital conversion module (A/D module) of veneer is connected to actual peripheral circuit by interface 1, and pulse
Width modulated PWM, input and output IO etc. are connected to FPGA/CPLD by interface 2 and realize some data
Communication.
For the embodiment of the present invention, the analog-to-digital conversion module (A/D module) of DSP veneers is by interface
1 is connected to RAM, and whole dsp software is run through on DSP veneers, when HIL Validation Modes are set to,
The data change of the analog quantity sampling that A/D module reads is to read (by Fig. 3 from shared section key RAM
In interface 1), other data-interfaces it is constant (as schemed, interface 1 and 2), i.e. pulse width modulation (PWM),
The signal of the interfaces such as input and output IO 2 is still normally used.Interface 1 is except simulation number during emulation in addition
It is outer according to interaction, the such as task such as communication data, protection information interaction will be also undertaken when normal system works.
Preferably, there is on the DSP veneers of the embodiment of the present invention observation interface, DSP veneers are soft by DSP
The result output of part operation, is recorded the output under measurement condition, judges DSP by the observation interface of DSP
Whether software is correct.
Preferably, the system also includes：
Verification management module, for configuring the outer of DSP veneers of the FPGA/CPLD by software emulation
Circuit is enclosed, the dsp software operation result of DSP veneers output is received and record, according to the operation result
Whether checking dsp software is correct.
The peripheral circuit of DSP veneers of the verification management module configuration FPGA/CPLD by software emulation,
Can be specifically that periphery circuit design is completed with hardware description language, specifically can manually configure hardware and retouch
Predicate says VHDL source codes, and then just VHDL source codes are quickly burned onto on FPGA；Or,
By configuring Matlab softwares.If configuration Matlab softwares, the then VHDL for generating Matlab afterwards
Compilation of source code is simultaneously downloaded on FPGA/CPLD, emulates the peripheral circuit of DSP veneers.
The preferred embodiment of dsp software checking system of the present invention is given below.
Embodiment
As shown in figure 4, DSP veneers are mono- using the TMS320F2823x DSP of TI in the embodiment of the present invention
Plate, cyclone IV 4CE6FPGAs of the FPGA using Altera.It is, of course, also possible to adopt other models
DSP veneers and FPGA.
DSP veneers are connected to the internal RAM space of FPGA with its external expansion interface (interface 1),
Specifically interface 1 can be realized using the XTINF modules of DSP, the ram space is configured for shared drive
Area, for storing data interactive at a high speed between DSP and FPGA.
The embodiment of the present invention as the outer extension memory of DSP, is assigned the RAM in FPGA special
Storage space, in addition to analogue data of the interface 1 when emulation is interacted, also will when normal system works
Undertake the such as task such as communication data, protection information interaction.And the signal of the interface such as PWM, IO 2 is still just
Often use.
Peripheral circuits of the FPGA by software emulation DSP veneers, runs through whole DSP on DSP veneers
Software, when HIL Validation Modes are set to, DSP veneers will be sent to the data is activation of peripheral circuit to institute
RAM being stated, needing to read from the RAM when data are read from peripheral circuit, FPGA is imitative by software
Genuine peripheral circuit, reads the data that dsp software sends from RAM, needs to dsp software to send
It is sent in RAM during data.
The emulation of system can be greatly improved between DSP and FPGA using the data interactive mode of shared drive
Performance, but as the deformation of the present invention, however not excluded that other data interactions are adopted between DSP and FPGA
Mode, such as serial peripheral equipment interface SPI communication etc..
The embodiment of the present invention directly runs DSP file destinations on DSP veneers, under Validation Mode, only
The acquisition address of analog quantity is altered, i.e., be changed to from RAM by obtaining from actual peripheral circuit originally
Obtain, other are not changed, and accomplish the emulation closest to real system.
Preferably, the dsp software checking system in the embodiment of the present invention also includes：
Verification management module, for configuring the periphery electricity of DSP veneers of the FPGA by software emulation
Road, receives and records the dsp software operation result of DSP veneers output, is verified according to the operation result
Whether dsp software is correct.
As shown in figure 5, verification management module mainly realizes two functions, one is that measurement result is received and recorded
According to operation result, dsp software operation result, verifies whether dsp software is correct, and one is test case pipe
Reason, can configure different DSP veneer peripheral circuits, as needed such that it is able to realize dsp software
Automatic Verification.
According to another embodiment of the present invention, there is provided a kind of Digital Signal Processing dsp software verification method, such as
Shown in Fig. 6, including：
Step 601, by on-site programmable gate array FPGA/complex programmable logic device (CPLD)
The peripheral circuit of software emulation DSP veneers；
Step 602, runs dsp software on DSP veneers and exports operation result to verify dsp software
It is whether correct, in dsp software running, the data is activation of peripheral circuit will be sent to RAM, needed
Read from RAM when reading data from peripheral circuit, the FPGA/CPLD is by software emulation
Peripheral circuit, reads the data that dsp software sends from RAM, needs to send data to dsp software
When be sent in RAM.
Dsp software verification method provided in an embodiment of the present invention, when being verified, for dsp software
For, only the acquisition address of peripheral circuit analog quantity is altered, i.e., is obtained from original substantial periphery circuit
Take analog signalses to be changed in RAM, other are not changed, accomplish the emulation closest to real system；
In addition, by the use of RAM as data sharing space, the data of FPGA/CPLD and DSP single plate interactives are all
It is stored in RAM, the data interaction of this employing shared drive between DSP veneers and FPGA/CPLD
Mode can greatly improve the simulation performance of system.
Preferably, by the peripheral circuit of the software emulation DSP veneers on FPGA/CPLD, specifically include：
The peripheral circuit that Hardware Description Language VHDL source code emulates DSP veneers is configured manually；
Or
By configuring Matlab softwares, by Matlab generate VHDL compilation of source code and download to FPGA/
On CPLD, the peripheral circuit of DSP veneers is emulated.
Preferably, the peripheral circuit of DSP veneers of the FPGA/CPLD by software emulation includes：
Signal sample circuit, signal deteching circuit, Switching Converter Topologies, LC filter circuits.
Preferably, the method also includes：
Step 603, receives and records the dsp software operation result of DSP veneers output, according to the fortune
Whether row result verification dsp software is correct.
Obviously, those skilled in the art can carry out various changes and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these modification and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of Digital Signal Processing dsp software checking system, it is characterised in that include：
On-site programmable gate array FPGA/complex programmable logic device (CPLD), by software emulation DSP
The peripheral circuit of veneer；
Random access memory ram；
DSP veneers, are connected with the RAM, for running dsp software and exporting operation result to verify
Whether dsp software is correct；
In the DSP veneers operation dsp software running, the data is activation of peripheral circuit will be sent to
To the RAM, need to read from the RAM when reading data from peripheral circuit, it is described
Peripheral circuits of the FPGA/CPLD by software emulation, reads the data that dsp software sends from RAM,
Need to be sent in RAM when sending data to dsp software.
2. the system as claimed in claim 1, it is characterised in that the FPGA/CPLD passes through software
The peripheral circuit of the DSP veneers of emulation includes following arbitrary or any number of circuits：
Signal sample circuit, signal deteching circuit, Switching Converter Topologies, passive filter circuit.
3. the system as claimed in claim 1, it is characterised in that the DSP veneers pass through DSP veneers
The external expansion interface RAM additional with the RAM/CPLD inside FPGA be connected.
4. system as claimed in claim 3, it is characterised in that
The external expansion interface of the RAM connections is realized using the Fabric Interface XTINF modules of DSP.
5. the system as claimed in claim 1, it is characterised in that
TMS320F2823x DSP veneer of the DSP veneers using TI, the FPGA adopt Altera
Cyclone IV 4CE6FPGA.
6. the system as claimed in claim 1, it is characterised in that also include：
Verification management module, for configuring the outer of DSP veneers of the FPGA/CPLD by software emulation
Circuit is enclosed, the dsp software operation result of DSP veneers output is received and record, according to the operation result
Whether checking dsp software is correct.
7. a kind of Digital Signal Processing dsp software verification method, it is characterised in that include：
By the software emulation on on-site programmable gate array FPGA/complex programmable logic device (CPLD)
The peripheral circuit of DSP veneers；
Dsp software is run on DSP veneers and operation result is exported to verify whether dsp software is correct,
In dsp software running, the data is activation of peripheral circuit will be sent to RAM, needed from peripheral electricity
Road is read when reading data from the RAM, periphery electricity of the FPGA/CPLD by software emulation
Road, reads the data that dsp software sends from RAM, needs to send when sending data to dsp software
To in RAM.
8. method as claimed in claim 7, it is characterised in that by the software on FPGA/CPLD
The peripheral circuit of emulation DSP veneers, specifically includes：
The peripheral circuit that Hardware Description Language VHDL source code emulates DSP veneers is configured manually；
Or
By configuring Matlab softwares, by Matlab generate VHDL compilation of source code and download to FPGA/
On CPLD, the peripheral circuit of DSP veneers is emulated.
9. method as claimed in claim 7, it is characterised in that the FPGA/CPLD passes through software
The peripheral circuit of the DSP veneers of emulation includes：
Signal sample circuit, signal deteching circuit, Switching Converter Topologies, LC filter circuits.
10. method as claimed in claim 7, it is characterised in that also include：
The dsp software operation result of DSP veneers output is received and recorded, is verified according to the operation result
Whether dsp software is correct.
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| CN201510611543.1A CN106547937A (en) | 2015-09-23 | 2015-09-23 | A kind of Digital Signal Processing dsp software checking system and method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115685864A (en) * | 2022-09-15 | 2023-02-03 | 江苏亚威机床股份有限公司 | Bending machine control method |
| CN115994096A (en) * | 2023-03-21 | 2023-04-21 | 安徽隼波科技有限公司 | Verification method for radar signal processing and simulation |
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| CN104009541A (en) * | 2014-05-07 | 2014-08-27 | 深圳市国电南思系统控制有限公司 | System and method for processing operation information of intelligent substation |
| CN203812236U (en) * | 2013-11-29 | 2014-09-03 | 力博特公司 | Data exchange system based on processor and field programmable gate array |
| CN104267264A (en) * | 2014-09-16 | 2015-01-07 | 国家电网公司 | Transformer insulation oil dielectric loss and electrical resistivity automatic detecting system |
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| CN103812739A (en) * | 2012-11-06 | 2014-05-21 | 中国北车股份有限公司 | Communication apparatus and communication method between FPGA and DSP |
| CN203812236U (en) * | 2013-11-29 | 2014-09-03 | 力博特公司 | Data exchange system based on processor and field programmable gate array |
| CN104009541A (en) * | 2014-05-07 | 2014-08-27 | 深圳市国电南思系统控制有限公司 | System and method for processing operation information of intelligent substation |
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| CN115685864A (en) * | 2022-09-15 | 2023-02-03 | 江苏亚威机床股份有限公司 | Bending machine control method |
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