CN106533425B - High-res time to digital converter and its method - Google Patents
High-res time to digital converter and its method Download PDFInfo
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- CN106533425B CN106533425B CN201610604840.8A CN201610604840A CN106533425B CN 106533425 B CN106533425 B CN 106533425B CN 201610604840 A CN201610604840 A CN 201610604840A CN 106533425 B CN106533425 B CN 106533425B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
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Abstract
A kind of time-to-digital converter includes: a rectifier, and for receiving one first clock signal and a second clock signal and exporting a rectified signal, wherein the difference of the second clock signal and first clock signal is a timing off-set；One low-pass filter, for receiving the rectified signal and exporting a filtering signal；And an analog-to-digital converter, for the filtering signal is converted into a digital signal.
Description
Technical field
The present invention relates generally to a time-to-digital converter.
Background technique
Those skilled in the art of the present technique can understand the term and basic conception of microelectronic field in present disclosure, described
Term and basic conception seem voltage, signal, logical signal, clock, phase, the period, trip point (trip point), resistance,
Capacitor, transistor, MOS (metal-oxide-semiconductor (MOS)), PMOS (P channel metal-oxide-semiconductor (MOS)), NMOS (N channel metal-oxide-semiconductor (MOS)), source electrode,
Grid, drain electrode, rectifier (rectifier), half-wave rectifier (half-wave rectifier), full-wave rectifier (full-
Wave rectifier) and analog-to-digital converter.Suchlike term and basic conception are to those skilled in the art
For be apparent easy to know, therefore correlative detail herein will it will not go into details.
In the disclosure, a logical signal refers to a kind of signal with two kinds of states, two kinds of states be respectively "
It is high " and " low ", can also say it is " 1 " and " 0 ".In order to illustrate succinct, when a logical signal is in the "high" (" low ") state, I
Can referred to as this logical signal be "high" (" low "), or referred to as this logical signal be " 1 " (" 0 ").Similarly, in order to illustrate letter
Clean, our occasionals omit quotation marks, and referred to as the logical signal is high (low), or referred to as this logical signal is 1 (0), while can
To understand in a manner of above description for illustrating a level state of the logical signal in context train of thought.
When a logical signal is high, referred to as establishment (asserted)；When a logical signal is low, referred to as stopping
It establishes (de-asserted).
One clock signal is a periodic logical signal and has a period.In order to illustrate succinct, explanation hereafter
In, " clock signal " can be called " clock " for short.
One time-to-digital converter receive one first clock and a second clock and one digital code of output represent this
A time sequence difference (timing difference) between one and second clock.Time-to-digital converter belongs to showing for this field
There is skill, it will not be described here for details.
One self-calibrating multiphase clock circuit (self-calibrating multi-phase clock circuit)
The case being disclosed in an application is entitled " the leggy clock pulse circuit and its method of self-calibrating ", uses the time to number
Converter to execute calibrating operation to a multiphase clock.Typically, calibrating operation can not be very accurate, unless the time is extremely
Digital quantizer has high-res (high resolution)；In addition, if the multiphase clock have a high-frequency, this when
Between need parse the timing of (resolve) high frequency clock to digital quantizer, however design one with high-res and energy
Enough parse high frequency clock timing time-to-digital converter be it is very difficult, for example, to be up to 1ps (parts per trillion
One second) resolution come the timing for parsing a multiphase clock (frequency 25GHz) be extremely difficult thing.
This field what is desired is that one with high-res and can parse high frequency clock timing time to number
Converter.
Summary of the invention
According to an exemplary embodiment, of the invention one is using a rectifier towards (aspect) to convert for the moment
One timing off-set of clock signal simultaneously generates a rectified signal, filters the rectified signal to generate a filtering signal and conversion and be somebody's turn to do
Filtering signal represents the timing off-set to generate a digital code.
According to an exemplary embodiment, of the invention one towards being to use a transmission gate as a rectifier, whereby
Convert a timing off-set of a clock signal and generate a rectified signal, filter the rectified signal with generate a filtering signal, with
And it converts the filtering signal and represents the timing off-set to generate a digital code.
In an exemplary embodiment, a circuit of the invention includes: a rectifier, for receiving one first clock letter
Number with a second clock signal and export a rectified signal, wherein the difference of the second clock signal and first clock signal exists
In a timing off-set；One low-pass filter, for receiving the rectified signal and exporting a filtering signal；And one simulation to number
Converter, for the filtering signal is converted into a digital signal.In an exemplary embodiment, which includes one the
One half-wave rectifier, which includes: the transmission gate of a first kind, is used to pass according to the second clock signal
Pass a first end of first clock signal to the rectified signal.In an exemplary embodiment, the transmission of the first kind
Lock includes: MOS (metal-oxide-semiconductor (MOS)) transistor of a first kind, wherein a source electrode of the MOS transistor of the first kind, one
Grid and a drain electrode are respectively coupled to the first end of first clock signal, the second clock signal and the rectified signal.
In an exemplary embodiment, the transmission gate of the first kind is further included: the MOS transistor of a Second Type, wherein
One source electrode of the MOS transistor of the Second Type, a grid and a drain electrode be respectively coupled to the second clock signal, this second when
The first end of clock signal and the rectified signal.In an exemplary embodiment, which is further wrapped
Contain: the transmission gate of a Second Type, for transmitting the second clock signal to the rectified signal according to first clock signal
One second end.In an exemplary embodiment, the transmission gate of the Second Type includes: the MOS transistor of a Second Type,
In the Second Type a source electrode of MOS transistor, a grid and a drain electrode be respectively coupled to the second clock signal, this first
This of clock signal and the rectified signal second end.In an exemplary embodiment, the transmission gate of the Second Type is into one
Step includes: the MOS transistor of a first kind, wherein a source electrode of the MOS transistor of the first kind, a grid and a drain electrode
It is respectively coupled to the second end of first clock signal, first clock signal and the rectified signal.It is exemplary in one
In embodiment, which further includes one second half-wave rectifier, second half-wave rectifier and first halfwave rectifier
The difference of device is the role exchange of first clock signal and the second clock signal.It, should in an exemplary embodiment
Low-pass filter includes a shunting capacitance.In an exemplary embodiment, which further includes a series electrical
Resistance.
In an exemplary embodiment, a method of the invention includes: when receiving one first clock signal with one second
Clock signal, wherein the difference of the second clock signal and first clock signal is a timing off-set；It is whole using a rectifier
The difference between first clock signal and the second clock signal is flowed to generate a rectified signal；Use a low-pass filter
The rectified signal is filtered to generate a filtering signal；And the filtering signal is converted to generate using an analog-to-digital converter
One digital signal.In an exemplary embodiment, which includes one first half-wave rectifier, first half-wave rectifier
Include: the transmission gate of a first kind, for transmitting first clock signal to the rectified signal according to the second clock signal
A first end.In an exemplary embodiment, the transmission gate of the first kind includes: MOS (the golden oxygen half of a first kind
Conductor) transistor, wherein a source electrode of the MOS transistor of the first kind, a grid and one drain electrode be respectively coupled to this first
The first end of clock signal, the second clock signal and the rectified signal.In an exemplary embodiment, the first kind
The transmission gate of type further includes: the MOS transistor of a Second Type, wherein a source electrode of the MOS transistor of the Second Type,
One grid and one drain electrode be respectively coupled to the second clock signal, the second clock signal and the rectified signal this first
End.In an exemplary embodiment, which is further included: the transmission gate of a Second Type, be used to according to
A second end of the second clock signal to the rectified signal is transmitted according to first clock signal.In an exemplary embodiment
In, the transmission gate of the Second Type includes: the MOS transistor of a Second Type, wherein the one of the MOS transistor of the Second Type
Source electrode, a grid and a drain electrode are respectively coupled to being somebody's turn to do for the second clock signal, first clock signal and the rectified signal
Second end.In an exemplary embodiment, the transmission gate of the Second Type is further included: the MOS crystal of a first kind
Pipe, wherein a source electrode of the MOS transistor of the first kind, a grid with one drain be respectively coupled to first clock signal,
The second end of first clock signal and the rectified signal.In an exemplary embodiment, which is further wrapped
Containing one second half-wave rectifier, the difference of second half-wave rectifier and first half-wave rectifier is first clock signal
With the role exchange of the second clock signal.In an exemplary embodiment, which includes a shunting capacitance.In
In one exemplary embodiment, which further includes series resistance.
Detailed description of the invention
(Figure 1A) shows a functional block diagram of a time-to-digital converter according to an exemplary embodiment.
(Figure 1B) shows an exemplary timing diagram of the time-to-digital converter of Figure 1A.
(Fig. 2A) shows a schematic diagram of a rectifier according to an exemplary embodiment.
(Fig. 2 B) shows a schematic diagram of a P type transfers lock according to an exemplary embodiment.
(Fig. 2 C) shows a schematic diagram of a N type transfers lock according to an exemplary embodiment.
(Fig. 3) shows a schematic diagram of a low-pass filter according to an exemplary embodiment.
(Fig. 4) shows an analog result of the waveform of the filtering signal of the low-pass filter of Fig. 3.
Description of symbols:
100 time-to-digital converters (TDC)
110 rectifiers
120 analog-to-digital converters (ADC)
130 low-pass filters (LPF)
The first clock signal of CKA
CKB second clock signal
X rectified signal
V filtering signal
DK digital signal
151,153,155 positive pulse
152,154,156 negative pulse
161,163,165 positive pulse (odd number impulse)
162,164,166 positive pulses (punching of coupling rapid pulse)
TCKPeriod
TOSTiming off-set
VHHigh voltage
VLLow-voltage
Difference between DAB CKA and CKB
200 rectifiers
210 first half-wave rectifiers
220 second half-wave rectifiers
210P the first P-type transmission lock
210N the first N-type transmission gate
220P the second P-type transmission lock
220N the second N-type transmission gate
X+The first end of rectified signal X
X?The second end of rectified signal X
I input terminal
O output end
C control terminal
231 PMOS transistors
232 NMOS transistors
241 NMOS transistors
242 PMOS transistors
The first series resistance of R1
The second series resistance of R2
The first shunting capacitance of C1
The second shunting capacitance of C2
V+、V?One end of filtering signal V
Specific embodiment
The present invention advocates U.S. patent application case (Application No.: 14/854,495；The applying date: 2015/9/15) preferential
Power, all the elements of this application are quoted by the present invention as reference.
The present invention is relevant to a time-to-digital converter.Although this specification refers to several implementation examples of the invention,
It is related to the better model when present invention is implemented, however the present invention can realize in many ways, that is, the present invention not by
It is limited to aftermentioned particular implementation example or ad hoc fashion, wherein it is special to be loaded with the technology being carried out for the particular implementation example or mode
Sign.Furthermore it is known that details will not be shown or illustrate, avoid the presentation for interfering feature of the invention whereby.
The presentation of the disclosure is from an engineering terms, wherein if one first magnitude (first quantity) and one the
Less than a given tolerance, which can be described as " being equal to difference between two magnitudes (second quantity)
(equal to) " second magnitude.For example, if the given tolerance is 0.5mv or other design value appropriate,
100.2mV can be described as being equal to 100mV.In other words, when statement " A equals B ", which means " without real between A and B
Matter difference " considers lower done measurement similar to Practical Project.
Figure 1A shows a TDC (time-to-digital converter (time-to-digital according to an exemplary embodiment
Converter)) 100 functional block diagram.The TDC 100 includes: a rectifier 110, for receiving one first clock signal
A CKA and second clock signal CKB simultaneously exports a rectified signal X；One LPF (low-pass filter (low-pass filter))
130, for receiving rectified signal X and exporting a filtering signal V；An and ADC (analog-to-digital converter (analog-
To-digital converter)) 120, for filtering signal V is converted into a digital signal DK.In order to illustrate succinct, this
First clock signal CKA will be called CKA for short afterwards, second clock signal CKB will be called CKB, rectified signal X for short will
It is called X for short, filtering signal V will be called V for short and digital signal DK will be called DK for short.In addition to a timing off-set
(timing offset) outside, CKA and CKB are that (in other words, the difference of CKA and CKB is that the timing is inclined to identical clock herein
It moves).The period for enabling CKA is TCK, enabling the timing off-set is TOS, one of the function of the TDC 100 is to parse the timing off-set
TOSAnd it is indicated with DK.The rectifier 110 is together with the LPF 130 by timing off-set TOSV is converted to, so that V is effectively
Represent TOS.Next V is converted to DK by the ADC 120, so that DK effectively represents TOS, to realize the time to number
The function of conversion.Even if CKA and CKB may be high-frequency signal, timing off-set TOSAlmost one fixed offset, therefore, V meeting
It is the signal slowly changed, and can be effectively handled in a manner of high-res by ADC 120.According to the above, only
Will the rectifier 110 and the LPF 130 can be suitably by timing off-set TOSBe converted to V, TOSIt just can be with the side of high-res
Formula and be resolved.
Figure 1B shows an exemplary timing diagram, for illustrating the principle of an exemplary embodiment.As shown, CKA
Being is T in the periodCKA clock, the difference of CKB and CKA is timing off-set TOS, V hereinHWith VLIt is the clock respectively
(CKA or CKB) be it is high with it is low when voltage level, DAB is the difference between CKA and CKB, that is, DAB=CKA-CKB, by
Timing off-set between CKA and CKB, DAB are essentially (the impulsive in nature) of pulse feature and include a succession of
Pulse converts in turn between a positive pulse (such as 151,153,155) and a negative pulse (such as 152,154,156)
(alternating), wherein the width of each pulse (either positive or negative) is TOSAnd height is VH-VL.One demonstration
Property embodiment one towards (aspect) be to DAB execute rectifying operation (rectification) with export the rectification letter
Number X, that is, X=| DAB |=| CKA-CKB |.Based on the rectifying operation, X is substantially also pulse feature, but is only comprising width
TOSPositive pulse (such as 161,162 ..., 166), wherein the width of each pulse be TOSAnd height is VH-VL.It will be clear that
Be X an average value be equal to 2. (VH-VL).TOS/TCK, therefore the average value of the X is proportional to TOS, so as to be used to represent
TOS.The LPF 130 effectively executes an average operation to X, so that filtering signal V derived from institute is proportional to TOSAnd can have
Represent T to effectOS。
Fig. 2A depicts the schematic diagram of a rectifier 200 according to an exemplary embodiment, and rectifier 200 can be realized figure
The rectifier 110 of 1A.Rectified signal X is by a differential wave (differential signal) Lai Shixian, the differential letter herein
Number include a first end (first end) X+With a second end (second end) X?, and rectified signal X is equivalent to X+With X?
Between a difference, the concept that " differential wave " is well known to those skilled in the art, it will not be described here for details.Rectifier
200 include one first half-wave rectifier (half-wave rectifier) 210 and one second half-wave rectifier 220.This first half
Wave rectifier 210 includes: one first P-type transmission lock (transmission gate) 210P and one first N-type transmission gate
210N.Second half-wave rectifier 220 includes: one second P-type transmission lock 220P and one second N-type transmission gate 220N.It is above-mentioned
Four transmission gates (i.e. the first P-type transmission lock 210P, the second P-type transmission lock 220P, the first N-type transmission gate 210N and
Second N-type transmission gate 220N) each tool there are three endpoint (three terminals) include an input terminal be denoted as "
I ", an output end are denoted as " O " and a control terminal is denoted as " C ".First p-type (N-type) the transmission gate 210P's (210N) should
Input terminal " I ", the control terminal " C " and the output end " O " are respectively coupled to CKA (CKB), CKB (CKA) and X+(X?).This
The input terminal " I ", the control terminal " C " and output end " O " of two p-types (N-type) transmission gate 220P (220N) is respectively coupled to CKB
(CKA), CKA (CKB) and X+(X?).For a P-type transmission lock (210P or 220P), when its control terminal " C " is stopped really
Vertical (de-asserted), input terminal " I " received signal can be passed to its output end " O ".To a N-type transmission gate
For (210N or 220N), when its control terminal " C " is established (asserted), input terminal " I " received signal can be passed
It is delivered to its output end " O ".Therefore, when CKA is high (that is, to have a high voltage VH) and CKB be it is low (that is, have a low electricity
Press VL), the first P-type transmission lock 210P is by high voltage VHIt is transferred to X+, the first N-type transmission gate 210N is by the low electricity at this time
Press VLIt is transferred to X?, to effectively transmit a positive pulse (such as 151,153 and 155 of Figure 1B) of DAB to an odd number arteries and veins of X
It rushes (such as 161,163,165 of Figure 1B)；When CKB is high (that is, to have a high voltage VH) and CKA be it is low (that is, have one
Low-voltage VL), the second P-type transmission lock 220P is by high voltage VHIt is transferred to X+, the second N-type transmission gate 220N should at this time
Low-voltage VLIt is transferred to X?, to effectively transmit a negative pulse (such as 152,154 and 156 of Figure 1B) of DAB to a coupling of X
Rapid pulse rushes (such as 162,164,166 of Figure 1B).First half-wave rectifier 210 whereby rectifies the positive pulse of DAB, this
When the second half-wave rectifier 220 negative pulse of DAB is rectified.Generally speaking, rectifier 200 whereby performs full DAB
Wave rectification.
Fig. 2 B depicts the schematic diagram of a P-type transmission lock 230 according to an exemplary embodiment.The P-type transmission lock 230 is
One or three pole elements (three-terminal device), be denoted as " I " comprising an input terminal, an output end be denoted as " O " and
One control terminal is denoted as " C ".The P-type transmission lock 230 can be used to realize the first P-type transmission lock 210P and the 2nd P of Fig. 2A
Type transmission gate 220P.When the P-type transmission lock 230 is used to realize first (the second) P-type transmission lock 210P (220P), the input
" I " is coupled to CKA (CKB), the control terminal " C " is coupled to CKB (CKA), the output end " O " is coupled to X at end+.The P-type transmission lock
230 include a PMOS (p-channel metal-oxide-semiconductor (MOS)) transistor 231.Source electrode, grid and the drain electrode of the PMOS transistor 231 are distinguished
It is coupled to the input terminal " I ", the control terminal " C " and the output end " O " of the P-type transmission lock 230." the source of one PMOS transistor
Pole ", " grid " and " drain electrode " are well known to those skilled in the art, therefore it will not be described here for details.Use a PMOS transistor
To realize that a transmission gate is similarly as it is known to those skilled in the art that also it will not go into details to correlative detail.In a selectivity
In exemplary embodiment, which further includes a NMOS (n-channel metal-oxide-semiconductor (MOS)) transistor 232, should
Source electrode, grid and the drain electrode of NMOS transistor 232 be respectively coupled to the control terminal " C " of the P-type transmission lock 230, the control terminal "
C " and the output end " O "." source electrode ", " grid " of one NMOS transistor are well known to those skilled in the art with " drain electrode ",
It will not be described here for details.One purpose of the NMOS transistor 232 is to help so that the P-type transmission lock 230 balances
(balanced).When the signal for being located at the output end " I " and the signal for being located at the control terminal " C " they are low, the P-type transmission lock
230 may partly transmit low-voltage VLTo the output end " O ", to introduce an offset (offset) to the output end " O ".
By importing the NMOS transistor 232, when the signal for being located at the control terminal " C " is high, which may also can
Partly transmit high voltage VHTo the output end " O ", to compensate for offset caused by the output end " O ".It is worth note
Meaning be Fig. 2A rectifier 200 rectification function in the presence of the offset still maintenance effect, but compensate the offset and can improve
The correctness of the rectifier 200, thus it is quite practical.
Fig. 2 C depicts the schematic diagram of a N-type transmission gate 240 according to an exemplary embodiment.The N-type transmission gate 240 is
One or three pole elements are denoted as " I " comprising an input terminal, an output end is denoted as " O " and a control terminal is denoted as " C ".The N-type
Transmission gate 240 can be used to realize the first N-type transmission gate 210N and the second N-type transmission gate 220N of Fig. 2A.When the N-type is transmitted
Lock 240 is used to realize first (the second) N-type transmission gate 210N (220N), which is coupled to CKB (CKA), the control
End " C " processed is coupled to CKA (CKB), the output end " O " is coupled to X?.The N-type transmission gate 240 includes a NMOS transistor 241.
Source electrode, grid and the drain electrode of the NMOS transistor 241 are respectively coupled to the input terminal " I ", the control of the N-type transmission gate 240
Hold " C " and the output end " O ".Realized using a NMOS transistor transmission gate be similarly as it is known to those skilled in the art that
Therefore it will not be described here for details.In the exemplary embodiment of a selectivity, which further includes a PMOS
Transistor 242, source electrode, grid and the drain electrode of the PMOS transistor 242 be respectively coupled to the N-type transmission gate 240 the control terminal "
C ", the control terminal " C " and the output end " O ".One purpose of the PMOS transistor 242 is to help so that the N-type transmission gate 240
Balance.When the signal for being located at the output end " I " and the signal for being located at the control terminal " C " are high, which can
High voltage V can partly be transmittedHTo the output end " O ", so that introducing one is offset to the output end " O ".It should by importing
PMOS transistor 242, when the signal for being located at the control terminal " C " is low, which also can may partly be transmitted
Low-voltage VLTo the output end " O ", to compensate for offset caused by the output end " O ".It is worth noting that Fig. 2A
Rectifier 200 rectification function in the presence of the offset still maintenance effect, but compensate the offset and can improve the rectifier 200
Correctness, therefore it is quite practical.
Please referring again to Fig. 2A.Other than the role exchange (swapped) of CKA and CKB, second half-wave rectifier 220
It is identical as first half-wave rectifier 210.By using first half-wave rectifier 210 and second half-wave rectifier 220
In conjunction with rectifier 200 is carried out full-wave rectification, and wherein the positive pulse (that is, when it is low that CKA, which is high and CKB) of DAB is by this
The rectification of first half-wave rectifier 210, and the negative pulse (that is, when CKA is low and CKB is high) of DAB is by second halfwave rectifier
Device 220 rectifies.However, rectifier 110 can pass through a full-wave rectifier for the time-to-digital converter 100 of Figure 1A
Or one half-wave rectifier be implemented.When rectifier 110 is implemented by a half-wave rectifier, rectifier 110 remains to transport
Make, but a gain factor (gainfactor) can be halved that (that is, the average value of the X can be reduced to (VH-VL).TOS/TCK)。
Based on to above explained understanding, in the exemplary embodiment of a selectivity, which is removed, in
In this example, a half-wave rectifying operation is performed, and only negative pulse can be rectified；In another selective exemplary embodiment
In, which is removed, and in this example, a half-wave rectifying operation is performed, and only positive pulse is whole
Stream.
The one of one exemplary embodiment can be an extremely fast (extremely towards are as follows: the rectifier 200 of Fig. 2A
Fast) circuit, because use a transmission gate therefore, in input (that is, CKA and CKB) and output (that is, X+With X?) between only one
Single transistor delay (single transistor delay).Therefore, rectifier 200 can be used to one hypervelocity of processing
(very high speed) clock.
Fig. 3 is painted the schematic diagram of a low-pass filter (LPF) 300 according to an exemplary embodiment, and LPF 300 can be used to
Realize the LPF 130 of Figure 1A.LPF 300 includes: one first series resistance (serialresistor) R1, one first shunting capacitance
(shunt capacitor) C1, one second series resistance R2 and one second shunting capacitance C2.Rectified signal X is logical herein
It crosses a differential wave and is carried out, which includes a first end X+With a second end X?, and rectified signal X is equivalent to
X+With X?Between a difference.Similarly, filtering signal V is carried out by a differential wave, which includes
One first end V+With a second end V?, and filtering signal V is equivalent to V+With V?Between a difference.For those skilled in the art
Member for, Fig. 3 it will be clear that and it is to be understood that therefore its details it will not be described here.In addition, the first series resistance R1 and this
Two series resistance R2 are selective, therefore can be removed.
Fig. 4 shows that an analog result of the waveform of filtering signal V, the analog result are based on a 25GHz clock, is loud
Answer (in response to) timing off-set TOSDifferent value.In in the prior art, a 1ps (parts per trillion of a 25GHz clock
One second) timing off-set be very difficult to detect, but the timing off-set is converted in an exemplary embodiment of the invention
The burning voltage for being about 130mv for voltage value (can refer to figure by subsequent analog-to-digital converter (ADC) 120
1A) detects and convert easily.Analog-to-digital converter is the state of the art, and it will not be described here for details.It should
The one of exemplary embodiment towards are as follows: therefore, filtering signal V can be one slow due to using the low-pass filter 130 of Figure 1A
Slowly (slowly-changing) signal changed, and can be located in easily by subsequent analog-to-digital converter (ADC) 120
Reason.
In Fig. 2A, 2B and Fig. 3, differential wave is used.It is worth noting that differential wave is one preferable but unrestricted
The embodiment of property.Circuit designers can use single-ended signal (single-ended signaling) according to its judgement selection.When making
When with single-ended signal, it is only necessary to one end (X of rectified signal X+Or X?) and filtering signal V one end (V+Or V?), at this time
Become unimportant for handling the circuit of the signal of the other end, and can be removed.For example, if only X+It is used, it should
Two N-type transmission gate 210N and 220N (as shown in Figure 2 A), the second series resistance R2 and the second shunting capacitance C2 (such as Fig. 3
It is shown) it can be removed.If only X?It is used, the two P-type transmissions lock 210P and 220P (as shown in Figure 2 A), first series electrical
Resistance R1 and first shunting capacitance C1 (as shown in Figure 3) can be removed.
Although the embodiment of the present invention is as described above, however those embodiments not are used to limit the present invention, this technology neck
The content that field technique personnel can express or imply according to the present invention imposes variation to technical characteristic of the invention, all this kind change
Change may belong to patent protection scope sought by the present invention, and in other words, scope of patent protection of the invention must regard this explanation
Subject to the as defined in claim of book.
Claims (10)
1. a kind of time-to-digital converter, includes:
One rectifier, for receiving one first clock signal and a second clock signal and exporting a rectified signal, wherein this
The difference of two clock signals and first clock signal is a timing off-set；
One low-pass filter, for receiving the rectified signal and exporting a filtering signal；And
One analog-to-digital converter, for the filtering signal is converted into a digital signal.
2. time-to-digital converter as described in claim 1, wherein the rectifier includes one first half-wave rectifier, this
One half-wave rectifier includes: the transmission gate of a first kind, for transmitting first clock signal according to the second clock signal
To a first end of the rectified signal.
3. time-to-digital converter as claimed in claim 2, wherein the transmission gate of the first kind includes: a first kind
MOS transistor, wherein a source electrode of the MOS transistor of the first kind, a grid and one drain electrode be respectively coupled to this first
The first end of clock signal, the second clock signal and the rectified signal.
4. time-to-digital converter as claimed in claim 3, wherein the transmission gate of the first kind further includes: one
The MOS transistor of two types, wherein a source electrode of the MOS transistor of the Second Type, a grid and a drain electrode are respectively coupled to
The first end of the second clock signal, the second clock signal and the rectified signal.
5. time-to-digital converter as claimed in claim 2, wherein first half-wave rectifier further includes: one second
The transmission gate of type, for transmitting a second end of the second clock signal to the rectified signal according to first clock signal.
6. time-to-digital converter as claimed in claim 5, wherein the transmission gate of the Second Type includes: a Second Type
MOS transistor, wherein a source electrode of the MOS transistor of the Second Type, a grid and one drain electrode be respectively coupled to this second
The second end of clock signal, first clock signal and the rectified signal.
7. time-to-digital converter as claimed in claim 6, wherein the transmission gate of the Second Type further includes: one
The MOS transistor of one type, wherein a source electrode of the MOS transistor of the first kind, a grid and a drain electrode are respectively coupled to
The second end of first clock signal, first clock signal and the rectified signal.
8. time-to-digital converter as claimed in claim 2, wherein the rectifier further includes one second halfwave rectifier
A full-wave rectifier is collectively formed in device, second half-wave rectifier and first half-wave rectifier.
9. time-to-digital converter as described in claim 1, wherein the low-pass filter includes a shunting capacitance.
10. a kind of time to digital conversion method, includes:
One first clock signal and a second clock signal are received, wherein the difference of the second clock signal and first clock signal
It is different to be a timing off-set；
Using the difference between a rectifier rectification first clock signal and the second clock signal to generate rectification letter
Number；
The rectified signal is filtered using a low-pass filter to generate a filtering signal；And
The filtering signal is converted using an analog-to-digital converter to generate a digital signal.
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| US14/854,495 US9344103B1 (en) | 2015-07-21 | 2015-09-15 | High-resolution time-to-digital converter and method thereof |
| US14/854,495 | 2015-09-15 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101594149A (en) * | 2008-05-29 | 2009-12-02 | 瑞昱半导体股份有限公司 | Time-to-digital converter and its method |
| CN104040903A (en) * | 2011-08-19 | 2014-09-10 | 路梅戴尼科技公司 | Time Domain Switched Analog-to Digital Converter Apparatus And Methods |
| US8957712B2 (en) * | 2013-03-15 | 2015-02-17 | Qualcomm Incorporated | Mixed signal TDC with embedded T2V ADC |
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| US8064561B2 (en) * | 2007-09-16 | 2011-11-22 | Infineon Technologies Ag | Determining a time interval based on a first signal, a second signal, and a jitter of the first signal |
| US9456257B2 (en) * | 2013-09-12 | 2016-09-27 | Texas Instruments Incorporated | Device for transferring power from a first circuit to a second circuit |
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2016
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101594149A (en) * | 2008-05-29 | 2009-12-02 | 瑞昱半导体股份有限公司 | Time-to-digital converter and its method |
| CN104040903A (en) * | 2011-08-19 | 2014-09-10 | 路梅戴尼科技公司 | Time Domain Switched Analog-to Digital Converter Apparatus And Methods |
| US8957712B2 (en) * | 2013-03-15 | 2015-02-17 | Qualcomm Incorporated | Mixed signal TDC with embedded T2V ADC |
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| CN106533425A (en) | 2017-03-22 |
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| TW201710808A (en) | 2017-03-16 |
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