CN106533370B - Operational amplification circuit with direct current offset technology for eliminating - Google Patents
Operational amplification circuit with direct current offset technology for eliminating Download PDFInfo
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- CN106533370B CN106533370B CN201510585247.9A CN201510585247A CN106533370B CN 106533370 B CN106533370 B CN 106533370B CN 201510585247 A CN201510585247 A CN 201510585247A CN 106533370 B CN106533370 B CN 106533370B
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- 239000003990 capacitor Substances 0.000 claims description 33
- 230000008030 elimination Effects 0.000 claims description 24
- 238000003379 elimination reaction Methods 0.000 claims description 24
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- 239000004065 semiconductor Substances 0.000 description 4
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- 239000013078 crystal Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
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Abstract
A kind of operational amplification circuit with direct current offset technology for eliminating includes an operational amplifier and an offset voltage compensator.The operational amplifier includes first non-inverting input of one inverting input terminal, a reception the first input voltage, and an offer one is relevant to the output end of the output voltage of first input voltage, when mismatching between the inverting input terminal and first non-inverting input, an offset voltage is will be present in the common-mode voltage between the inverting input terminal and first non-inverting input.The offset voltage compensator is electrically connected between the inverting input terminal, first non-inverting input and the output end of the operational amplifier, and the offset voltage is replicated to obtain the voltage that prestores for being identical to the offset voltage, and the voltage compensation output voltage is prestored according to this.
Description
Technical field
The present invention relates to a kind of operational amplification circuits, put more particularly to a kind of operation with direct current offset technology for eliminating
Big circuit.
Background technique
Existing operational amplifier causes the crystalline substance of its differential input level due to the process variation in the presence of production process
It is mismatched between body pipe, so that each operational amplifier after volume production respectively has different direct current offsets.The direct current offset will
It is unfavorable for the operational amplifier in the application category of high-precision or high standard.A kind of cancellation of existing direct current offset,
Be the compensation of the offset is carried out to each operational amplifier by adjusting outer member (such as variable resistance), however this
The external pins that the mode of sample not only needs to increase the operational amplifier thus increase the cost of encapsulation, and are also short of using upper
Convenience.
Summary of the invention
It can be compensated the purpose of the present invention is to provide a kind of control by internal circuit and eliminate the direct current offset
Operational amplification circuit with direct current offset technology for eliminating.
Operational amplification circuit with direct current offset technology for eliminating of the invention includes: an operational amplifier and one
Offset voltage compensator.The operational amplifier include an inverting input terminal, one reception one the first input voltage first
Non-inverting input and an offer one are relevant to the output end of the output voltage of first input voltage, when the reverse phase is defeated
When entering to hold mismatching between first non-inverting input, the common mode between the inverting input terminal and first non-inverting input is electric
An offset voltage will be present in pressure.The offset voltage compensator be electrically connected to the operational amplifier the inverting input terminal, this
Between one non-inverting input and the output end, and replicate the offset voltage with obtain one be identical to the offset voltage prestore electricity
Pressure, and the voltage compensation output voltage is prestored according to this.
Preferably, the offset voltage compensator includes one for storing the energy-storage units for prestoring voltage and one is electrically connected
The switch unit of the energy-storage units is connect, which has the of the inverting input terminal for being electrically connected the operational amplifier
One end and a second end, the switch unit are made that the second end suspension joint of the energy-storage units, to be electrically connected this first noninverting by control
Input terminal or the output end.
Preferably, the operational amplifier further includes the second non-inverting input of one the second input voltage of a reception,
The energy-storage units also have a third end, a first capacitor being electrically connected between the first end and the second end and one
The second capacitor being electrically connected between the first end and the third end, and the switch unit has a first switch, one second
Switch, a third switch, the 4th switch and one the 5th switch, the first switch are electrically connected to being somebody's turn to do for the energy-storage units
It between first end and the output end, and is controlled in conducting and is switched between being not turned on, which is electrically connected to the energy-storage units
The third end and second non-inverting input between, and be controlled in conducting and switched between being not turned on, third switch is electrically connected
It is connected between the second end of the energy-storage units and first non-inverting input, and is controlled in conducting and switched between being not turned on,
4th switch is electrically connected between the third end of the energy-storage units and the output end, and is controlled in conducting and cut between being not turned on
It changes and the 5th switch is electrically connected between the second end of the energy-storage units and the output end, and be controlled in conducting and do not led
Switch between logical.
Preferably, the offset voltage compensator further includes the control for being electrically connected the first to the 5th switch of the switch unit
Unit processed, and a buffer mode, a storage mode and an elimination mode are operated in, delay when the control unit operates in this
When punch die formula, the control unit control the first switch be conducting, the second switch be not turned on, third switch is does not lead
Logical, the 4th switch is is not turned on and the 5th switch is is not turned on；It, should when the control unit operates in the storage mode
Control unit controls that the first switch is conducting, the second switch is conducting, third switch is conducting, the 4th switch for not
Conducting and the 5th switch are to be not turned on；When the control unit operates in the elimination mode, the control unit control this first
Switch for be not turned on, the second switch be not turned on, the third switch for be not turned on, the 4th switch be conducting and the 5th
Switch is conducting.
Preferably, the energy-storage units also have a first transistor, first current source, a second transistor and
One the second current source, the first transistor have first end, a second end for one the first bias generator of an electrical connection, and
One is electrically connected to the control terminal of third switch；First current source is electrically connected the second end of the first transistor and one the
Between two bias generators, the current potential of second bias generator is less than the current potential of first bias generator；The second transistor has one and is electrically connected
Connect the first end of first bias generator, a second end and one are electrically connected to the control terminal of the second switch；Second electric current
Source is electrically connected between the second end of the second transistor and second bias generator.
Preferably, the offset voltage compensator further includes the control for being electrically connected the first to the 5th switch of the switch unit
Unit processed, and operate in a storage mode and an elimination mode, when the control unit operates in the storage mode, the control
Unit processed controls that the first switch is conducting, the second switch is conducting, third switch is conducting, the 4th switch not lead
Logical and the 5th switch is to be not turned on；When the control unit operates in the elimination mode, which controls this and first opens
Close for be not turned on, the second switch be not turned on, the third switch for be not turned on, the 4th switch be that conducting and the 5th open
It closes as conducting.
Preferably, the switch unit has a first switch, a third switch and one the 5th switch.This first is opened
It is powered-down to be connected between the first end of the energy-storage units and the output end, and be controlled in conducting and switched between being not turned on；This
Three switches are electrically connected between the second end of the energy-storage units and first non-inverting input, and are controlled in conducting and do not led
Switch between logical；5th switch be electrically connected between the second end of the energy-storage units and the output end, and be controlled in conducting with
Switch between being not turned on.The energy-storage units also have a first transistor, first current source and a first capacitor.This
One transistor is electrically connected to the third with a first end for being electrically connected first bias generator, a second end and one
The control terminal of switch；First current source is electrically connected between the second end of the first transistor and second bias generator, this second
The current potential of bias generator is less than the current potential of first bias generator；The first capacitor is electrically connected to the first end and the first transistor
Second end.
Preferably, the offset voltage compensator further includes a control unit, which is electrically connected the switch unit
First switch, third switch and the 5th switch, and operate in a storage mode and an elimination mode.When the control unit
When operating in the storage mode, the control unit control the first switch be conducting, the third switch be that conducting and the 5th open
It closes to be not turned on.When the control unit operates in the elimination mode, it is to be not turned on, be somebody's turn to do which, which controls the first switch,
Third switch for be not turned on and the 5th switch be connected.
The beneficial effects of the present invention are: it is identical to obtain one to replicate the offset voltage by the offset voltage compensator
The voltage compensation output voltage is prestored in the voltage that prestores of the offset voltage, and according to this, thus the operational amplifier can be eliminated
DC offset voltage.
Detailed description of the invention
Other features of the invention and effect will be clearly presented in the embodiment referring to attached drawing, in which:
Fig. 1 is a circuit diagram, illustrates that the present invention has the one of operational amplification circuit of direct current offset technology for eliminating
A first embodiment；
Fig. 2 is a circuit diagram, illustrates that the first embodiment operates in a buffer mode；
Fig. 3 is a circuit diagram, illustrates that the first embodiment operates in a storage mode；
Fig. 4 is a circuit diagram, illustrates that the first embodiment operates in an elimination mode；
Fig. 5 is a circuit diagram, illustrates that the present invention has the one of operational amplification circuit of direct current offset technology for eliminating
A second embodiment；
Fig. 6 is a circuit diagram, illustrates an alternate embodiment of the second embodiment；
Fig. 7 is a circuit diagram, illustrates that the second embodiment operates in a storage mode；
Fig. 8 is a circuit diagram, illustrates that the second embodiment operates in an elimination mode；
Fig. 9 is a circuit diagram, illustrates that the present invention has the one of operational amplification circuit of direct current offset technology for eliminating
A 3rd embodiment；
Figure 10 is a circuit diagram, illustrates an alternate embodiment of the 3rd embodiment.
Specific embodiment
Refering to fig. 1, the present invention has a first embodiment of the operational amplification circuit of direct current offset technology for eliminating, includes
One operational amplifier 1 and an offset voltage compensator 2.
The operational amplifier 1 include an inverting input terminal (-), one receive the of first input voltage vin 1
One non-inverting input (+), second non-inverting input (+) for receiving second input voltage vin 2 and one mention
For one be relevant to first, second input voltage vin 1, Vin2 output voltage Vout output end.Wherein, sheet first is real
Apply the crystal that the operational amplifier 1 used in example corresponds to first, second non-inverting input by designing its input stage
The breadth length ratio of pipe, and first, second input voltage vin 1, Vin2 is made to be added to obtain an input electricity according to respective weighted value
Vin is pressed, (but not limited to this) is illustrated for this sentences the weighted value of 1:3, then shown in Vin such as formula (1):
When being mismatched between the inverting input terminal and first, second non-inverting input, the inverting input terminal and this
One, an offset voltage (dc offset voltage) will be present in the common-mode voltage between the second non-inverting input.
The offset voltage compensator 2 is electrically connected to the inverting input terminal of the operational amplifier 1, first non-inverting input
Between end, second non-inverting input and the output end, and replicates the offset voltage and be identical to the offset voltage to obtain one
Prestore voltage, and voltage compensation output voltage Vout is prestored according to this.
The offset voltage compensator 2 includes 21, switch units 22 of an energy-storage units and a control unit 23.
The energy-storage units 21 have first end 211, one of an inverting input terminal for being electrically connected the operational amplifier 1
Second end 212 and a third end 213, prestore voltage for storing this.The energy-storage units 21 also have one and are electrically connected to this
First capacitor C1 between first end 211 and the second end 212 and one are electrically connected between the first end 211 and the third end 213
The second capacitor C2.Wherein, the capacitance of second capacitor C2 of the first embodiment is the 3 of the capacitance of first capacitor C1
Times.But the ratio of the capacitance is not limited thereto.
The switch unit 22 is electrically connected the energy-storage units 21 and is controlled in the control unit 23, makes the energy-storage units 21
212 suspension joint of second end is electrically connected first non-inverting input or the output end, and makes the third end 213 of the energy-storage units 21
Suspension joint is electrically connected second non-inverting input or the output end.The switch unit 22 has one and is electrically connected to the energy storage list
Between the first end 211 and the output end of member 21 and by first switch S1, the electricity for being controlled in conducting and switching between being not turned on
Between being connected between the third end 213 of the energy-storage units 21 and second non-inverting input and be controlled in conducting and being not turned on
The second switch S2 of switching, one be electrically connected between the second end 212 of the energy-storage units 21 and first non-inverting input
And the third end of the energy-storage units 21 is electrically connected to by the third switch S3 for being controlled in conducting and switching between being not turned on, one
The energy storage is electrically connected between 213 and the output end and by the 4th switch S4 for being controlled in conducting and switching between being not turned on and one
Between the second end 212 of unit 21 and the output end and by the 5th switch S5 for being controlled in conducting and switching between being not turned on.
The control unit 23 is electrically connected first to the 5th switch S1~S5 of the switch unit 22, and operates in one and delay
Punch die formula, a storage mode and an elimination mode.
Referring to Fig.2, the control unit 23 controls first switch S1 when the control unit 23 operates in the buffer mode
For conducting, second switch S2 be not turned on, the third switch S3 be not turned on, the 4th switch S4 for be not turned on and this
Five switch S5 are to be not turned on.Therefore, shown in output voltage Vout such as formula (2), wherein parameter Voff is the value of offset voltage.
Vout=Vin+Voff ... (2)
Refering to Fig. 3, when the control unit 23 operates in the storage mode, which controls first switch S1
It is conducting for conducting, second switch S2, third switch S3 is conducting, the 4th switch S4 to be not turned on and the 5th opens
Closing S5 is to be not turned on.Therefore, the charge Q 2 for being stored in the charge Q 1 of first capacitor C1 and being stored in second capacitor C2 is distinguished
As shown in formula (3), (4):
Q1=C1 × [(Vin+Voff)-Vin1] ... (3)
Q2=C2 × [(Vin+Voff)-Vin2] ... (4)
Refering to Fig. 4, when the control unit 23 operates in the elimination mode, which controls first switch S1
To be not turned on, second switch S2 be not turned on, the third switch S3 to be not turned on, the 4th switch S4 be conducting and this
Five switch S5 are conducting.Therefore, first capacitor C1 and the second capacitor C2 is in status of electrically connecting in parallel and a corresponding end
Shown in voltage Vtotal such as formula (5):
Then the output end generates shown in a new output voltage Vout_new such as formula (6):
Vout_new=Vin+Voff-Vtotal ... (6)
Convolution (3)~formula (5), it is available
Convolution (1), formula (6) and formula (7), it is available
That is, it is defeated that the output voltage Vout_new of the output end can be identical to this after completing the elimination mode
Enter voltage Vin without being influenced by offset voltage Voff.
Refering to Fig. 5, the present invention has a second embodiment of the operational amplification circuit of direct current offset technology for eliminating, substantially
Be identical to the first embodiment, different places is: the energy-storage units 21 of the second embodiment also have one first crystalline substance
Body pipe M1, the first current source IS1, a second transistor M2 and a second current source IS2.The second embodiment
The control unit 23 be electrically connected the switch unit 22 first to the 5th switch S1~S5 and operate in a storage mode and
One elimination mode.
The first transistor M1 has first end, a second end and one of one the first bias generator VDD of an electrical connection
A control terminal for being electrically connected to third switch S3.First current source IS1 be electrically connected the second end of the first transistor M1 with
Between one the second bias generator VSS, the current potential of second bias generator VSS is less than the current potential of first bias generator VDD.Second crystal
There is pipe M2 one to be electrically connected the first end of first bias generator VDD, a second end and one are electrically connected to the second switch
The control terminal of S2.Second current source IS2 is electrically connected between the second end of second transistor M2 and second bias generator VSS.
Again in the second embodiment, the first transistor M1 and second transistor M2 are respectively a N-type metal oxidation
Object semiconductor transistor (NMOS), and its first end is drain electrode, its second end is source electrode and its control terminal is grid.And this
One, second transistor M1, M2 forms first, second source follower with the first, second current source IS1, the IS2 respectively
(Source Follower).It is respectively a N-type metal oxidation that the second embodiment, which is with first, second transistor M1, M2,
It is illustrated for object semiconductor transistor (NMOS), it should be noted that first, second transistor M1, M2 can also be such as figures
It is a P type metal oxide semiconductor transistor (PMOS) shown in 6.
Refering to Fig. 7, when the control unit 23 operates in the storage mode, which controls first switch S1
It is conducting for conducting, second switch S2, third switch S3 is conducting, the 4th switch S4 to be not turned on and the 5th opens
Closing S5 is to be not turned on.Therefore, shown in output voltage Vout such as formula (9):
Vout=Vin+Voff ... (9)
Refering to Fig. 8, when the control unit 23 operates in the elimination mode, which controls first switch S1
To be not turned on, second switch S2 be not turned on, the third switch S3 to be not turned on, the 4th switch S4 be conducting and this
Five switch S5 are conducting.The grid voltage for defining first, second transistor M1, M2 enters the elimination mode from the storage mode
Generated voltage increment is respectively Δ Vg1 ,-Δ Vg2, then output voltage Vout_new such as formula new corresponding to the output end
(10) shown in:
Vout_new=Vin1+ Δ Vg1=Vin2- Δ Vg2 ... (10)
And the source voltage increment of first, second transistor M1, M2 are respectively as shown in formula (11), (12):
Δ Vs1=Δ Vg1 × Gsf1 ... (11)
Δ Vs2=- Δ Vg2 × Gsf2 ... (12)
Wherein, Gsf1, Gsf2 are respectively the voltage gain between the source electrode and grid of first, second source follower.By
There is no charge and discharge path when the inverting input terminal of the operational amplifier 1 is in the elimination mode, therefore in charge conservation and such as
Shown in formula (13):
C1 × Δ Vg1 × Gsf1-C2 × Δ Vg2 × Gsf2=0 ... (13)
Furthermore since the voltage gain between the source electrode and grid of the source follower is approximately equal to 1, formula (13) can quilt
Shown in approximation such as formula (14):
C1 × Δ Vg1=C2 × Δ Vg2 ... (14)
Convolution (1), formula (10) and formula (14), it is available
That is, it is defeated that the output voltage Vout_new of the output end can be identical to this after completing the elimination mode
Enter voltage Vin without being influenced by offset voltage Voff.
It is noted that compared to the first embodiment, since the second embodiment is respectively at first, second capacitor
First, second source follower is more electrically connected between C1, C2 and the third, second switch S3, S2, so that the second embodiment is grasped
When making in the storage mode end voltage of first, second capacitor C1, C2 compared to the first embodiment increase separately Vgs1,
Vgs2, wherein Vgs1, Vgs2 are respectively the gate-source voltage of first, second transistor M1, M2.The end voltage of the capacitor increases
Amount Vgs1, Vgs2 is comparable to second input voltage vin 2 especially suitable for first input voltage vin 1, and this first, second
Capacitor C1, C2 are the operating condition of MOS capacitor (MOS-cap).It further illustrates, when this is first, second defeated
Enter voltage Vin1, Vin2 it is close when, the end voltage of first, second capacitor C1, C2 are respectively as shown in formula (16), (17):
VC1=(Vin+Voff)-(Vin1-Vgs1) ≈ Voff+Vgs1 ... (16)
VC2=(Vin+Voff)-(Vin2-Vgs2) ≈ Voff+Vgs2 ... (17)
To make MOS capacitor energy normal operation with sufficient end voltage, and utilize metal
There is oxide semiconductor capacitors the biggish characteristic of unit area capacitance to reduce chip area.
Refering to Fig. 9 and Figure 10, there is the present invention third of the operational amplification circuit of direct current offset technology for eliminating to implement
Example, is operationally approximately identical to the second embodiment, different places is: the operational amplifier 1 of the 3rd embodiment wraps
Include first non-inverting input, the energy-storage units 21 have a first capacitor C1, a first transistor M1 and one
First current source IS1, and the switch unit 22 has a first switch S1, a third switch S3 and one the 5th switch
S5.The control unit 23 is electrically connected the first, third of the switch unit 22 and the 5th switch S1, S3, S5 and operates in one
Storage mode and an elimination mode.
Via above explanation, above-described embodiment is had the advantage that
One, the offset voltage is replicated by the offset voltage compensator 2 and is identical to the pre- of the offset voltage to obtain one
Voltage is deposited, and voltage compensation output voltage Vout is prestored according to this, thus the direct current offset electricity of the operational amplifier 1 can be eliminated
Pressure.
Two, it is controlled by the switch of the switch unit 22 by the control unit 23, so that the energy-storage units 21 be made to exist
Voltage is prestored to store this using its capacitor when the storage mode, and compensates output voltage Vout in the elimination mode and disappears
Except the DC offset voltage of the operational amplifier 1.
Three, the output is determined by the capacitance ratio of both first, second capacitor C1, C2 of the energy-storage units 21
The voltage value of voltage Vout can promote the stability of the voltage value.It further illustrates, since the capacitor is passive device, In
It can be better than active member in the performance of process variation, and since two capacitors in the same chip are whether in processing procedure or temperature
The relationship mutually interlocked is suffered from degree variation, so that ratio between the two is less susceptible to the shadow of processing procedure or temperature change
It rings.Also therefore, it is decided by the output voltage Vout of the capacitance ratio of both first, second capacitor C1, C2 similarly more
It is not influenced by processing procedure or temperature change.
Four, by output voltage Vout by the capacitance ratio of both first, second capacitor C1, C2 determine to
Conductance (gm) variation that not will receive 1 input stage of operational amplifier is influenced, therefore even if operates in first, second input
Under conditions of voltage Vin1, Vin2 have larger pressure difference between the two, remain to keep output voltage Vout unaffected and stablize
Ground is maintained at design value.
Five, formed with the first, second current source IS1, the IS2 respectively by first, second transistor M1, M2 this
One, the second source follower is end voltage increment Vgs1, Vgs2 provided by first, second capacitor C1, C2, can make this
One, second capacitor C1, C2 implements to reduce chip face in turn with the biggish MOS capacitor of unit area capacitance
Product.
In conclusion so the purpose of the present invention can be reached really.
Claims (7)
1. a kind of operational amplification circuit with direct current offset technology for eliminating, includes: an operational amplifier and an electrical connection
In the offset voltage compensator of the operational amplifier, which is characterized in that:
The operational amplifier includes first non-inverting input of one inverting input terminal, a reception the first input voltage
End, second non-inverting input for receiving second input voltage and one provide one be relevant to this first, second
The output end of the output voltage of input voltage, when being mismatched between the inverting input terminal and first, second non-inverting input,
An offset voltage will be present in common-mode voltage between the inverting input terminal and first, second non-inverting input；And
The offset voltage compensator is electrically connected to the inverting input terminal of the operational amplifier, first non-inverting input, is somebody's turn to do
Between second non-inverting input and the output end, and replicates the offset voltage and be identical to prestoring for the offset voltage to obtain one
Voltage, and the voltage compensation output voltage is prestored according to this, which includes
One energy-storage units, the first end for the inverting input terminal for being electrically connected the operational amplifier with one and one second
End, prestore voltage for storing this, the energy-storage units also have a third end, one be electrically connected to the first end and this second
First capacitor and second capacitor being electrically connected between the first end and the third end between end, and
One switch unit is electrically connected the energy-storage units, and is made the second end suspension joint of the energy-storage units, electrical connection should by control
First non-inverting input or the output end, and make that the third end suspension joint of the energy-storage units, to be electrically connected this second noninverting defeated
Entering end or the output end, the switch unit has
One first switch, is electrically connected between the first end of the energy-storage units and the output end, and be controlled in conducting with not
Switch between conducting,
One second switch is electrically connected between the third end of the energy-storage units and second non-inverting input, and is controlled
Switch between being connected and being not turned on,
One third switch, is electrically connected between the second end of the energy-storage units and first non-inverting input, and controlled
Switch between being connected and being not turned on,
One the 4th switch, be electrically connected between the third end of the energy-storage units and the output end, and be controlled in conducting with not
Switch between conducting, and
One the 5th switch, be electrically connected between the second end of the energy-storage units and the output end, and be controlled in conducting with not
Switch between conducting.
2. the operational amplification circuit according to claim 1 with direct current offset technology for eliminating, the operational amplification circuit
It is characterized in that: the offset voltage compensator further include:
One control unit, is electrically connected the first to the 5th switch of the switch unit, and operates in a buffer mode, a storage
Mode and an elimination mode are deposited,
When the control unit operates in the buffer mode, which controls the first switch as conducting, the second switch
To be not turned on, third switch to be not turned on, the 4th switch is is not turned on and the 5th switch is is not turned on；
When the control unit operates in the storage mode, which controls the first switch as conducting, the second switch
It is conducting, the 4th switch to be not turned on and the 5th switch is is not turned on for conducting, third switch；And
When the control unit operates in the elimination mode, the control unit control the first switch be not turned on, this second is opened
It closes to be not turned on, the third switchs to be not turned on, the 4th switch is conducting and the 5th switch is conducting.
3. the operational amplification circuit according to claim 1 with direct current offset technology for eliminating, the operational amplification circuit
Be characterized in that: the energy-storage units also include
One the first transistor is electrically connected with a first end for being electrically connected first bias generator, a second end and one
It is connected to the control terminal of third switch；
One the first current source is electrically connected between the second end of the first transistor and second bias generator, second bias generator
Current potential be less than first bias generator current potential；
There is one second transistor one to be electrically connected the first end of first bias generator, a second end and an electrical connection
In the control terminal of the second switch；And
One the second current source is electrically connected between the second end of the second transistor and second bias generator.
4. the operational amplification circuit according to claim 3 with direct current offset technology for eliminating, the operational amplification circuit
It is characterized in that: the offset voltage compensator further include:
One control unit, is electrically connected the first to the 5th switch of the switch unit, and operates in a storage mode and one
Elimination mode,
When the control unit operates in the storage mode, which controls the first switch as conducting, the second switch
It is conducting, the 4th switch to be not turned on and the 5th switch is is not turned on for conducting, third switch；And
When the control unit operates in the elimination mode, the control unit control the first switch be not turned on, this second is opened
It closes to be not turned on, the third switchs to be not turned on, the 4th switch is conducting and the 5th switch is conducting.
5. a kind of operational amplification circuit with direct current offset technology for eliminating, includes: an operational amplifier and an electrical connection
In the offset voltage compensator of the operational amplifier, which is characterized in that:
The operational amplifier includes first non-inverting input of one inverting input terminal, a reception the first input voltage
End and one provide the output end for the output voltage that one is relevant to first input voltage, when the inverting input terminal and this
When mismatching between one non-inverting input, the common-mode voltage between the inverting input terminal and first non-inverting input will be present one
A offset voltage；And
The offset voltage compensator is electrically connected to the inverting input terminal of the operational amplifier, first non-inverting input and should
Between output end, and replicates the offset voltage and be identical to the voltage that prestores of the offset voltage to obtain one, and electricity is prestored according to this
Pressure compensates the output voltage, which includes
One energy-storage units, the first end for the inverting input terminal for being electrically connected the operational amplifier with one and one second
End, prestores voltage for storing this, and
One switch unit is electrically connected the energy-storage units, and is made the second end suspension joint of the energy-storage units, electrical connection should by control
First non-inverting input or the output end, the switch unit have
One first switch, is electrically connected between the first end of the energy-storage units and the output end, and be controlled in conducting with not
Switch between conducting,
One third switch, is electrically connected between the second end of the energy-storage units and first non-inverting input, and controlled
Switch between being connected and being not turned on, and
One the 5th switch, be electrically connected between the second end of the energy-storage units and the output end, and be controlled in conducting with not
Switch between conducting.
6. the operational amplification circuit according to claim 5 with direct current offset technology for eliminating, the operational amplification circuit
Be characterized in that: the energy-storage units also include
One the first transistor is electrically connected with a first end for being electrically connected first bias generator, a second end and one
It is connected to the control terminal of third switch,
One the first current source is electrically connected between the second end of the first transistor and second bias generator, second bias generator
Current potential be less than first bias generator current potential, and
One first capacitor, is electrically connected to the second end of the first end Yu the first transistor.
7. the operational amplification circuit according to claim 6 with direct current offset technology for eliminating, the operational amplification circuit
It is characterized in that: the offset voltage compensator further include:
One control unit, is electrically connected first switch, third switch and the 5th switch of the switch unit, and operates in a storage
Mode and an elimination mode are deposited,
When the control unit operates in the storage mode, which controls the first switch as conducting, third switch
It is to be not turned on for conducting and the 5th switch；And
When the control unit operates in the elimination mode, the control unit control the first switch be not turned on, the third is opened
Close for be not turned on and the 5th switch be connected.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510585247.9A CN106533370B (en) | 2015-09-15 | 2015-09-15 | Operational amplification circuit with direct current offset technology for eliminating |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510585247.9A CN106533370B (en) | 2015-09-15 | 2015-09-15 | Operational amplification circuit with direct current offset technology for eliminating |
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| Publication Number | Publication Date |
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| CN106533370A CN106533370A (en) | 2017-03-22 |
| CN106533370B true CN106533370B (en) | 2019-12-03 |
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| Application Number | Title | Priority Date | Filing Date |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6946986B2 (en) * | 2002-12-19 | 2005-09-20 | International Business Machines Corporation | Differential sampling circuit for generating a differential input signal DC offset |
| CN101059940A (en) * | 2006-04-18 | 2007-10-24 | 凌阳科技股份有限公司 | Operation amplifier driving circuit for eliminating the operational amplifier offset voltage |
| US8102203B2 (en) * | 2007-09-25 | 2012-01-24 | Oracle America, Inc. | Offset cancellation in a capacitively coupled amplifier |
| US8330536B1 (en) * | 2010-12-20 | 2012-12-11 | Xilinx, Inc. | Differential reference interface with low noise offset cancellation |
-
2015
- 2015-09-15 CN CN201510585247.9A patent/CN106533370B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6946986B2 (en) * | 2002-12-19 | 2005-09-20 | International Business Machines Corporation | Differential sampling circuit for generating a differential input signal DC offset |
| CN101059940A (en) * | 2006-04-18 | 2007-10-24 | 凌阳科技股份有限公司 | Operation amplifier driving circuit for eliminating the operational amplifier offset voltage |
| US8102203B2 (en) * | 2007-09-25 | 2012-01-24 | Oracle America, Inc. | Offset cancellation in a capacitively coupled amplifier |
| US8330536B1 (en) * | 2010-12-20 | 2012-12-11 | Xilinx, Inc. | Differential reference interface with low noise offset cancellation |
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| Publication number | Publication date |
|---|---|
| CN106533370A (en) | 2017-03-22 |
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