CN106526923A - Array substrate, testing method thereof and display device - Google Patents
Array substrate, testing method thereof and display device Download PDFInfo
- Publication number
- CN106526923A CN106526923A CN201710022521.0A CN201710022521A CN106526923A CN 106526923 A CN106526923 A CN 106526923A CN 201710022521 A CN201710022521 A CN 201710022521A CN 106526923 A CN106526923 A CN 106526923A
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- driving chip
- array base
- base palte
- outlet line
- test
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- 238000012360 testing method Methods 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 title abstract description 9
- 238000005259 measurement Methods 0.000 claims abstract description 45
- 230000005540 biological transmission Effects 0.000 claims abstract description 36
- 238000010998 test method Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 4
- 230000002035 prolonged effect Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 2
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
Abstract
The embodiment of the invention discloses an array substrate, a testing method thereof and a display device. The array substrate comprises a driving chip and at least one pixel unit. Each pixel unit comprises an output circuit. The first end of the output circuit is connected to the output end of the driving chip, and a testing circuit same as the output circuit is arranged beyond the effective display area of the array substrate. The first end of the testing circuit is connected to the second end of the output circuit, and the second end of the testing circuit is connected to the testing end of the driving chip. According to the array substrate and the testing method and display device thereof, when the testing circuit same as the general output circuit is arranged on the array substrate of a display panel, the output circuit is connected with the testing circuit in series, accordingly, the transmission delay measurement between the two ends of the output circuit is transformed into the transmission delay measurement between the connection end of the output circuit and the driving chip and the connection end of the testing circuit and the driving chip, and the problem that a signal of the end, far away from the driving chip, of the output circuit is difficult to actually measure is solved.
Description
Technical field
The present invention relates to display technology field, particularly relates to a kind of array base palte, its method of testing and display device.
Background technology
In the design and manufacture process of the array base palte of liquid crystal display, the AC impedance of outlet line on array base palte
Excessive problem is there may be, is caused and delay is produced by the signal of outlet line.As shown in figure 1, for the output of array base palte
The schematic diagram of the excessive signal delay for causing of circuit AC impedance, circuit initial endpoint signal are square wave, and line end signal is because of face
Plate AC impedance is excessive, generates obvious distortion (such as T in figuredIt is shown).This results in the driving chip of LCDs normal
Under rule driving force, it is impossible to driven liquid crystal panel, the display effect of liquid crystal display is directly affected.
But in a practical situation, outlet line end is because of reasons such as encapsulation, it is difficult to is directly connected to by instrument, is caused defeated
Go out circuit signal delay cannot direct measurement, and then the driving force of driving chip cannot be adjusted, affect liquid crystal display
The display effect of device.
The content of the invention
In view of this, it is an object of the invention to propose a kind of array base palte, its method of testing and display device, to reality
The signal delay of array base palte outlet line is detected now.
Based on above-mentioned purpose, the embodiment of the present invention provides a kind of array base palte, including driving chip and at least one pixel
Unit, the pixel cell include outlet line, and the first end of the outlet line is connected to the output end of the driving chip,
The array base palte effective display area is overseas, arranges and the outlet line identical measurement circuit；The of the measurement circuit
One end is connected to the second end of the outlet line, and the second end of the measurement circuit is connected to the test of the driving chip
End.
Optionally, it is connected by switch element between the second end of the outlet line and the first end of the measurement circuit
Connect.
Optionally, the switch element includes triode or FET.
Optionally, it is provided between the output end and test lead of the driving chip and examines for the delay for detecting transmission delay
Survey unit.
Optionally, the delay detector unit includes 2 or more than 2 d type flip flops being sequentially connected with, and touches with the D
Send out device connect one to one with door；The clock signal terminal of first d type flip flop is connected to known clock signal；Trigger in front D
The data signal end and inverse output terminal of device is connected to the adjacent clock signal terminal in rear d type flip flop；The reset of whole d type flip flops
End is connected to the output end of the driving chip；The output end of d type flip flop is respectively connecting to the first end with door, all with door
Second end is connected to the test lead of the driving chip.
Based on identical purpose, the embodiment of the present invention provides a kind of method of testing of array base palte, and the array base palte includes
Driving chip and at least one pixel cell, the pixel cell include outlet line, the first end connection of the outlet line
To the output end of the driving chip, it is characterised in that the array base palte effective display area is overseas, arrange and the output line
Road identical measurement circuit；The first end of the measurement circuit is connected to the second end of the outlet line, the measurement circuit
The second end be connected to the test lead of the driving chip, the method for testing includes：
By testing the transmission delay between the driving chip output end and test lead, the biography of the array base palte is calculated
Defeated delay.
Optionally, it is connected by switch element between the second end of the outlet line and the first end of the measurement circuit
Connect；The method of testing includes：
When the switch element is connected, the transmission delay of the array base palte is tested.
Optionally, the transmission delay between the test driving chip output end and test lead, specifically includes：
Apply the first test voltage to the driving chip output end, and start timing；
Detect the driving chip test terminal voltage value；
When driving chip test terminal voltage value reaches the second test voltage, stop timing and by duration obtained by timing
As the transmission delay between the driving chip output end and test lead.
Optionally, the transmission delay for calculating the array base palte, specifically includes：
By the transmission delay between the driving chip output end and test lead divided by two biographies for obtaining the array base palte
Defeated delay.
Based on identical purpose, the embodiment of the present invention provides a kind of display device, the battle array described in above-mentioned any one embodiment
Row substrate.
From the above it can be seen that array base palte provided in an embodiment of the present invention, its method of testing and display device are logical
Cross on the array base palte of display floater, one and common output circuit identical measurement circuit are set, by outlet line and survey
Examination circuit series connection, so as to by the measurement of outlet line two ends transmission delay be converted into outlet line and measurement circuit each with driving
The measurement of transmission delay between chip connection end, solves outlet line and is difficult to asking for actual measurement away from driving chip end signal
Topic.
Description of the drawings
Fig. 1 is the schematic diagram of the excessive signal delay for causing of outlet line AC impedance of array base palte in prior art；
The structural representation of the array base palte that Fig. 2 is provided for first embodiment of the invention；
The structural representation of the array base palte that Fig. 3 is provided for second embodiment of the invention；
The structural representation of the array base palte that Fig. 4 is provided for third embodiment of the invention；
Fig. 5 is that a kind of circuit structure of optional embodiment of delay detector unit in third embodiment of the invention is illustrated
Figure.
Specific embodiment
To make the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
It should be noted that the statement of all uses " first " and " second " is for differentiation two in the embodiment of the present invention
The parameter of the entity or non-equal of individual same names non-equal, it is seen that the convenience of " first " " second " only for statement, should not
The restriction to the embodiment of the present invention is interpreted as, subsequent embodiment is no longer illustrated one by one to this.
The structural representation of the array base palte that Fig. 2 is provided for first embodiment of the invention.As illustrated, the of the present invention
In one embodiment, there is provided a kind of array base palte 10, including driving chip 20 and at least one pixel cell 12, the pixel cell
12 include outlet line 30, and the first end of the outlet line 30 is connected to the output end 21 of the driving chip 20, the battle array
Outside the effective display area domain 11 of row substrate 10, arrange and 30 identical measurement circuit 40 of the outlet line；The measurement circuit
40 first end is connected to the second end of the outlet line 30, and the second end of the measurement circuit 40 is connected to the driving core
The test lead 22 of piece 20.
The pixel cell 12 is provided with the effective display area domain 11, for driving liquid crystal to produce display effect.And
Liquid crystal will not be then set the effective display area domain 11 is outer, this part is usually located at array base palte edge, therefore the present embodiment
Selection arranges the measurement circuit 40 herein, to eliminate the impact produced to display effect.
The embodiment of the present invention based on a general thought be：On the array base palte of liquid crystal display, all of output
The friendship impedance of circuit is typically in same level under normal circumstances, therefore is prolonged by measuring the transmission of a wherein outlet line
Late, the AC impedance for learning the outlet line can be calculated, so as to learn overall AC impedance and the transmission of the array base palte
Postpone.Based on this thinking, the array base palte of the present embodiment need to measure when measuring, only output end 21 and test lead 22 it
Between transmission delay, and the transmission delay (because outlet line 30 is identical with measurement circuit 40, therefore is possessed into identical divided by 2
Transmission delay, and the two can be considered series relationship, thus total transmission postpone for the two each from transmission delay sum), you can
The overall transfer for obtaining array base palte postpones.
In the present embodiment and other alternative embodiments, the quantity of the measurement circuit can also be 2 or more than 2,
All the measurement circuit is connected with each other successively from beginning to end with the outlet line, positioned at the end of the last outlet line
(the second end of the measurement circuit 40 being equal in the present embodiment) is connected to the test lead of driving chip, after a measurement according to test
The quantity of circuit calculates the transmission delay of outlet line.By the quantity for increasing measurement circuit, can use up in measurement and calculating
The side-looking error that cas fortuit is caused may be eliminated, measuring accuracy is improved.
In the present embodiment and other alternative embodiments, the outlet line 30 can be source class (Source levels) output line
Road, or grid (Gate levels) outlet line, the corresponding driving chip 20 are respectively source class driving chip or grid
Driving chip；And the measurement circuit 40 also should be identical with the set-up mode of circuit to be measured.
As fully visible, the present embodiment is by the array base palte of display floater, arranging one with common output circuit phase
Same measurement circuit, outlet line is connected with measurement circuit, so as to the measurement of outlet line two ends transmission delay is converted into
Outlet line and measurement circuit each between driving chip connection end transmission delay measurement, solve outlet line away from drive
Dynamic chip end signal is difficult to the problem of actual measurement.
The structural representation of the array base palte that Fig. 3 is provided for second embodiment of the invention.As illustrated, in second embodiment
In, it is connected by switch element 50 between the second end of the outlet line 30 and the first end of the measurement circuit 40.
When the switch element 50 is breaking, the outlet line 30 does not constitute loop with the measurement circuit 40, therefore surveys
Examination circuit 40 will not have any impact to normal use of outlet line 30；It is when the switch element 50 is connected, described defeated
Go out circuit 30 and loop is constituted with the measurement circuit 40, the transmission delay of the array base palte can be tested.It can be seen that, lead to
Cross setting switch element 50 so that the state of array base palte can be switched between normal operating condition and test mode,
The normal use of array base palte 10 will not be affected because increasing measurement circuit 40.
In some optional embodiments of the present embodiment, the switch element 50 includes triode or FET.
It should be noted that other disclosure satisfy that on array base palte 10 arrange condition, while control circuit break-make effect can be reached
Electrical equipment or circuit structure, fall within the optional embodiment of the present embodiment breaker in middle unit 50.
The structural representation of the array base palte that Fig. 4 is provided for third embodiment of the invention.As illustrated, in the present embodiment
In, it is provided between the output end 21 and test lead 22 of the driving chip 20 for detecting the delay detector unit of transmission delay
60。
When test is performed, the output end 21 of the driving chip 20 exports the first test voltage, and the delay detection is single
Unit 60 is triggered by first test voltage, starts to perform timing, now due to there is transmission delay, therefore the driving chip
20 test lead 22 does not have voltage and changes；When the magnitude of voltage of the output end 21 reaches (be more than or equal to) the second test voltage
When, the delay detector unit 60 is triggered again, stops timing.Read the timing result for postponing detector unit 60
Obtain the transmission delay between 10 output end 21 of the driving chip and test lead 22, namely the outlet line 30 and the survey
The total transmission of examination circuit 40 postpones.
Fig. 5 is that a kind of circuit structure of optional embodiment of delay detector unit in third embodiment of the invention is illustrated
Figure.As illustrated, in some optional embodiments of the present embodiment, the delay detector unit include 2 or more than 2 it is suitable
D type flip flop (the D in Fig. 5 of secondary connection1-Dn), and connect one to one with the d type flip flop with door；First d type flip flop
Clock signal terminal is connected to known clock signal；The data signal end and inverse output terminal of front d type flip flop be connected to it is adjacent
The clock signal terminal of d type flip flop afterwards；The reset terminal of whole d type flip flops is connected to the output end of the driving chip；D type flip flop
Output end is respectively connecting to the first end with door, is all connected to the test lead of the driving chip with the second end of door.It is above-mentioned
In circuit structure, other ports of each electrical equipment are placed in normal operating conditions.
By the combination of setting multigroup " d type flip flop+and door " in above-mentioned embodiment, the binary system of a multidigit is established
Counter.Output end Q of first d type flip flop can occur saltus step when the rising edge of the known clock signal arrives；In rear D
Output end Q of trigger can occur saltus step, so as to set up more than one when it is " 0 " that previous d type flip flop is exported by " 1 " saltus step
The binary counter of position, the lowest order of count results is first and door (D1) output, highest order is last and door
(Dn) output.After high potential (the first test voltage) in driving chip output end, the counter of the present embodiment starts, until
Driving chip test lead equally reaches the moment of high potential (the second test voltage), reading occurs with the output end of door, by note
Now reading the decimal system are recorded, and simple computation are carried out further according to the known clock signal period, you can obtain the output
Circuit connect with measurement circuit after total transmission postpone duration.
The embodiment of the present invention also provides a kind of display device, and which includes the array base palte described in above-mentioned any embodiment,
Certainly also include such as other known structures such as color membrane substrates, will not be described in detail herein.
Display device in the embodiment of the present invention is liquid crystal indicator, can also be Electronic Paper, mobile phone, panel computer,
Any product with display function such as television set, display, notebook computer, DPF, navigator or part.
Those of ordinary skill in the art should be understood：The discussion of any of the above embodiment is exemplary only, not
It is intended to imply that the scope of the present disclosure (including claim) is limited to these examples；Under the thinking of the present invention, above example
Or can also be combined between the technical characteristic in different embodiments, step can be realized with random order, and is existed such as
Many other changes of the different aspect of the upper described present invention, for simple and clear their no offers in details.
In addition, to simplify explanation and discussing, and in order to obscure the invention, can in the accompanying drawing for being provided
To illustrate or can not illustrate that the known power ground with integrated circuit (IC) chip and other parts is connected.Furthermore, it is possible to
Device is shown in block diagram form, to avoid obscuring the invention, and this have also contemplated that following facts, i.e., with regard to this
The details of the embodiment of a little block diagram arrangements be depend highly on the platform that will implement the present invention (that is, these details should
It is completely in the range of the understanding of those skilled in the art).Elaborating detail (for example, circuit) to describe the present invention's
In the case of exemplary embodiment, it will be apparent to those skilled in the art that these details can not there is no
In the case of or implement the present invention in the case that these details are changed.Therefore, these descriptions are considered as explanation
It is property rather than restricted.
Embodiments of the invention be intended to fall within the broad range of claims it is all such replace,
Modification and modification.Therefore, all any omissions within the spirit and principles in the present invention, made, modification, equivalent, improvement
Deng should be included within the scope of the present invention.
Claims (10)
1. a kind of array base palte, including driving chip and at least one pixel cell, the pixel cell include outlet line, institute
The first end for stating outlet line is connected to the output end of the driving chip, it is characterised in that the array base palte effectively shows
Outside region, arrange and the outlet line identical measurement circuit；The first end of the measurement circuit is connected to the output line
Second end on road, the second end of the measurement circuit are connected to the test lead of the driving chip.
2. array base palte according to claim 1, it is characterised in that the second end of the outlet line and the p-wire
It is connected by switch element between the first end on road.
3. array base palte according to claim 2, it is characterised in that the switch element includes triode or field-effect
Pipe.
4. array base palte according to claim 1, it is characterised in that between the output end and test lead of the driving chip
It is provided with for detecting the delay detector unit of transmission delay.
5. array base palte according to claim 4, it is characterised in that the delay detector unit includes 2 or more than 2
The d type flip flop being sequentially connected with, and connect one to one with the d type flip flop with door；The clock signal terminal of first d type flip flop
It is connected to known clock signal；It is connected in the data signal end and inverse output terminal of front d type flip flop adjacent in rear d type flip flop
Clock signal terminal；The reset terminal of whole d type flip flops is connected to the output end of the driving chip；The output end difference of d type flip flop
The first end with door is connected to, and all the test lead of the driving chip is connected to the second end of door.
6. a kind of method of testing of array base palte, the array base palte includes driving chip and at least one pixel cell, described
Pixel cell includes outlet line, and the first end of the outlet line is connected to the output end of the driving chip, and its feature exists
In the array base palte effective display area is overseas, arranges and the outlet line identical measurement circuit；The measurement circuit
First end is connected to the second end of the outlet line, and the second end of the measurement circuit is connected to the test of the driving chip
End, the method for testing include：
By testing the transmission delay between the driving chip output end and test lead, the transmission for calculating the array base palte is prolonged
Late.
7. method of testing according to claim 6, it is characterised in that the second end of the outlet line and the p-wire
It is connected by switch element between the first end on road；The method of testing includes：
When the switch element is connected, the transmission delay of the array base palte is tested.
8. method of testing according to claim 6, it is characterised in that the test driving chip output end and test
Transmission delay between end, specifically includes：
Apply the first test voltage to the driving chip output end, and start timing；
Detect the driving chip test terminal voltage value；
When the driving chip test terminal voltage value reach the second test voltage when, stop timing and using duration obtained by timing as
Transmission delay between the driving chip output end and test lead.
9. the method for testing according to claim 6-8 any one, it is characterised in that the calculating array base palte
Transmission delay, specifically includes：
Transmission delay between the driving chip output end and test lead is prolonged divided by two transmission for obtaining the array base palte
Late.
10. a kind of display device, it is characterised in that including the array base palte described in claim 1-5 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710022521.0A CN106526923B (en) | 2017-01-12 | 2017-01-12 | Array substrate, its test method and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710022521.0A CN106526923B (en) | 2017-01-12 | 2017-01-12 | Array substrate, its test method and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106526923A true CN106526923A (en) | 2017-03-22 |
| CN106526923B CN106526923B (en) | 2019-04-23 |
Family
ID=58335532
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710022521.0A Expired - Fee Related CN106526923B (en) | 2017-01-12 | 2017-01-12 | Array substrate, its test method and display device |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068027A (en) * | 2017-05-27 | 2017-08-18 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, liquid crystal display panel detecting system and method |
| WO2020107590A1 (en) * | 2018-11-30 | 2020-06-04 | 惠科股份有限公司 | Mischarging detection method, mischarging detection apparatus, and display apparatus |
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| CN1482588A (en) * | 2002-07-12 | 2004-03-17 | ��֥������ʾ��������˾ | Display device |
| CN1497512A (en) * | 2002-09-27 | 2004-05-19 | ������������ʽ���� | Signal transmission circuit and display equipment |
| CN1577465A (en) * | 2003-07-24 | 2005-02-09 | 精工爱普生株式会社 | Display driver, electrooptical device and driving method |
| CN106205443A (en) * | 2016-09-22 | 2016-12-07 | 合肥京东方光电科技有限公司 | Testing circuit and method of work, drive circuit |
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2017
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|---|---|---|---|---|
| US20020070750A1 (en) * | 2000-12-07 | 2002-06-13 | Seiko Epson Corporation | Test method of electro-optical device, test circuit of electro-optical device, electro-optical device, and electronic equipment |
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| CN1497512A (en) * | 2002-09-27 | 2004-05-19 | ������������ʽ���� | Signal transmission circuit and display equipment |
| CN1577465A (en) * | 2003-07-24 | 2005-02-09 | 精工爱普生株式会社 | Display driver, electrooptical device and driving method |
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Cited By (3)
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| CN107068027A (en) * | 2017-05-27 | 2017-08-18 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, liquid crystal display panel detecting system and method |
| WO2020107590A1 (en) * | 2018-11-30 | 2020-06-04 | 惠科股份有限公司 | Mischarging detection method, mischarging detection apparatus, and display apparatus |
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| Publication number | Publication date |
|---|---|
| CN106526923B (en) | 2019-04-23 |
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