CN106505053A - Semiconductor structure and method for fabricating the same - Google Patents
Semiconductor structure and method for fabricating the same Download PDFInfo
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- CN106505053A CN106505053A CN201510600837.4A CN201510600837A CN106505053A CN 106505053 A CN106505053 A CN 106505053A CN 201510600837 A CN201510600837 A CN 201510600837A CN 106505053 A CN106505053 A CN 106505053A
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- dielectric layer
- layer
- electric connection
- semiconductor structure
- block
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title description 8
- 238000002161 passivation Methods 0.000 claims abstract description 57
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 238000002360 preparation method Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 14
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000004642 Polyimide Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 10
- 238000004528 spin coating Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XLTRGZZLGXNXGD-UHFFFAOYSA-N benzene;1h-pyrazole Chemical compound C=1C=NNC=1.C1=CC=CC=C1 XLTRGZZLGXNXGD-UHFFFAOYSA-N 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005272 metallurgy Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- PJJRJASJDRRJOW-UHFFFAOYSA-N benzene;cyclobutane Chemical compound C1CCC1.C1=CC=CC=C1 PJJRJASJDRRJOW-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
- H01L2224/02125—Reinforcing structures
- H01L2224/02126—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
The invention provides a semiconductor structure and a manufacturing method thereof, which comprises the steps of providing a chip comprising a plurality of electric connecting pads and a passivation layer, wherein the passivation layer is provided with a plurality of passivation layer openings to expose the electric connecting pads; forming a first dielectric layer on the passivation layer, wherein the first dielectric layer comprises a plurality of discontinuous first dielectric layer blocks, and each first dielectric layer block is provided with a plurality of first dielectric layer openings to expose the electrical connection pads; and forming a plurality of conductive elements on the electrical connection pads exposed out of the first dielectric layer opening. The invention reduces the residual stress of the first dielectric layer by forming a plurality of discontinuous first dielectric layer blocks, avoids the occurrence of chip warping (warping), and further can improve the product yield.
Description
Technical field
The present invention relates to a kind of semiconductor structure and its preparation method, more particularly to one kind prevent warpage
(warpage) semiconductor structure and its preparation method.
Background technology
With flourishing for electronic industry, electronic product tends to compact in kenel,
High-performance, high function, the R＆D direction of high speedization are functionally then gradually marched toward.And at present partly
The packing forms of conductor chip are encapsulated comprising routing type (Wire Bonding) or crystal covering type (Flip
Chip) encapsulation etc., wherein, encapsulates compared to routing type, and flip-chip type package can more reduce overall half
The volume of conductor device.
General flip-chip type package is bound to envelope by conductive projection on the acting surface of semiconductor chip
On the electric connection pad of dress substrate, primer is further filled with acting surface and the encapsulation of the semiconductor chip
Between substrate, to coat the conductive projection.
The technology of the existing semiconductor chip for providing tool conductive projection, refers to Figure 1A to Figure 1B.
As shown in Figure 1A, there is provided one has the chip 10 of multiple electric connection pads 100, its appearance
Face is made up of passivation layer 101.The passivation layer 101 is formed with perforate to expose the electric connection
Pad 100.Then, formation dielectric layer 11 is on the passivation layer 101 and perforate wall.Re-form
Projection underlying metal layer (Under Bump Metallurgy, UBM) 16 is in electric connection pad 100
On perforate wall.Then, formation conducting element 14 is on the projection underlying metal layer 16.
Figure 1B is the upper schematic diagram of corresponding Figure 1A, as illustrated, dielectric layer 11 is located at whole
On chip 10, continuous block is formed.
But, in aforementioned existing preparation method, because being first coated with a strata acid imide (Polyimide, PI)
, as dielectric layer on whole chip, but the polyimides are in a manufacturing method through high temperature for layer
Baking and cooling after, will produce stress-retained, be easily caused chip generation warpage (warpage),
Affect follow-up manufacture method yield.
Therefore, above-mentioned prior art how is avoided to lead because of the stress-retained problem of polyimide layer
Cause chip that warpage (warpage), and then the problem of the follow-up manufacture method yield of impact occur, actually
Current target to be solved.
Content of the invention
In view of the shortcoming of above-mentioned prior art, a kind of semiconductor structure of present invention offer and its preparation method,
The generation of chip warpage (warpage) is avoided, and then product yield can be improved.
The semiconductor structure of the present invention, including：Chip, its include passivation layer and multiple electrically
Connection gasket, the passivation layer have multiple passivation layer openings to expose those electric connection pads；First
Dielectric layer, its are formed on the passivation layer, and include multiple discontinuous first dielectric layer areas
Block, wherein respectively the first dielectric layer block is formed with multiple first dielectric layer openings to expose outside this
A little electric connection pads；And multiple conducting elements, which is formed at and exposes outside those the first dielectric layers
On those electric connection pads of opening.
The present invention also provides a kind of semiconductor structure, including：Chip, its include passivation layer and
Multiple electric connection pads, the passivation layer have multiple passivation layer openings to expose those electric connections
Pad；First dielectric layer, its are formed on the passivation layer, and include multiple discontinuous first
Dielectric layer block, wherein respectively the first dielectric layer block be formed with multiple first dielectric layer openings with
Expose outside those electric connection pads；Line layer, its are formed on first dielectric layer, and electrically
It is connected to the electric connection pad；Second dielectric layer, its are formed at first dielectric layer and the circuit
On layer, and include multiple discontinuous second electric dielectric layer blocks, wherein each second dielectric
Layer block is formed with exposed portion line layer beyond multiple second dielectric layer openings；And it is multiple
Conducting element, its are formed on the part line layer for exposing outside second dielectric layer opening.
The present invention reoffers a kind of preparation method of semiconductor structure, including：Offer includes multiple electricity
Property connection gasket and the chip of passivation layer, wherein, the passivation layer has beyond multiple passivation layer openings
Expose those electric connection pads；The first dielectric layer is formed on the passivation layer, wherein this first is situated between
Electric layer includes multiple discontinuous first dielectric layer blocks, and respectively the first dielectric layer block shape
Into having multiple first dielectric layer openings to expose outside those electric connection pads；And form multiple leading
Electric device is on those electric connection pads for exposing outside first dielectric layer opening.
The present invention provides a kind of preparation method of semiconductor structure again, including：Offer includes multiple electricity
Property connection gasket and the chip of passivation layer, wherein, the passivation layer has beyond multiple passivation layer openings
Expose those electric connection pads；The first dielectric layer is formed on the passivation layer, wherein this first is situated between
Electric layer includes multiple discontinuous first dielectric layer blocks, and respectively the first dielectric layer block shape
Into having multiple first dielectric layer openings to expose outside those electric connection pads；Line layer is formed in this
On first dielectric layer, and the line layer is made to be electrically connected to the electric connection pad；Form second to be situated between
Electric layer on first dielectric layer and the line layer, wherein second dielectric layer include multiple not
Continuous second dielectric layer block, and respectively the second dielectric layer block is formed with multiple second dielectrics
Exposed portion line layer beyond layer opening；And formed multiple conducting elements in expose outside this
On the line layer of the part of two dielectric layer openings.
In aforesaid semiconductor structure and its preparation method, wherein, before multiple conducting elements are formed,
Multiple include forming projection underlying metal layer below those conducting elements.
In aforesaid semiconductor structure and its preparation method, wherein, the conducting element is metal column, weldering
Stannum material or its combination.
In aforesaid semiconductor structure and its preparation method, wherein, the second dielectric layer block locations pair
Should be in the first dielectric layer block locations.
From the foregoing, it will be observed that the semiconductor structure of the present invention and its preparation method, in conducting element gap (pitch)
Larger region, or there is no the band of position of conducting element, by part of first dielectric layer or
Second dielectric layer is removed, to form multiple discontinuous first dielectric layer blocks and the second dielectric layer
Block.The residual stress of the first dielectric layer or the second dielectric layer can so be reduced, it is to avoid chip
The generation of warpage (warpage), and then improve product yield.
Description of the drawings
Figure 1A is the generalized section of the semiconductor chip of existing tool conductive projection；
Figure 1B is the upper schematic diagram of the semiconductor chip of existing tool conductive projection；
Fig. 2A to Fig. 2 D is the section of the first embodiment of the preparation method of the semiconductor structure of the present invention
Schematic diagram；
Fig. 2 E are the upper schematic diagram of the first embodiment of the semiconductor structure of the present invention；
Fig. 3 A to Fig. 3 C are the section of the second embodiment of the preparation method of the semiconductor structure of the present invention
Schematic diagram；And
Fig. 3 D are the upper schematic diagram of the second embodiment of the semiconductor structure of the present invention.
Description of reference numerals
10,20,30 chips
100,200,300 electric connection pads
101,201,301 passivation layers
11 dielectric layers
14,24,34 conducting elements
16,26,36 projection underlying metal layers
2,3 semiconductor structures
2011,3011 passivation layer openings
21,31 first dielectric layers
The first dielectric layer block of 21a, 31a
211,311 first dielectric layer openings
24a, 34a metal column
24b, 34a scolding tin material
32 line layers
33 second dielectric layers
33a the second dielectric layer blocks
331 second dielectric layer openings.
Specific embodiment
Embodiments of the present invention, art technology are described below by way of particular specific embodiment
Personnel can be understood other advantages and the work(of the present invention easily by content disclosed in the present specification
Effect.
It should be clear that structure, ratio, size depicted in this specification institute accompanying drawing etc., only in order to
Coordinate the content disclosed in description, for the understanding and reading of those skilled in the art, not
In order to limit enforceable qualificationss of the invention, therefore do not have technical essential meaning, any
The modification of structure, the change of proportionate relationship or the adjustment of size, can produce the present invention is not affected
Under raw effect and the purpose that can reach, still all should fall in disclosed technology contents
Obtain in the range of covering.Meanwhile, in this specification cited as " on ", " top ", " side ",
The term of " first ", " second " and " the 3rd " etc., is also only and is easy to described to understand, and
It is not used to limit enforceable scope of the invention, its relativeness is altered or modified, without reality
Under qualitative change more technology contents, when being also considered as enforceable category of the invention.
Fig. 2A to Fig. 2 E is refer to, which is the preparation method first embodiment of semiconductor structure of the present invention
Generalized section and upper schematic diagram.
As shown in Figure 2 A, there is provided one includes multiple electric connection pads 200 of such as aluminium (Al)
And the chip 20 of passivation layer 201.In one embodiment, the chip 20 can be multiple in wafer
One of chip.The outer surface of the chip 20 is by the passivation layer of for example, silicon nitride (SiN)
201 are constituted, and the passivation layer 201 has a passivation layer opening 2011 to expose the electric connection
Pad 200.Species about chip structure is various, and known to industry, therefore repeat no more.
As shown in Figure 2 B, the first dielectric layer 21 of formation is on the passivation layer 201.First Jie
Electric layer 21 is for example with polyimides (polyimide, PI), poly- to diazole benzene
(polybenzoxazole, PBO) or benzocyclobutene (Benezocy-clobutene, BCB) are
Material, is formed with method of spin coating (Spin Coating).
As shown in Figure 2 C, in exposure imaging mode, the first dielectric layer 21 of part is removed, is somebody's turn to do with making
First dielectric layer 21 forms multiple discontinuous first dielectric layer block 21a, and this is blunt to make part
Change layer 201 to be revealed between those first dielectric layers block 21a, while in respectively first dielectric layer
In block 21a to should 2011 position of passivation layer opening be formed with the first dielectric layer opening 211,
To expose the electric connection pad 200.
As shown in Figure 2 D, formed projection underlying metal layer (Under Bump Metallurgy,
UBM) 26 in the exposed surface of the electric connection pad 200, first dielectric layer opening 211 and portion
Divide on first dielectric layer 21.Conducting element 24 is formed in the projection with such as plating mode again
On underlying metal layer 26, so that the semiconductor structure 2 of the present invention is obtained.And the conducting element 24
Can be metal column, scolding tin material or its combination.In the present embodiment, the conducting element 24 includes gold
The category post 24a and scolding tin material 24b being formed on metal column 24a.
Additionally referring to Fig. 2 E, which is the upper schematic diagram of the semiconductor structure 2 of the present invention, wherein
Multiple discontinuous first dielectric layer block 21a are formed with the passivation layer 201.
Fig. 3 A to Fig. 3 D are refer to, which is the second embodiment of the preparation method of semiconductor structure of the present invention
Generalized section and upper schematic diagram.Part manufacture method is same as aforementioned in the present embodiment
As shown in Fig. 2A to Fig. 2 E, only illustrate below not exist together, in this step of identical manufacture method
Repeat no more.
As shown in Fig. 3 A to Fig. 3 B, the first dielectric layer 31 is initially formed in the passivation layer of chip 30
On 301.First dielectric layer 31 is for example with polyimides (polyimide, PI), poly- to diazole
Benzene (polybenzoxazole, PBO) or benzocyclobutene (Benezocy-clobutene, BCB)
For material, formed with method of spin coating (Spin Coating).
Then in exposure imaging mode, the first dielectric layer 31 of part is removed, so that first dielectric
Layer 31 forms multiple discontinuous first dielectric layer block 31a, and corresponding passivation layer opening 3011
Position is formed with the first dielectric layer opening 311, to expose the electric connection pad 300.
Line layer 32 is re-formed in each passivation layer opening 3011, and extends to first dielectric
On the part surface of layer 31, and the line layer 32 is made to be electrically connected with the electric connection pad 300.
As shown in Figure 3 C, the second dielectric layer 33 is formed in first dielectric layer 31, the line layer
On 32 and on the passivation layer 301.Second dielectric layer 33 for example with polyimides (polyimide,
PI), gather to diazole benzene (polybenzoxazole, PBO) or benzocyclobutene
(Benezocy-clobutene, BCB) is material, with method of spin coating (Spin Coating)
Formed.
Then in exposure imaging mode, the second dielectric layer 33 of part is removed, so that second dielectric
Layer 33 forms multiple discontinuous second dielectric layer block 33a, wherein the second dielectric layer block
33a positions correspond to the first dielectric layer block 31a positions, to make the part passivation layer 301 appear
In between those second dielectric layers block 33a, and formed in respectively second dielectric layer block 33a
There are multiple second dielectric layer openings 331 with the exposed parts line layer 32.
Re-form projection underlying metal layer 36 being somebody's turn to do for second dielectric layer opening 331 is exposed outside in this
On line layer 32, the second dielectric layer opening 331 and part second dielectric layer 33.Again with for example
Plating mode forms conducting element 34 on the projection underlying metal layer 36, so that the present invention is obtained
Semiconductor structure 3.And the conducting element 34 can be metal column, scolding tin material or its combination.In
In the present embodiment, the conducting element 34 includes metal column 34a and is formed on metal column 34a
Scolding tin material 34b.
Additionally referring to Fig. 3 D, which is the upper schematic diagram of the semiconductor structure 3 of the present invention, wherein
Multiple discontinuous second dielectric layer block 33a are formed with the passivation layer 301.
The present invention also provides a kind of semiconductor structure 2, as shown in Figure 2 D, the semiconductor structure 2
Include chip 20, the first dielectric layer 21 and conducting element 24.
The chip 20 includes multiple electric connection pads 200 of such as aluminium and for example, silicon nitride
(SiN) passivation layer 201, the passivation layer 201 have passivation layer opening 2011 to expose part
The electric connection pad 200.
First dielectric layer 21 is formed on the passivation layer 201 and includes multiple discontinuous
One dielectric layer block 21a, wherein respectively first dielectric layer block 21a is formed with multiple first dielectrics
Layer opening 211, those 211 positions of the first dielectric layer opening correspond to those passivation layer openings 2011
Position, to expose outside those electric connection pads 200.The material of the first dielectric layer 21 can be polyamides
Imines (polyimide, PI), poly- to diazole benzene (polybenzoxazole, PBO) or benzene
Cyclobutane (Benezocy-clobutene, BCB).
The conducting element 24 is formed at and exposes outside this of those the first dielectric layer openings 211 and electrically connect
On connection pad 200, to be electrically connected to the electric connection pad 200.In an embodiment, the conduction
Element 24 can be metal column, scolding tin material or its combination.In some embodiments, also include convex
Block underlying metal layer 26, its are located at below those conducting elements 24.
The present invention reoffers a kind of semiconductor structure 3, as shown in Figure 3 C.
The semiconductor structure 3 is similar to the semiconductor structure 2 described in preceding embodiment, also includes wired
Road floor 32 and the second dielectric layer 33.
The line layer 32 also extends to first dielectric in each first dielectric layer opening 311
On the part surface of layer 31, and it is electrically connected to the electric connection pad 300.
Second dielectric layer 33 is on first dielectric layer 31 with the line layer 32, and includes
There are multiple discontinuous second dielectric layer block 33a, wherein each second dielectric layer block 33a
Multiple second dielectric layer openings 331 are formed with the exposed parts line layer 32.
Conducting element 34 is formed on the line layer 32 for exposing outside second dielectric layer opening 331,
To be electrically connected with the line layer 32.
Another conducting element 34 can be metal column, scolding tin material or its combination, and in the conducting element 34
Projection underlying metal layer 36 formed below.
In sum, semiconductor structure of the invention and its preparation method, in conducting element gap (pitch)
Larger region, or there is no the band of position of conducting element, by part of first dielectric layer and
Second dielectric layer is removed, to form multiple discontinuous first dielectric layer blocks and the second dielectric layer
Block, can so reduce the residual stress of the first dielectric layer or the second dielectric layer, it is to avoid chip
The generation of warpage (warpage), and then improve product yield.
Principle and its effect of the above-described embodiment only in order to the illustrative present invention, not for
Limit the present invention.Any those skilled in the art can be in the spirit and the scope without prejudice to the present invention
Under, above-described embodiment is modified.Therefore the scope of the present invention, should be such as right
Listed by claim.
Claims (10)
1. a kind of semiconductor structure, it is characterized by, the semiconductor structure includes：
Chip, its include passivation layer and multiple electric connection pads, and the passivation layer has multiple blunt
Change layer opening to expose the electric connection pad；
First dielectric layer, its are formed on the passivation layer, and include multiple discontinuous first
Dielectric layer block, wherein respectively the first dielectric layer block be formed with multiple first dielectric layer openings with
Expose outside the electric connection pad；And
Multiple conducting elements, its are formed at and expose outside the described electrical of first dielectric layer opening
On connection gasket.
2. a kind of semiconductor structure, it is characterized by, the semiconductor structure includes：
Chip, its include passivation layer and multiple electric connection pads, and the passivation layer has multiple blunt
Change layer opening to expose the electric connection pad；
First dielectric layer, its are formed on the passivation layer, and include multiple discontinuous first
Dielectric layer block, wherein respectively the first dielectric layer block be formed with multiple first dielectric layer openings with
Expose outside the electric connection pad；
Line layer, its are formed on first dielectric layer, and are electrically connected to the electric connection pad；
Second dielectric layer, its are formed on first dielectric layer and the line layer, and are included many
Individual discontinuous second electric dielectric layer block, wherein respectively the second dielectric layer block be formed with multiple
Exposed portion line layer beyond second dielectric layer opening；And
Multiple conducting elements, its are formed at the part circuit for exposing outside second dielectric layer opening
On layer.
3. such as semiconductor structure according to claim 1 and 2, it is characterized by, this is partly led
Body structure also includes projection underlying metal layer, and which is formed at below the conducting element.
4. such as semiconductor structure according to claim 1 and 2, it is characterized by, the conduction
Element is metal column, scolding tin material or its combination.
5. such as semiconductor structure according to claim 2, it is characterized by, second dielectric
Layer block locations correspond to the first dielectric layer block locations.
6. a kind of preparation method of semiconductor structure, it is characterized by, the preparation method includes：
The chip for including multiple electric connection pads and passivation layer is provided, wherein, the passivation layer tool
There are multiple passivation layer openings to expose outside the electric connection pad；
The first dielectric layer is formed on the passivation layer, wherein first dielectric layer include multiple not
Continuous first dielectric layer block, and respectively the first dielectric layer block is formed with multiple first dielectrics
Layer is open to expose outside the electric connection pad；And
Multiple conducting elements are formed in the electric connection pad for exposing outside first dielectric layer opening
On.
7. a kind of preparation method of semiconductor structure, it is characterized by, the preparation method includes：
The chip for including multiple electric connection pads and passivation layer is provided, wherein, the passivation layer tool
There are multiple passivation layer openings to expose outside the electric connection pad；
The first dielectric layer is formed on the passivation layer, wherein first dielectric layer include multiple not
Continuous first dielectric layer block, and respectively the first dielectric layer block is formed with multiple first dielectrics
Layer is open to expose outside the electric connection pad；
Line layer is formed on first dielectric layer, and it is electrical to make the line layer be electrically connected to this
Connection gasket；
The second dielectric layer is formed on first dielectric layer and the line layer, wherein second dielectric
Layer includes multiple discontinuous second dielectric layer blocks, and respectively the second dielectric layer block is formed
There is exposed portion line layer beyond multiple second dielectric layer openings；And
Multiple conducting elements are formed in the part line layer for exposing outside second dielectric layer opening
On.
8. such as the preparation method of the semiconductor structure according to claim 6 or 7, it is characterized by,
Before multiple conducting elements are formed, also include being formed projection underlying metal layer in the conducting element
Lower section.
9. such as the preparation method of the semiconductor structure according to claim 6 or 7, it is characterized by,
The conducting element is metal column, scolding tin material or its combination.
10. such as the preparation method of semiconductor structure according to claim 7, it is characterized by, this
Two dielectric layer block locations correspond to the first dielectric layer block locations.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104129481 | 2015-09-07 | ||
| TW104129481A TWI549230B (en) | 2015-09-07 | 2015-09-07 | Semiconductor structure and fabrication method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106505053A true CN106505053A (en) | 2017-03-15 |
Family
ID=57445032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510600837.4A Pending CN106505053A (en) | 2015-09-07 | 2015-09-21 | Semiconductor structure and method for fabricating the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106505053A (en) |
| TW (1) | TWI549230B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101138084A (en) * | 2004-10-29 | 2008-03-05 | 弗利普芯片国际有限公司 | Semiconductor device package with bump overlying a polymer layer |
| US20130334656A1 (en) * | 2012-06-13 | 2013-12-19 | Samsung Electronics Co., Ltd. | Electrical interconnection structures including stress buffer layers |
| US20140319695A1 (en) * | 2013-04-24 | 2014-10-30 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW523842B (en) * | 2002-03-22 | 2003-03-11 | Advanced Chip Eng Tech Inc | Method for manufacturing i/o terminals and the structure thereof |
| US8759209B2 (en) * | 2010-03-25 | 2014-06-24 | Stats Chippac, Ltd. | Semiconductor device and method of forming a dual UBM structure for lead free bump connections |
| US8283781B2 (en) * | 2010-09-10 | 2012-10-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having pad structure with stress buffer layer |
-
2015
- 2015-09-07 TW TW104129481A patent/TWI549230B/en active
- 2015-09-21 CN CN201510600837.4A patent/CN106505053A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101138084A (en) * | 2004-10-29 | 2008-03-05 | 弗利普芯片国际有限公司 | Semiconductor device package with bump overlying a polymer layer |
| US20130334656A1 (en) * | 2012-06-13 | 2013-12-19 | Samsung Electronics Co., Ltd. | Electrical interconnection structures including stress buffer layers |
| US20140319695A1 (en) * | 2013-04-24 | 2014-10-30 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201711143A (en) | 2017-03-16 |
| TWI549230B (en) | 2016-09-11 |
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