CN106486485A - Memory component and its manufacture method - Google Patents
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- CN106486485A CN106486485A CN201510543155.4A CN201510543155A CN106486485A CN 106486485 A CN106486485 A CN 106486485A CN 201510543155 A CN201510543155 A CN 201510543155A CN 106486485 A CN106486485 A CN 106486485A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000007667 floating Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000002245 particle Substances 0.000 claims abstract description 23
- 239000007789 gas Substances 0.000 claims description 53
- 239000012535 impurity Substances 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 7
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 3
- 229910000070 arsenic hydride Inorganic materials 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 description 13
- 230000005641 tunneling Effects 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 5
- 238000010276 construction Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 230000000750 progressive effect Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- NIPNSKYNPDTRPC-UHFFFAOYSA-N N-[2-oxo-2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 NIPNSKYNPDTRPC-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- SVXHDONHRAZOCP-UHFFFAOYSA-N ethane;silicon Chemical compound [Si].CC SVXHDONHRAZOCP-UHFFFAOYSA-N 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
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- 238000003860 storage Methods 0.000 description 1
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Abstract
The invention discloses a kind of memory component and its manufacture method.Memory component includes dielectric layer between tunnel dielectric layer, floating grid, grid, control gate level and source area and drain region.Tunnel dielectric layer is located in substrate.Floating grid includes that Part I is located at Part II in tunnel dielectric layer and thereon.Part I contains the first admixture and the second admixture；Part II contains the first admixture.The particle diameter of Part I is less than the particle diameter of Part II, and the average grain diameter of Part I is between to dielectric layer between grid on floating grid.Control gate is between Wei Yuing grid on dielectric layer.Source area is located at drain region in the substrate of the both sides of floating grid.
Description
Technical field
The invention relates to a kind of semiconductor element and its manufacture method, and in particular to one kind
Memory component and its manufacture method.
Background technology
The electronic products such as digital camera, mobile phone camera and MP3 are very rapid in growth over the years,
So that consumer also rapidly increases to the demand of store media.As flash memory (Flash Memory) has
The characteristic of data non-volatile, power saving, small volume and mechanical structure etc., is therefore best suitable for as this
The store media of the portable and battery-powered electronic product of class.
But persistently pursue under high integration and result of scaling trend in integrated circuit, flash memory
Area shared by each memory cell but thus must reduce, and the live width of element equally reduces therewith.
Consequently, it is possible to the grid coupling efficiency (gate coupling ratio) between floating grid and control gate
Also and then can decline.The reduction of grid coupling efficiency can not only allow the threshold voltage (threshold of programming
voltage；Vt distribution) becomes wide, and can reduce Memory windows (memory window), storage
The reliability (such as data are preserved and durability) of device element can also be decreased.
Content of the invention
The present invention provides a kind of memory component and its manufacture method, and wherein memory component is formed as
There is the data preservation of improvement and the reliability of durability.
The present invention provides a kind of memory element, is situated between including substrate, control gate level, floating grid, tunnelling
Dielectric layer and source area and drain region between electric layer, grid.Tunnel dielectric layer is located in substrate.Floating grid
Pole includes the Part I in tunnel dielectric layer and Part II thereon, and wherein Part I contains
There are the first admixture and the second admixture；Part II contains the first admixture.The particle diameter of Part I is less than the
The particle diameter of two parts, and the average grain diameter of Part I betweenExtremelyDielectric layer position between grid
On floating grid.Control gate is between Wei Yuing grid on dielectric layer.Source area is located at floating grid with drain region
In the substrate of the both sides of pole.
According to the memory component described in the embodiment of the present invention, wherein described Part I and described second
Partial material includes DOPOS doped polycrystalline silicon, and in the Part I, the concentration of the first admixture is less than described the
The concentration of the first admixture in two parts.
According to the memory component described in the embodiment of the present invention, wherein described first admixture includes arsenic, phosphorus
Or boron；Second admixture includes carbon, nitrogen, oxygen or its combination.
The present invention provides a kind of memory element, is situated between including substrate, control gate level, floating grid, tunnelling
Dielectric layer and source area and drain region between electric layer, grid.Tunnel dielectric layer is located in substrate.Floating grid
Pole includes Part II positioned at Part I in tunnel dielectric layer and thereon, and wherein Part I contains
First admixture and the second admixture；Part II contains the first admixture.The electrical conductivity of Part I is less than the
The electrical conductivity of two parts.Between grid, dielectric layer is located on floating grid.Control gate dielectric layer between Wei Yuing grid
On.Source area is located at drain region in the substrate of the both sides of floating grid.
According to the memory component described in the embodiment of the present invention, wherein described Part I and described second
Partial material includes DOPOS doped polycrystalline silicon, and in the Part I, the concentration of the first admixture is less than described the
The concentration of the first admixture in two parts.
According to the memory component described in the embodiment of the present invention, wherein described first admixture includes arsenic, phosphorus
Or boron；Second admixture includes carbon, nitrogen, oxygen or its combination.
According to the memory component described in the embodiment of the present invention, the average grain diameter of wherein described Part I
BetweenExtremely
The present invention provides a kind of manufacture method of memory element, is included in formation tunnel dielectric layer in substrate.
Then, the first depositing operation is carried out, and the first mixed gas are passed through during first depositing operation,
To form Part I in the tunneling dielectric material layer, wherein described first mixed gas include silicon
Source, the first impurity gas and the second impurity gas.Then, the second depositing operation is carried out, and in institute
The second mixed gas are passed through during stating the second depositing operation, to form second on the Part I
Point, wherein described second mixed gas include the gas and first impurity gas.Afterwards,
Dielectric layer between grid is formed on the Part II.Furthermore, control on dielectric layer, is formed between the grid
Grid.Thereafter, source area and drain region are formed in the substrate of the side wall of the floating grid,
Wherein the conductivity type of the Part I and Part II is determined by first impurity gas,
And the particle size of the Part I is controlled by second impurity gas.
According to the manufacture method of the memory component described in the embodiment of the present invention, first impurity gas
Including arsenic hydride, hydrogen phosphide or diborane；Second impurity gas includes ethene, ammonia, ozone
Or its combination.
According to the manufacture method of the memory component described in the embodiment of the present invention, wherein described Part I
The concentration of the first admixture adulterated via first impurity gas is less than the Part II via institute
State the concentration of first admixture of the first impurity gas doping.
Based on above-mentioned, the present invention during floating grid is formed, due to being first passed through containing can prevent
The impurity gas of the admixture of silicon atom diffusion, therefore can first deposit one layer of particle diameter in tunnel dielectric layer
The relatively low doped layer of less and electrical conductivity, this contributes to memory component reaches narrower threshold voltage and divides
Cloth curve, and then improve the reliability of memory component.Therefore, the memory component of the present invention for
Data storage has higher reliability with durability degree.
It is that the features described above of the present invention and advantage can be become apparent, special embodiment below, and join
Close institute's accompanying drawings to be described in detail below.
Description of the drawings
Figure 1A to Fig. 1 C be according to the memory component Making programme depicted in embodiments of the invention
Profile.
Fig. 2 is the threshold voltage distribution map of the programming of memory component.
【Symbol description】
100：Substrate
102、102a：Tunneling dielectric material layer
102b：Tunnel dielectric layer
103：Strip laminated construction
104、104a：First doped layer
104b：Part I
105：Floating grid
106、106a：Second doped layer
106b：Part II
108：Dielectric materials layer between grid
108a：Dielectric layer between grid
110：Conductor material layer
110a：Control gate
112：Grid structure
114：Source area and drain region
Specific embodiment
Figure 1A to Fig. 1 C be according to the memory component Making programme depicted in embodiments of the invention
Profile.
First, refer to Figure 1A, substrate 100 be provided, substrate 100 be, for example, semiconductor base, half
Have on conductor compound substrate or insulating barrier semiconductor base (Semiconductor Over Insulator,
SO1).Semiconductor is, for example, the atom of IVA race, such as silicon or germanium.Semiconducting compound is, for example, IVA
The semiconducting compound formed by the atom of race, e.g. carborundum or germanium silicide, or Group IIIA
The semiconducting compound formed with VA race atom by atom, e.g. GaAs.
Then, tunneling dielectric material layer 102 is formed in substrate 100.Tunneling dielectric material layer 102
Material be, for example, silica, silicon oxynitride or dielectric constant higher than 4 dielectric material.Tunneling dielectric
The forming method of material layer 102 includes to carry out chemical vapour deposition technique, situ steam method of formation (in-situ
Steam generation, ISSG), low pressure free-radical oxidation method or furnace oxidation method etc..
Then, the first depositing operation is carried out, and is adulterated so that first is formed in tunneling dielectric material layer 102
Layer 104.The material of the first doped layer 104 is, for example, DOPOS doped polycrystalline silicon.First depositing operation is, for example,
Carried out with Low Pressure Chemical Vapor Deposition, its operating pressure is e.g. between 50Torr to 200Torr
Between, and technological temperature be, for example, between 450 degree to 650 degree Celsius.First doped layer 104
Thickness be, for example,Extremely
In the present embodiment, the first mixed gas are passed through during the first depositing operation.First gaseous mixture
Body includes silicon source, the first impurity gas and the second impurity gas, and the first doped layer 104 for being formed
The second admixture that the first admixture provided containing the first impurity gas and the second impurity gas are provided.
Silicon source is, for example, silicomethane (SiH4), silicon ethane (Si2H6) or its combination.First impurity gas example
Hydrogen phosphide (PH in this way3), arsenic hydride (AsH3) or diborane (B2H6).In the present embodiment,
The conductivity type of the first doped layer 104 can be determined by the first impurity gas, for example, when desire shape
Become N-type the first doped layer 104 when, the first impurity gas being passed through be PH3Or AsH3；When
During the first doped layer 104 of p-type to be formed, the first impurity gas being passed through is then B2H6.Second
Impurity gas is, for example, ethene (C2H4), ammonia (NH3), ozone (O3) or its combination.First
Admixture is, for example, phosphorus, arsenic or boron.Second admixture is, for example, carbon, nitrogen, oxygen or its combination.Second doping
The second admixture (such as carbon, nitrogen, oxygen or its combination) that gas is provided can be in the first depositing operation phase
Between prevent the diffusion of silicon atom, and then reduce the expansion of crystal boundary (grain boundary), therefore institute's shape
Become the particle diameter of the first doped layer 104 can be less.That is, the second doping gas can be passed through by adjustment
The flow of body is controlling the particle size of the first doped layer 104.The average grain diameter of the first doped layer 104
E.g. betweenExtremelyIn an exemplary embodiment, the first mixed gas be SiH4,
PH3With C2H4Mixed gas, wherein SiH4Range of flow is 100sccm to 250sccm；PH3
Range of flow is 10sccm to 200sccm；C2H4Range of flow is 1sccm to 10sccm.
Afterwards, Figure 1A is continued referring to, the second depositing operation is carried out, with the first doped layer 104
The second doped layer 106 of upper formation.In one embodiment, the material of the second doped layer 106 can be with
The material of one doped layer 104 is identical, e.g. DOPOS doped polycrystalline silicon.Can also in second doped layer 106
Equally there is the first admixture.But the concentration of the first admixture is more than the first doping in the second doped layer 106
The concentration of the first admixture in layer 104.The concentration of the first admixture and the second doping in first doped layer 104
In layer 106, the ratio of the concentration of the first admixture is between 1: 6 to 1: 2.In an exemplary embodiment, first
In doped layer 104 in the concentration of the first admixture and the second doped layer 106 concentration of the first admixture ratio
About 1: 3.In one embodiment, there is no the second admixture in the second doped layer 106.In another reality
Apply in example, in the second doped layer 106, can also have the second admixture, but in the second doped layer 106
The concentration of the second admixture is less than the concentration of the second admixture in the first doped layer 104.In other embodiments,
Progressive doped layer (not illustrating) can also be formed in tunneling dielectric material layer 102 to replace first
Doped layer 104 and the second doped layer 106.The concentration of the first admixture of progressive doped layer is by progressive
The top of doped layer toward 100 direction of substrate reduce, and the concentration of the second admixture of progressive doped layer by
The top of progressive doped layer increases toward 100 direction of substrate.
Second depositing operation is, for example, to be carried out with Low Pressure Chemical Vapor Deposition.In the second depositing operation
Period is passed through the second mixed gas.Second mixed gas include silicon source and above-mentioned first impurity gas.
The operating pressure of the second depositing operation is e.g. between 50Torr to 200Torr, and process warm
Degree be, for example, between 450 degree to 650 degree Celsius.The thickness of the second doped layer 106 is, for example, to be situated between
InExtremely
Silicon can be seldom prevented to spread due to not containing during the second doped layer 106 is formed or only containing
The second admixture, and in the second doped layer 106 first admixture concentration higher than in the first doped layer 104
The concentration of the first admixture, the particle diameter of the second doped layer 106 for therefore being formed can be more than the first doped layer
104 particle diameter.In one embodiment, the average grain diameter of the first doped layer 104 betweenExtremely
The average grain diameter of the second doped layer 106 be, for example, betweenExtremelyFurther, since first mixes
The particle diameter of diamicton 104 is less than the particle diameter of the second doped layer 106, the first admixture in the first doped layer 104
Concentration less than the first admixture in the second doped layer 106 concentration, therefore the leading of the first doped layer 104
Electric degree is less than the electrical conductivity of the second doped layer 106.
Then, Figure 1A and Figure 1B is refer to, and dielectric materials layer is tunneled through using photoetching and etching technics
102nd, the first doped layer 104 is patterned with the second doped layer 106, many to be formed in substrate 100
Individual strip laminated construction 103.Each strip laminated construction 103 includes tunneling dielectric material layer from lower to upper
102a, the first doped layer 104a and the second doped layer 106a.Strip laminated construction 103 is, for example, edge
First direction D1 extension.
Then, dielectric materials layer 108 and conductor material layer 110 between grid is sequentially formed in substrate 100.
In the present embodiment, between grid dielectric materials layer 108 be, for example, by oxide layer/nitration case/oxide layer
(Oxide/Nitride/Oxide；ONO the composite bed for) being constituted, but the invention is not restricted to this.Multiple
It can be three layers or more layers to close layer.The method for forming dielectric materials layer 108 between grid includes to carry out chemical gas
Phase sedimentation or thermal oxidation method etc..The material of conductor material layer 110 is, for example, DOPOS doped polycrystalline silicon.Formed
The method of conductor material layer 110 includes to carry out chemical vapour deposition technique.
Furthermore, Fig. 1 C is refer to, will be situated between conductor material layer 110, grid using photoetching and etching technics
Material layer 108 is patterned with strip laminated construction 103, to form grid structure in substrate 100
112.Grid structure 112 is included between tunnel dielectric layer 102b, floating grid 105, grid from lower to upper
Dielectric layer 108a and control gate 110a.Floating grid 105 includes Part I 104b and second
Part 106b.Between control gate 110a and grid, dielectric layer 108a extends each along second direction D2.
Second direction D2 is different from first direction D1, e.g. perpendicular to one another.
Then, with grid structure 112 as injection mask, ion implantation technology is carried out, with grid
Source area and drain region 114 is formed in the substrate 100 of the both sides of structure 112.In one embodiment,
Substrate 100 has the first conductivity type, and source area has the second conductivity type with drain region 114.First leads
Electric type is, for example, p-type；Second conductivity type is, for example, N-type, and vice versa.So far, the present invention is completed
Memory component making.
Hereinafter, the example for enumerating the present invention comes more specifically that the present invention will be described.However, not
Depart from the spirit of the present invention, suitably the material shown in Examples below, using method etc. can be entered
Row change.Therefore, the scope of the present invention should not carry out limited interpretation with concrete example shown below.
Example 1
In example 1, depositing operation is carried out using Low Pressure Chemical Vapor Deposition, with a silicon substrate
Form doped polysilicon layer.It is passed through during depositing operation including silicomethane, hydrogen phosphide and ethene
The flow of mixed gas, wherein ethene is 4sccm.
Example 2
Doped polysilicon layer is formed using the method similar with example 1, its difference is only ethene
Flow is 7sccm.
Example 3
Doped polysilicon layer is formed using the method similar with example 1, its difference is only ethene
Flow is 10sccm.
Comparative example
Doped polysilicon layer is formed using the method similar with example 1, its difference is only to be passed through
Mixed gas only include silicomethane and hydrogen phosphide.
Table 1 is the result of the particle size of the doped polysilicon layer formed by example 1-3 and comparative example.
Table 1
As shown in Table 1, in identical phosphorus concentration and C is passed through2H4In the case of gas,
With being passed through C2H4The flow of gas increases, and the particle diameter of the doped polysilicon layer for being formed is less.This
Be due to formed doped polysilicon layer during, C2H4Admixture (i.e. carbon atom) meeting provided by gas
Prevent the diffusion of silicon atom, and then the expansion of minimizing crystal boundary, therefore form the doped polycrystalline compared with small particle
Silicon layer.Will also realize that by the above results, can be by adjusting C2H4The flow of gas is controlling doped polycrystalline
The particle size of silicon layer.
Fig. 2 is the threshold voltage distribution map of the programming of memory component.First memory element has this
The floating grid being made up of Part I and Part II of invention, and second memory element has
Floating grid only through the doping of the first admixture.As seen from Figure 2, due to the first memory of the present invention
The particle diameter of the Part I of the floating grid of element is less, therefore may achieve the threshold value electricity of narrower programming
Pressure distribution curve, and then improve the reliability of memory component.
In sum, the present invention is during floating grid is formed, and is first passed through containing can prevent silicon
The impurity gas of the admixture of atoms permeating, less first to deposit one layer of particle diameter in tunnel dielectric layer
Doped layer, re-forms the larger doped layer of particle diameter afterwards.The less doped layer of particle diameter contributes to reaching relatively
The threshold voltage distribution curve of narrow programming, and then improve the reliability of memory component.
Although the present invention is disclosed above with embodiment, so which is not limited to the present invention, Ren Hesuo
Has usually intellectual in category technical field, without departing from the spirit and scope of the present invention, when can make
A little change and retouching, therefore protection scope of the present invention ought be defined depending on appended claims scope
Be defined.
Claims (10)
1. a kind of memory component, including：
Tunnel dielectric layer, in substrate；
Floating grid, including on the Part I in the tunnel dielectric layer and the Part I
Part II, wherein described Part I contains the first admixture and the second admixture, the Part II
Containing first admixture；
Dielectric layer between grid, on the floating grid；
Control gate, positioned between the grid on dielectric layer；And
Source area and drain region, in the substrate of the both sides of the floating grid,
The particle diameter of wherein described Part I is less than the particle diameter of the Part II, and the Part I
Average grain diameter betweenExtremely
2. memory component according to claim 1, wherein described Part I and described
The material of two parts includes DOPOS doped polycrystalline silicon, first admixture in wherein described Part I dense
Degree is less than the concentration of first admixture in the Part II.
3. memory component according to claim 1, wherein described first admixture include arsenic,
Phosphorus or boron；Second admixture includes carbon, nitrogen, oxygen or its combination.
4. a kind of memory component, including：
Tunnel dielectric layer, in substrate；
Floating grid, including on the Part I in the tunnel dielectric layer and the Part I
Part II, wherein described Part I contains the first admixture and the second admixture, the Part II
Containing first admixture；
Dielectric layer between grid, on the floating grid；
Control gate, positioned between the grid on dielectric layer；And
Source area and drain region, in the substrate of the both sides of the floating grid,
The electrical conductivity of wherein described Part I is less than the electrical conductivity of the Part II.
5. memory component according to claim 4, wherein described Part I and described
The material of two parts includes DOPOS doped polycrystalline silicon, and the concentration of first admixture in the Part I is low
The concentration of first admixture in the Part II.
6. memory component according to claim 4, wherein described first admixture include arsenic,
Phosphorus or boron；Second admixture includes carbon, nitrogen, oxygen or its combination.
7. memory component according to claim 4, the average grain of wherein described Part I
Footpath betweenExtremely
8. a kind of manufacture method of memory component, including：
Tunnel dielectric layer is formed in substrate；
The first depositing operation is carried out with the first mixed gas, floating to be formed in the tunnel dielectric layer
The Part I of grid, wherein described first mixed gas include silicon source, the first impurity gas and
Two impurity gas；
The second depositing operation is carried out with the second mixed gas, described floating to be formed on the Part I
The Part II of grid is put, wherein described second mixed gas include that the silicon source and described first is mixed
Miscellaneous gas；
Dielectric layer between grid is formed on the Part II；
Control gate is formed between the grid on dielectric layer；And
Source area and drain region are formed in the substrate of the side wall of the floating grid,
Wherein determine the Part I and the Part II by first impurity gas
Conductivity type, and the particle size of the Part I is controlled by second impurity gas.
9. the manufacture method of memory component according to claim 8, wherein described first mixes
Miscellaneous gas includes hydrogen phosphide, arsenic hydride or diborane；Second impurity gas include ethene, ammonia,
Ozone or its combination.
10. the manufacture method of memory component according to claim 8, wherein described first
The concentration of the first admixture that lease making is adulterated by first impurity gas less than the Part II via
The concentration of first admixture of the first impurity gas doping.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510543155.4A CN106486485A (en) | 2015-08-31 | 2015-08-31 | Memory component and its manufacture method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109494224A (en) * | 2017-09-08 | 2019-03-19 | 华邦电子股份有限公司 | Nonvolatile memory device and its manufacturing method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229631A (en) * | 1990-08-15 | 1993-07-20 | Intel Corporation | Erase performance improvement via dual floating gate processing |
| CN1536650A (en) * | 2003-02-06 | 2004-10-13 | ���ǵ�����ʽ���� | Method for making semiconductor integrated circuit and semiconductor integrated circuit madefrom |
| CN1630036A (en) * | 2003-12-17 | 2005-06-22 | 旺宏电子股份有限公司 | Semiconductor component and method of forming polysilicon layer therein |
| US20050184327A1 (en) * | 2004-02-19 | 2005-08-25 | Yoshio Ozawa | Stacked gate semiconductor memory and manufacturing method for the same |
| US20050212036A1 (en) * | 2004-03-26 | 2005-09-29 | Masayuki Tanaka | Semiconductor memory device and method of manufacturing the same |
| CN101047192A (en) * | 2006-03-31 | 2007-10-03 | 株式会社半导体能源研究所 | Nonvolatile semiconductor memory device |
| KR20090003746A (en) * | 2007-07-03 | 2009-01-12 | 주식회사 하이닉스반도체 | Nonvolatile memory device and method for fabricating the same |
| US20110001181A1 (en) * | 2009-07-06 | 2011-01-06 | Byoungsun Ju | Nonvolatile Memory Devices |
-
2015
- 2015-08-31 CN CN201510543155.4A patent/CN106486485A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229631A (en) * | 1990-08-15 | 1993-07-20 | Intel Corporation | Erase performance improvement via dual floating gate processing |
| CN1536650A (en) * | 2003-02-06 | 2004-10-13 | ���ǵ�����ʽ���� | Method for making semiconductor integrated circuit and semiconductor integrated circuit madefrom |
| CN1630036A (en) * | 2003-12-17 | 2005-06-22 | 旺宏电子股份有限公司 | Semiconductor component and method of forming polysilicon layer therein |
| US20050184327A1 (en) * | 2004-02-19 | 2005-08-25 | Yoshio Ozawa | Stacked gate semiconductor memory and manufacturing method for the same |
| US20050212036A1 (en) * | 2004-03-26 | 2005-09-29 | Masayuki Tanaka | Semiconductor memory device and method of manufacturing the same |
| CN101047192A (en) * | 2006-03-31 | 2007-10-03 | 株式会社半导体能源研究所 | Nonvolatile semiconductor memory device |
| KR20090003746A (en) * | 2007-07-03 | 2009-01-12 | 주식회사 하이닉스반도체 | Nonvolatile memory device and method for fabricating the same |
| US20110001181A1 (en) * | 2009-07-06 | 2011-01-06 | Byoungsun Ju | Nonvolatile Memory Devices |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109494224A (en) * | 2017-09-08 | 2019-03-19 | 华邦电子股份有限公司 | Nonvolatile memory device and its manufacturing method |
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