CN106469755A - Lateral double diffusion metal oxide semiconductor element and its manufacture method - Google Patents
Lateral double diffusion metal oxide semiconductor element and its manufacture method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 25
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000009792 diffusion process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 144
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 150000002500 ions Chemical group 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention proposes a kind of lateral double diffusion metal oxide semiconductor (lateral double diffused metal oxide semiconductor, LDMOS) element and its manufacture method.Wherein, LDMOS element comprises：P-type substrate, the first epitaxial layer, the second epitaxial layer, p type buried layer (P-type buried layer, PBL), p-type high pressure trap, p-type body zone, N-type trap, isolation zoneofoxidation, drift zoneofoxidation, grid, N-type contact areas, p-type contact areas, upper source electrode, lower source electrode and N-type drain.PBL stacks and is connected to the upper surface of p-type substrate.P-type high pressure trap stacks and is connected to PBL.P-type body zone stacks and is connected to p-type high pressure trap.Upper source electrode stacks and is connected to N-type contact areas and p-type contact areas.Lower source electrode stacks and is connected under the lower surface of p-type substrate.Wherein, in a normal operating, a conducting electric current flows through this lower source electrode by this N-type drain.
Description
Technical field
The present invention relates to a kind of lateral double diffusion metal oxide semiconductor (lateral double
Diffused metal oxide semiconductor, LDMOS) element and its manufacture method, particularly
Refer to a kind of LDMOS element reducing conducting resistance and its manufacture method.
Background technology
Fig. 1 shows a kind of existing lateral double diffusion metal oxide semiconductor (lateral double
Diffused metal oxide semiconductor, LDMOS) element 100 cross-sectional schematic.As
Shown in Fig. 1, LDMOS element 100 comprises：P-type substrate 101, drift region 102, isolation oxidation
Area 103, drift zoneofoxidation 104, body zone 106, drain electrode 110, source electrode 108 and grid 111.
Wherein, the conductivity type of drift region 102 is N-type, is formed on p-type substrate 101, completely cuts off zoneofoxidation
103 is zone oxidation (local oxidation of silicon, LOCOS) structure, with defining operation area
103a, main active region when operating as LDMOS element 100.The scope of operating space 103a by
In Fig. 1, slightly black arrow is illustrated.Grid 111 covering part drift zoneofoxidation 104.This is existing
LDMOS element 100 can use as power component, but therefore sacrifices conducting resistance, limits
The speed of operation, performance with element.
In view of this, the present invention is directed to the improvement of above-mentioned prior art, proposes a kind of LDMOS
Element and its manufacture method, it is possible to decrease the LDMOS element of conducting resistance and its manufacture method.
Content of the invention
It is an object of the invention to overcoming the deficiencies in the prior art and defect, one kind is proposed laterally double
Diffused metal oxide emiconductor element and its manufacture method, this element and its manufacture method can drop
Low on-resistance.
For reaching above-mentioned purpose, just wherein one viewpoint speech, the invention provides lateral double diffused metal
Oxide semiconductor (Lateral Double Diffused Metal Oxide Semiconductor,
LDMOS) element, comprises：One p-type substrate, in a short transverse, has on relative one
Surface and a lower surface；One first epitaxial layer, is formed on this p-type substrate, and highly square in this
Upwards, stack and be connected on this upper surface；One second epitaxial layer, is formed at this first extension
On layer, and in this short transverse, stack and be connected on this first epitaxial layer；One p type buried layer
(P-type buried layer, PBL), is formed in this first epitaxial layer and this second epitaxial layer, and
This PBL, in this short transverse, stacks and is connected to this upper surface, and comprises this first epitaxial layer
A junction with this second extension interlayer；One p-type high pressure trap, is formed in this second epitaxial layer
On this PBL, and in this short transverse, stack and be connected to this PBL；One p-type body zone,
It is formed on this p-type high pressure trap in this second epitaxial layer, and in this short transverse, stacking is simultaneously
It is connected to this p-type high pressure trap；One N-type trap, is formed in this second epitaxial layer, and horizontal in one
On be adjacent to this p-type body zone；One isolation zoneofoxidation, is formed on this second epitaxial layer, with fixed
An adopted operating space；One drift zoneofoxidation, is formed in this operating space on this second epitaxial layer,
And in this short transverse, this drift zoneofoxidation stacks and is connected to this N-type trap；One grid, shape
Become on this second epitaxial layer, and this grid is located in this operating space, and cover at least part of being somebody's turn to do
Drift zoneofoxidation, and in this short transverse, this gate stack is simultaneously connected to the second epitaxial layer simultaneously
This N-type trap of covering part and this p-type body zone of part；One N-type contact areas, are formed at this p-type originally
In body area；One p-type contact areas, are formed in this p-type body zone, and in this transversely with this N
Type contact areas adjoin；Source electrode on one, is formed on this second epitaxial layer, and in this short transverse
On, stack and be connected to this N-type contact areas and this p-type contact areas；Source electrode once, is formed at this P
Under this lower surface of type substrate, and in this short transverse, stack and be connected under this lower surface；
And a N-type drain, it is formed in this N-type trap, and this N-type drain is between this drift zoneofoxidation
And this isolation zoneofoxidation between；Wherein, in a normal operating, a conducting electric current is leaked by this N-type
Pole flows through this lower source electrode.
For reaching above-mentioned purpose, with regard to another viewpoint speech, the invention provides a kind of horizontal double diffusion gold
Genus oxide semiconductor (Lateral Double Diffused Metal Oxide Semiconductor,
LDMOS) manufacturing method, comprises：One p-type substrate is provided, its in a short transverse,
There is a relative upper surface and a lower surface；Form one first epitaxial layer on this p-type substrate,
And in this short transverse, stack and be connected on this upper surface；Form a p type buried layer (P-type
Buried layer, PBL) layer is ion implanted in this first epitaxial layer；Formed one second epitaxial layer in
On this first epitaxial layer, and in this short transverse, stack and be connected on this first epitaxial layer；
Layer is ion implanted with this PBL of hot fabrication process, to form a p type buried layer (P-type buried
Layer, PBL) in this first epitaxial layer with this second epitaxial layer, and this PBL is in this short transverse
On, stack and be connected to this upper surface, and comprise this first epitaxial layer and this second extension interlayer
A junction；Form a p-type high pressure trap on this PBL in this second epitaxial layer, and in this height
On degree direction, stack and be connected to this PBL；Form a p-type body zone in this second epitaxial layer
This p-type high pressure trap on, and in this short transverse, stack and be connected to this p-type high pressure trap；
Form a N-type trap in this second epitaxial layer, and be transversely adjacent to this p-type body zone in one；
Form an isolation zoneofoxidation on this second epitaxial layer, to define an operating space；Form a drift
Zoneofoxidation in this operating space on this second epitaxial layer, and in this short transverse, this drift
Zoneofoxidation stacks and is connected to this N-type trap；Form a grid on this second epitaxial layer, and this grid
Pole is located in this operating space, and covers this drift zoneofoxidation at least part of, and in this short transverse
On, this gate stack is simultaneously connected to the second epitaxial layer and this N-type trap of covering part and this p-type of part
Body zone；Form N-type contact areas in this p-type body zone；Form p-type contact areas in this P
In type body zone, and transversely adjoin with this N-type contact areas in this；Form a N-type drain in this
In N-type trap, and this N-type drain is between this drift zoneofoxidation and this isolation zoneofoxidation；Formed
On one, source electrode is on this second epitaxial layer, and in this short transverse, stacks and be connected to this N-type
Contact areas and this p-type contact areas；And formed source electrode under this lower surface of this p-type substrate,
And in this short transverse, stack and be connected under this lower surface；Wherein, in a normal operating
In, a conducting electric current flows through this lower source electrode by this N-type drain.
One kind is preferably implemented in kenel wherein, and this isolation zoneofoxidation with this drift zoneofoxidation is
Zone oxidation (local oxidation of silicon, LOCOS) structure or shallow trench isolation (shallow
Trench isolation, STI) structure.
One kind is preferably implemented in kenel wherein, and this conducting electric current is sequentially flowed through by this N-type drain
This N-type trap, this p-type body zone, this N-type contact areas, source electrode on this, this p-type contact areas, should
P-type body zone, this p-type high pressure trap, this PBL, this p-type substrate and this lower source electrode.
One kind is preferably implemented in kenel wherein, and on this, source electrode includes a metal level or a silication
Metal level.
One kind is preferably implemented in kenel wherein, and this lower source electrode includes a metal level or a silication
Metal level.
Below by way of specific embodiment elaborate, when being easier to understand the purpose of the present invention, skill
Art content, feature and its effect reached.
Brief description
Fig. 1 shows a kind of existing LDMOS element 100；
Fig. 2 shows first embodiment of the present invention；
Fig. 3 A-3M shows second embodiment of the present invention；
Fig. 4 shows the 3rd embodiment of the present invention.
In figure symbol description
100,200,300 LDMOS assemblies
101,201 p-type substrates
102 drift regions
103,203,303 isolation zoneofoxidations
103a, 203a operating space
104,204 drift zoneofoxidations
106,206 p-type body zone
108 source electrodes
110,210 drain electrodes
111,211 grids
201a upper surface
201b lower surface
202a first epitaxial layer
202b second epitaxial layer
205 p-type high pressure traps
207 N-type trap
208 N-type contact areas
209 p-type contact areas
212 p type buried layers (P-type buried layer, PBL)
212a junction
212b PBL is ion implanted layer
212c photoresist layer
213 times source electrodes
Source electrode on 214
Specific embodiment
Schema in the present invention all belongs to signal, is mostly intended to represent between fabrication steps and each layer
Orbution up and down, as shape, thickness and width then and not according to ratio draw.
Fig. 2 shows first embodiment of the present invention, and display is according to the horizontal double diffusion gold of the present invention
Genus oxide semiconductor (Lateral Double Diffused Metal Oxide Semiconductor,
LDMOS) the cross-sectional schematic of element 200.As shown in Fig. 2 LDMOS element, comprise：P
Type substrate 201, the first epitaxial layer 202a, the second epitaxial layer 202b, isolation zoneofoxidation 203, drift
Move zoneofoxidation 204, p-type high pressure trap 205, p-type body zone 206, N-type trap 207, N-type contact areas
208th, p-type contact areas 209, N-type drain 210, grid 211, p type buried layer (P-type buried layer,
PBL) 212, lower source electrode 213 and upper source electrode 214.
Wherein, p-type substrate 201 (side as shown in figure slightly black dotted line arrow in short transverse
To), there is relative upper surface 201a and lower surface 201b.First epitaxial layer 202a is formed at P
On type substrate 201, and in short transverse, stack and be connected on upper surface 201a.Outside second
Prolong a layer 202b to be formed on the first epitaxial layer 202a, and in short transverse, stack and be connected to
On first epitaxial layer 202a.PBL 212 is formed at the first epitaxial layer 202a and the second epitaxial layer 202b
In, and PBL 212, in short transverse, stacks and is connected to upper surface 201a, and comprise first
Junction 212a between epitaxial layer 202a and the second epitaxial layer 202b.P-type high pressure trap 205 is formed at
On PBL 212 in two epitaxial layer 202b, and in short transverse, stack and be connected to PBL
212.
P-type body zone 206 is formed on the p-type high pressure trap 205 in the second epitaxial layer 202b, and in
In short transverse, stack and be connected to p-type high pressure trap 205.N-type trap 207 is formed at the second extension
In layer 202b, and it is adjacent to p-type originally in transversely (direction as shown in figure slightly black solid arrow)
Body area 206.Isolation zoneofoxidation 203 is formed on the second epitaxial layer 202b, with defining operation area
203a.Drift zoneofoxidation 204 is formed in the operating space 203a on the second epitaxial layer 202b, and in
In short transverse, drift zoneofoxidation 204 stacks and is connected to N-type trap 207.Grid 211 is formed at
On second epitaxial layer 202b, and grid 211 is located in operating space 203a, and covers at least part of drift
Move zoneofoxidation 204, and in short transverse, grid 211 stacks and is connected to the second epitaxial layer 202b
And covering part N-type trap 207 and part p-type body zone 206.
N-type contact areas 208 are formed in p-type body zone 206.P-type contact areas 209 are formed at p-type
In body zone 206, and in transversely adjacent with N-type contact areas 208.Upper source electrode 214 is formed at
On two epitaxial layer 202b, and in short transverse, stack and be connected to N-type contact areas 208 and P
Type contact areas 209.Lower source electrode 213 is formed under the lower surface 201b of p-type substrate 201, and in height
On degree direction, stack and be connected under lower surface 201b.N-type drain 210 is formed at N-type trap 207
In, and N-type drain 210 is between drift zoneofoxidation 204 and isolation zoneofoxidation 203.Wherein,
In normal operating, conducting electric current flows through lower source electrode 213 by N-type drain 210, thick in such as Fig. 3 M
Black solid arrow is illustrated.
Fig. 3 A-3M shows second embodiment of the present invention.Fig. 3 A-3M shows according to the present invention
Lateral double diffusion metal oxide semiconductor (Lateral Double Diffused Metal Oxide
Semiconductor, LDMOS) element 200 manufacture method cross-sectional schematic.First, as Fig. 3 A
Shown, provide p-type substrate 201, wherein, p-type substrate 201 is such as, but not limited to P-type silicon substrate,
Can also be other semiconductor substrates.P-type substrate 201 is in short transverse (as in figure slightly black dotted line
Direction shown in arrow), there is relative upper surface 201a and lower surface 201b.Then as Fig. 3 B
Shown, form the first epitaxial layer 202a on p-type substrate 201, and in short transverse, stacking
And be connected on upper surface 201a.First epitaxial layer 202a is such as, but not limited to p-type epitaxial layer,
It is formed on p-type substrate 201.
Next, as illustrated in figs. 3 c and 3d, form p type buried layer (P-type buried layer, PBL)
Layer 212b is ion implanted in the first epitaxial layer 202a.Such as but not limited to formed with lithographic process
Photoresist layer 212c is shielding, to define PBL 212, and with ion implantation manufacture process, p-type is miscellaneous
Matter, in the form of accelerating ion, as in Fig. 3 C, fine dotted line arrow is illustrated, the area of implantation definition
In domain, and form PBL and layer 212b is ion implanted in the first epitaxial layer 202a, then again by photoetching
Glue-line 212c removes, as shown in Figure 3 D.
Next, as shown in FIGURE 3 E, form the second epitaxial layer 202b on the first epitaxial layer 202a,
And in short transverse, stack and be connected on the first epitaxial layer 202a.Next, as Fig. 3 F
Shown, a layer 212b is ion implanted with this PBL of hot fabrication process, to form p type buried layer (P-type
Buried layer, PBL) 212 in the first epitaxial layer 202a and the second epitaxial layer 202b, and PBL
212 in short transverse, stacks and be connected to upper surface 201a, and comprises the first epitaxial layer 202a
Junction 212a and between the second epitaxial layer 202b.Wherein, hot processing procedure and formation the second epitaxial layer 202b
Epitaxial manufacture process be necessarily separate two fabrication steps, this epitaxial manufacture process can also be incorporated into
In.
Next, as shown in Figure 3 G, form p-type high pressure trap 205 in the second epitaxial layer 202b
On PBL 212, and in short transverse, stack and be connected to PBL 212.Form p-type high pressure trap
205 method, is such as but not limited to formed with lithographic process, ion implantation manufacture process and hot processing procedure.
Next, as shown in figure 3h, form p-type in the second epitaxial layer 202b for the p-type body zone 206 high
On pressure trap 205, and in short transverse, stack and be connected to p-type high pressure trap 205.
Next, as shown in fig. 31, form N-type trap 207 in the second epitaxial layer 202b, and in
Transversely (direction as shown in figure slightly black solid arrow) is adjacent to p-type body zone 206.Connect down
Come, as shown in figure 3j, form isolation zoneofoxidation 203 on the second epitaxial layer 202b, to define behaviour
Make area 203a；Simultaneously or be subsequently formed drift operation on the second epitaxial layer 202b for the zoneofoxidation 204
In area 203a, and in short transverse, drift zoneofoxidation 203 stacks and is connected to N-type trap 204.
Wherein, isolation zoneofoxidation 203 and drift zoneofoxidation 204 are zone oxidation (local as depicted
Oxidation of silicon, LOCOS) structure or shallow trench isolation (shallow trench isolation,
STI) structure.
Next, as shown in Fig. 3 K, form grid 211 on the second epitaxial layer 202b, and grid
211 are located in operating space 203a, and cover at least part of drift zoneofoxidation 204, and in highly square
Upwards, grid 211 stacks and is connected to the second epitaxial layer 202b covering part N-type trap 207 and portion
Divide p-type body zone 206.Next, as shown in figure 3l, N-type contact areas 208 are formed in p-type body
In area 206；Form p-type contact areas 209 in p-type body zone 206, and in transversely connecing with N-type
Point area 208 adjoins；Form N-type drain 210 in N-type trap 207, and N-type drain 210 is between drift
Move between zoneofoxidation 204 and isolation zoneofoxidation 203.Wherein, N-type contact areas 208 and N-type drain 210
For example can be formed using identical lithographic process and ion implantation manufacture process.
Next, as shown in fig.3m, in formation source electrode 214 on the second epitaxial layer 202b, and
In short transverse, stack and be connected to N-type contact areas 208 and p-type contact areas 209；And shape
Become lower source electrode 213 under the lower surface 201a of p-type substrate 201, and in short transverse, stacking is simultaneously
It is connected under lower surface 201a.It should be noted that, in LDMOS element 200 normal operating, lead
Galvanization for example sequentially flows through N-type trap 207 by N-type drain 210, p-type body zone 206, N-type connect
Point area 208, upper source electrode 214, p-type contact areas 209, p-type body zone 206, p-type high pressure trap 205,
PBL 212, p-type substrate 201 and lower source electrode 213.Wherein, upper source electrode 214 and lower source electrode 213
For example include metal level or metal silicide layer.Wherein, conducting electric current flow to p-type originally by N-type trap 207
Body area 206, refers to be pressed on grid 211 because applying positive electricity, and in p-type body zone 206 and grid 211
When forming raceway groove (channel), therefore conducting operation at junction, conducting electric current is flowed by N-type trap 207
To p-type body zone 206, this is well known to those skilled in the art, and will not be described here.
Fig. 4 shows the 3rd embodiment of the present invention.The present embodiment shows according to the present invention's
The cross-sectional schematic of LDMOS element 300.The present embodiment is intended to illustrate, according to the present invention, to be formed
The mode of isolation zoneofoxidation 303 is however it is not limited to as shown in first embodiment.The present embodiment and
One embodiment difference is, as shown in figure 4, isolation zoneofoxidation 303 is shallow trench isolation
In (shallow trench isolation, STI) structure rather than such as first embodiment, completely cut off zoneofoxidation
203 is zone oxidation (local oxidation of silicon, LOCOS) structure.Other processing procedures with
First embodiment is identical, forms LDMOS element 300 as shown in Figure 4.Certainly, according to this
Invention, drift zoneofoxidation 204 is also not limited to as LOCOS structure, and can be sti structure.
It should be noted that, the present invention in many features, unlike the prior art, including normal
In operation, according to the LDMOS element 200 of the present invention, in conducting operation, the resistance of its series connection
Value includes being electrically connected to the concatenation path of lower source electrode 213 from upper source electrode 214, can be relatively low.
Wherein, the peak value of the p type impurity concentration of its high-voltage P-type trap 205, is distributed in not in the second epitaxial layer
The overhead surface of 202b.Additionally, by the epitaxial layer of two-layer, i.e. the first epitaxial layer 202a and
PBL 212 can be formed at the first epitaxial layer 202a and the second epitaxial layer by two epitaxial layer 202b
In 202b, and PBL 212, in short transverse, comprises the first epitaxial layer 212a and the second epitaxial layer
Junction 212a between 202b.Additionally, according to the LDMOS element 200 of the present invention, its lower source electrode 213
Under lower surface 201b, the LDMOS element 200 of the present invention can be made to be located under lower surface 201b
Concatenate another power component, the drain electrode of such as another power component again, radiating can be improved
Efficiency.
More than have been for preferred embodiment the present invention to be described, the above, only make this area
Technical staff is apparent to present disclosure, is not used for limiting the interest field of the present invention.
Under the same spirit of the present invention, those skilled in the art can think and various equivalence changes.Example
As, under not affecting the main characteristic of element, other fabrication steps or structure can be added, such as faces
Voltage Cortrol area of boundary etc.；For another example, photoetching technique is not limited to masking techniques, also can comprise electronics
Bundle photoetching technique；For another example, conductivity type p-type and N-type can exchange it is only necessary to other regions also
Exchange accordingly.The scope of the present invention should cover above-mentioned and other all equivalence changes.
Claims (10)
1. a kind of lateral double diffusion metal oxide semiconductor element is it is characterised in that comprise：
One p-type substrate, in a short transverse, has a relative upper surface and a lower surface；
One first epitaxial layer, is formed on this p-type substrate, and in this short transverse, stacking
And be connected on this upper surface；
One second epitaxial layer, is formed on this first epitaxial layer, and in this short transverse, heap
Fold and be connected on this first epitaxial layer；
One p type buried layer PBL, is formed in this first epitaxial layer and this second epitaxial layer, and should
PBL, in this short transverse, stacks and is connected to this upper surface, and comprises this first epitaxial layer
A junction with this second extension interlayer；
One p-type high pressure trap, is formed on this PBL in this second epitaxial layer, and in this height
On direction, stack and be connected to this PBL；
One p-type body zone, is formed on this p-type high pressure trap in this second epitaxial layer, and in
In this short transverse, stack and be connected to this p-type high pressure trap；
One N-type trap, is formed in this second epitaxial layer, and is transversely adjacent to this p-type in one
Body zone；
One isolation zoneofoxidation, is formed on this second epitaxial layer, to define an operating space；
One drift zoneofoxidation, is formed in this operating space on this second epitaxial layer, and in this height
On degree direction, this drift zoneofoxidation stacks and is connected to this N-type trap；
One grid, is formed on this second epitaxial layer, and this grid is located in this operating space, and
Cover at least partly this drift zoneofoxidation, and in this short transverse, this gate stack simultaneously connects
In the second epitaxial layer and this N-type trap of covering part and part this p-type body zone；
One N-type contact areas, are formed in this p-type body zone；
One p-type contact areas, are formed in this p-type body zone, and in this transversely with this N-type
Contact areas adjoin；
Source electrode on one, is formed on this second epitaxial layer, and in this short transverse, stacking is simultaneously
It is connected to this N-type contact areas and this p-type contact areas；
Source electrode once, is formed under this lower surface of this p-type substrate, and in this short transverse,
Stack and be connected under this lower surface；And
One N-type drain, is formed in this N-type trap, and this N-type drain aoxidizes between this drift
Between area and this isolation zoneofoxidation；
Wherein, in a normal operating, a conducting electric current flows through this lower source electrode by this N-type drain.
2. lateral double diffusion metal oxide semiconductor element as claimed in claim 1, wherein,
This isolation zoneofoxidation and this drift zoneofoxidation are zone oxidation structure or insulation structure of shallow groove.
3. lateral double diffusion metal oxide semiconductor element as claimed in claim 1, wherein,
This conducting electric current sequentially flows through this N-type trap, this p-type body zone, this N-type contact by this N-type drain
Area, source electrode on this, this p-type contact areas, this p-type body zone, this p-type high pressure trap, this PBL,
This p-type substrate and this lower source electrode.
4. lateral double diffusion metal oxide semiconductor element as claimed in claim 1, wherein,
On this, source electrode includes a metal level or a metal silicide layer.
5. lateral double diffusion metal oxide semiconductor element as claimed in claim 1, wherein,
This lower source electrode includes a metal level or a metal silicide layer.
6. a kind of lateral double diffusion metal oxide semiconductor manufacturing method, its feature exists
In comprising：
There is provided a p-type substrate, it has a relative upper surface and in a short transverse
Lower surface；
Form one first epitaxial layer on this p-type substrate, and in this short transverse, stacking is simultaneously
It is connected on this upper surface；
Form a p type buried layer PBL and layer is ion implanted in this first epitaxial layer；
Form one second epitaxial layer on this first epitaxial layer, and in this short transverse, stacking
And be connected on this first epitaxial layer；
Layer is ion implanted with this PBL of hot fabrication process, with formed a p type buried layer in this first
In epitaxial layer and this second epitaxial layer, and this PBL, in this short transverse, stacks and is connected to
This upper surface, and comprise a junction of this first epitaxial layer and this second extension interlayer；
Form a p-type high pressure trap on this PBL in this second epitaxial layer and highly square in this
Upwards, stack and be connected to this PBL；
Form a p-type body zone on this p-type high pressure trap in this second epitaxial layer, and in this
In short transverse, stack and be connected to this p-type high pressure trap；
Form a N-type trap in this second epitaxial layer, and be transversely adjacent to this p-type originally in one
Body area；
Form an isolation zoneofoxidation on this second epitaxial layer, to define an operating space；
Form a drift zoneofoxidation in this operating space on this second epitaxial layer, and in this height
On direction, this drift zoneofoxidation stacks and is connected to this N-type trap；
Form a grid on this second epitaxial layer, and this grid is located in this operating space, and cover
Lid at least partly this drift zoneofoxidation, and in this short transverse, this gate stack is simultaneously connected to
Second epitaxial layer this N-type trap of covering part and this p-type body zone of part；
Form N-type contact areas in this p-type body zone；
Form p-type contact areas in this p-type body zone, and transversely connect with this N-type in this
Point area adjoins；
Form a N-type drain in this N-type trap, and this N-type drain is between this drift zoneofoxidation
And this isolation zoneofoxidation between；
Form on one source electrode on this second epitaxial layer, and in this short transverse, stack and even
It is connected to this N-type contact areas and this p-type contact areas；And
Formed source electrode under this lower surface of this p-type substrate, and in this short transverse,
Stack and be connected under this lower surface；
Wherein, in a normal operating, a conducting electric current flows through this lower source electrode by this N-type drain.
7. lateral double diffusion metal oxide semiconductor element manufacturer as claimed in claim 6
Method, wherein, this isolation zoneofoxidation is zone oxidation structure with this drift zoneofoxidation or shallow trench is exhausted
Edge structure.
8. lateral double diffusion metal oxide semiconductor element manufacturer as claimed in claim 6
Method, wherein, this conducting electric current sequentially flows through this N-type trap, this p-type body by this N-type drain
Area, this N-type contact areas, source electrode, this p-type contact areas, this p-type body zone, this P on this
Type high pressure trap, this PBL, this p-type substrate and this lower source electrode.
9. lateral double diffusion metal oxide semiconductor element manufacturer as claimed in claim 6
Method, wherein, on this, source electrode includes a metal level or a metal silicide layer.
10. lateral double diffusion metal oxide semiconductor element as claimed in claim 6 manufactures
Method, wherein, this lower source electrode includes a metal level or a metal silicide layer.
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| CN110838512A (en) * | 2018-08-16 | 2020-02-25 | 立锜科技股份有限公司 | High voltage device and method for manufacturing the same |
| CN111081775A (en) * | 2018-10-19 | 2020-04-28 | 立锜科技股份有限公司 | High voltage device and method for manufacturing the same |
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