CN106469704A - Semiconductor chip package, system and manufacture method - Google Patents
Semiconductor chip package, system and manufacture method Download PDFInfo
- Publication number
- CN106469704A CN106469704A CN201510514194.1A CN201510514194A CN106469704A CN 106469704 A CN106469704 A CN 106469704A CN 201510514194 A CN201510514194 A CN 201510514194A CN 106469704 A CN106469704 A CN 106469704A
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- China
- Prior art keywords
- semiconductor chip
- chip package
- attachment disk
- lead wire
- lead
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of semiconductor chip package, a kind of system of this semiconductor chip package of inclusion and corresponding manufacture method.This semiconductor chip package includes：Lead frame, described lead frame includes a chip attachment disk and is arranged at least one lead wire of this chip attachment disk side；At least one semiconductor chip, at least one semiconductor chip described is disposed on the described chip attachment disk of described lead frame；Molding material, for covering at least a portion of described chip attachment disk and described lead wire, to form semiconductor chip package；Wherein the bottom in semiconductor chip package is provided with and climbs electric groove for increase creep age distance, and this is climbed electric groove and is located in the molding material between described chip attachment disk and described lead wire.The semiconductor chip package of the present invention can have bigger source-leakage creep age distance such that it is able to provide more preferable insulating properties when being applied to high-pressure electronic product.
Description
Technical field
The present invention relates to a kind of semiconductor chip package, a kind of this semiconductor die package of inclusion
The system of part and corresponding manufacture method.
Background technology
With the continuous development of high-power high voltage electronic device, semiconductor chip package is wanted
Seek also more and more higher.And, become less and less with electronic equipments such as radio telephones,
Require to produce less semiconductor chip package, enable them to be included in these electronics
In equipment.However, less packaging part usually requires that less semiconductor chip, this may
Impact internal performance simultaneously shortens creep age distance.Further, since comprising the half of such as power transistor
Conductor chip packaging part can produce amount of heat in the course of the work, also requires that improving tradition partly leads
The heat dispersion of body chip package.
For example, US granted patent US6756658B1 discloses a kind of surface with double lead
Install semiconductor chip package, wherein source electrode and drain electrode between creep age distance shorter so that
Easily break down when being applied to high voltage product.It is additionally, since this semiconductor die package
Part adopts wire as internal mutual line so that packaged resistance/inductance is higher it is impossible to carrying is high electric
Stream.Additionally, this semiconductor chip package only carries out unilateral cooling using PCB, lead to radiate
Effect is undesirable.
Therefore, need a kind of semiconductor chip package that can solve the problem that at least one the problems referred to above badly
And its system.
Content of the invention
The present invention passes through to provide a kind of semiconductor chip package, corresponding system and system as follows
Make method to realize at least one above-mentioned purpose.
On the one hand, the present invention provides a kind of semiconductor chip package it is characterised in that including：
Lead frame, described lead frame includes a chip attachment disk and to be arranged in this chip attached
At least one lead wire of disk side；
At least one semiconductor chip, at least one semiconductor chip described be disposed in described in draw
On the described chip attachment disk of wire frame；
Molding material, for covering at least a portion of described chip attachment disk and described lead wire,
To form semiconductor chip package；
Wherein the bottom in semiconductor chip package is provided with and climbs electricity for increase creep age distance
Groove, this climbs the molding material that electric groove is located between described chip attachment disk and described lead wire
In.
On the other hand, the present invention also provides a kind of system, and this system includes above-mentioned semiconductor chip
Packaging part, and a circuit substrate, described semiconductor chip package passes through surface-pasted
Mode is mounted to this circuit substrate.
Another further aspect, the present invention also provides a kind of manufacture for above-mentioned semiconductor chip package
Method, described manufacture method comprises the following steps：
A () obtains a lead frame, this lead frame includes a chip attachment disk and at least
One lead wire, at least one semiconductor chip is bonded to the chip attachment disk of lead frame；
B () covers chip attachment disk and at least one lead of described lead frame with molding material
Around at least a portion of piece, to form semiconductor chip package；And
C () forms electric recessed for increasing climbing of creep age distance in the bottom of semiconductor chip package
Groove, this climbs the mould that electric groove is located between described chip attachment disk and at least one lead wire described
In prepared material.
These and other embodiment of the present invention is described in detail with reference to the drawings in the description.
In the accompanying drawings, same or analogous part will be represented with same or analogous reference marker.In addition,
For clarity, some parts in accompanying drawing may be not to scale.
Brief description
Below in conjunction with the exemplary of the Description of Drawings present invention, can from described description
It is expressly understood the above and other aspects, features and advantages of the present invention.In the accompanying drawings：
Fig. 1 illustrates the decomposition of the semiconductor chip package according to one embodiment of the invention
Schematic diagram.
Fig. 2 illustrates the section of the semiconductor chip package according to one embodiment of the invention
Figure.
Fig. 3 illustrates the perspective of the semiconductor chip package according to one embodiment of the invention
Figure.
Fig. 4 illustrates that the semiconductor chip package according to one embodiment of the invention is encapsulating
Sectional view before.
Fig. 5 illustrates that the semiconductor chip package according to one embodiment of the invention is encapsulating
Axonometric chart before.
Fig. 6 illustrates the top view of the lead frame according to one embodiment of the invention.
Fig. 7 illustrates the side view of the lead frame of Fig. 6.
Fig. 8 illustrates the axonometric chart of the lead frame of Fig. 6.
Fig. 9 is shown in showing of the semiconductor chip package completing on the lead frame of Fig. 6
It is intended to.
Figure 10 illustrates the axonometric chart of the semiconductor chip package of Fig. 9.
Figure 11 illustrates the inclusion semiconductor chip package according to one embodiment of the invention
A system axonometric chart.
Figure 12 illustrates the sectional view of the system of Figure 11.
Figure 13 illustrates the inclusion semiconductor die package according to another embodiment of the invention
The axonometric chart of another system of part.
Figure 14 illustrates the sectional view of the system of Figure 13.
Specific embodiment
In the disclosure, term " bottom (portion) ", " top (portion) " are not intended to limit
Concrete orientation, but combine accompanying drawing and shown with respect to the conventional arrangement of semiconductor chip package
For example.
On the one hand, the present invention provides a kind of semiconductor chip package it is characterised in that including：
Lead frame, described lead frame includes a chip attachment disk and to be arranged in this chip attached
At least one lead wire of disk side；
At least one semiconductor chip, at least one semiconductor chip described be disposed in described in draw
On the described chip attachment disk of wire frame；
Molding material, for covering at least a portion of described chip attachment disk and described lead wire,
To form semiconductor chip package；
Wherein the bottom in semiconductor chip package is provided with and climbs electricity for increase creep age distance
Groove, this climbs the molding material that electric groove is located between described chip attachment disk and described lead wire
In.
In a preferred embodiment, at least one lead wire described has and is exposed to quasiconductor
Lead terminal outside chip package and the end of the inside inside semiconductor chip package
End, the lead terminal of at least one lead wire described and inside end are ladder-like arranged.
In a preferred embodiment, described semiconductor chip package further includes at least
One connection intermediate plate, described at least one connect intermediate plate be respectively electrically connected to described at least one
Between semiconductor chip and the corresponding inside end of at least one lead wire described.
In a preferred embodiment, described climb electric groove be located at described connection intermediate plate with described
Below connecting portion between the inside end of lead wire.
In a preferred embodiment, described climb electric groove along the basal surface side of chip attachment disk
To width be more than or equal to 1mm, and/or described climb electric groove along perpendicular to chip attachment disk side
To depth be more than or equal to 0.5mm.
In a preferred embodiment, wherein said chip attachment disk and described lead terminal it
Between edge climb electric groove profile creep age distance be more than or equal to 7.8mm.
In a preferred embodiment, described semiconductor chip package further includes one
Heating column, this heating column is disposed on described chip attachment disk neighbouring described semiconductor chip,
And the top surface of this heating column exposes from the top of semiconductor chip package.
In a preferred embodiment, the side of wherein this heating column is provided with recess, with shape
Become the cross sectional shape of basic " work " shape.
In a preferred embodiment, wherein this heating column is made of metal.
On the other hand, the present invention provides a kind of system it is characterised in that including：
One semiconductor chip package, this semiconductor chip package includes：
Lead frame, described lead frame includes a chip attachment disk and is arranged in this core
At least one lead wire of piece attachment disk side；
At least one semiconductor chip, at least one semiconductor chip described is disposed in institute
State on the described chip attachment disk of lead frame；
Molding material, for covering at least the one of described chip attachment disk and described lead wire
Part, to form semiconductor chip package；
Wherein it is provided with for increasing creep age distance in the bottom of semiconductor chip package
Climb electric groove, this is climbed electric groove and is located between described chip attachment disk and described lead wire
In molding material；And
One circuit substrate, semiconductor chip package is mounted to by surface-pasted mode
This circuit substrate.
In a preferred embodiment, described system further includes a top heat sink,
This top heat sink is installed in the top surface of semiconductor chip package, and be arranged in core
A heating column on piece attachment disk directly or indirectly contacts, and described circuit substrate is attached to half
The basal surface of conductor chip packaging part.
Preferably, in the case that described system includes above-mentioned top heat sink, this system also may be used
To further include an insulating trip, this insulating trip is disposed in top heat sink and semiconductor core
Between the top surface of chip package.Preferably, described circuit substrate is provided with an opening,
This opening climbs the lower section of electric groove and along the length direction extension climbing electric groove positioned at described.
In a preferred embodiment, described system further includes a bottom heat spreader,
This bottom heat spreader is installed in the basal surface of semiconductor chip package, and adheres to chip
The basal surface of disk directly or indirectly contacts, but climbs electric groove described in not covering.
Preferably, in the case that described system includes above-mentioned bottom heat spreader, semiconductor chip
The top surface of packaging part can be mounted to described circuit substrate, described circuit substrate be arranged in core
A heating column on piece attachment disk directly or indirectly contacts.And it is preferable that described system
An insulating trip can also be included, this insulating trip is disposed in bottom heat spreader and semiconductor chip
Between the basal surface of packaging part.
Another further aspect, the present invention provides a kind of side for manufacturing above-mentioned semiconductor chip package
Method, comprises the following steps：
A () obtains a lead frame, this lead frame includes a chip attachment disk and at least
One lead wire, at least one semiconductor chip is bonded to the chip attachment disk of lead frame；
B () covers chip attachment disk and at least one lead of described lead frame with molding material
Around at least a portion of piece, to form semiconductor chip package；And
C () forms electric recessed for increasing climbing of creep age distance in the bottom of semiconductor chip package
Groove, this climbs the mould that electric groove is located between described chip attachment disk and at least one lead wire described
In prepared material.
In a preferred embodiment, further include a step (d)：By a heat conduction
Post is arranged on described chip attachment disk neighbouring described semiconductor chip.
In a preferred embodiment, further include at one step of execution after step (c)
Suddenly (e)：By the top surface of a heat spreader attachment to semiconductor chip package or basal surface.
In a preferred embodiment, wherein this manufacture method is suitable to manufacture SiC device.
Describe the semiconductor chip package of the present invention below with reference to accompanying drawings in detail, including should be partly
The system of conductor chip packaging part and the embodiment of corresponding manufacture method.It should be appreciated that
Embodiments below and accompanying drawing are only illustrative, are not construed as limiting the scope of the present invention.
Fig. 1 illustrates the decomposition of the semiconductor chip package according to one embodiment of the invention
Schematic diagram.
As shown in fig. 1, the inside of this semiconductor chip package includes at least one quasiconductor
Chip 200, a such as one semiconductor chip DIODE 201 and semiconductor chip FET 202；
And also include a lead frame, this lead frame comprise a chip attachment disk 50 with relative
At least one lead wire 300 of arrangement.For example, this at least one lead wire may include electrically exhausted
The source lead piece of edge and grid lead piece.Molding material is used for covering described chip attachment disk 50
With at least a portion of described lead wire 300, they are partly encapsulated and partly leads thus being formed
Body chip package 100.Described molding material can be epoxy molding compounds (EMC), example
As epoxy resin.Advantageously, the bottom in semiconductor chip package 100 is provided with one and climbs
Electric groove 60, to increase the creep age distance between described lead wire and described chip attachment disk,
That is, source-leakage creep age distance.This climbs electric groove 60 can be after semiconductor chip package completes
Formed, in the molding material between described chip attachment disk and described lead wire.By setting
Put this and climb electric groove, the semiconductor chip package of the present invention can increase climbs electricity between source-leakage
Distance, thus be applied to high voltage high power electronic product and be greater than the SiC of 1200V
More preferable insulating properties is provided during device.
Fig. 2 illustrates the section of the semiconductor chip package according to one embodiment of the invention
Figure.Fig. 3 illustrates the perspective of the semiconductor chip package according to one embodiment of the invention
Figure.
In conjunction with Fig. 1, can be more clearly visible that from Fig. 2 and Fig. 3, source lead piece has cruelly
It is exposed at the source lead terminal 301 outside semiconductor chip package and be located at semiconductor chip envelope
Inside end 303 inside piece installing.Similarly, grid lead piece also has and is exposed to quasiconductor
Grid lead terminal 302 outside chip package and being located inside semiconductor chip package
Inside end 304.The source lead terminal 301 of described source lead piece and inside end 303
It is ladder-like arranged.Similarly, the grid lead terminal 302 of described grid lead piece and Qi Nei
Portion end 304 is also ladder-like arranged.The inside end 303 of described source lead piece and described
The inside end 304 of grid lead piece can be with the semiconductor core being arranged on chip attachment disk 50
Piece 201 and 202 flushes, is higher or lower than described semiconductor chip 201 and 202.
Preferably, described semiconductor chip package 100 further includes source electrode attachment clips
Piece 401 and a grid connect intermediate plate 402.Described source electrode connects intermediate plate 401 and is connected electrically in
The inside end 303 of described semiconductor chip DIODE 201 and corresponding source lead piece it
Between.Described grid connects intermediate plate 402 and is connected electrically in described semiconductor chip FET 202 and phase
Between the inside end 304 of corresponding grid lead piece.Replace tradition by using connecting intermediate plate
Wire, can achieve relatively low packaged resistance/inductance, and high current can be carried.
In the inside end 303 of described source lead piece and the inside end of described grid lead piece
In the case that 304 are flushed with the semiconductor chip 201 and 202 being arranged on chip attachment disk 50,
It can be a flat shape that described source electrode connects intermediate plate 401 and described grid connection intermediate plate 402
Connector (as shown in Figure 2).In the inside end 303 of described source lead piece and described
The horizontal level of the inside end 304 of grid lead piece is higher or lower than described semiconductor chip
When 201 and 202, described source electrode connects intermediate plate 401 and described grid connection intermediate plate 402 is permissible
It is correspondingly the connector of a stairstepping.In addition, the inside end of described source lead piece
303 and the upper surface of inside end 304 of described grid lead piece can be covered with for source electrode respectively
Connect intermediate plate 401 and grid connects electroconductive binder or the solder of intermediate plate 402.
Preferably, described climb electric groove 60 and be located at described connection intermediate plate 400 and described lead wire
Below connecting portion between 300 inside end, to form compact space arrangement.Described climb
The width W1 in the basal surface direction along chip attachment disk 50 for the electric groove 60 can be more than or equal to 1mm,
So that creep age distance can be calculated along the recessed profile climbing electric groove.Described climb electric groove edge
Depth D1 perpendicular to chip attachment disk direction can be more than or equal to 0.5mm.Described chip is attached
The edge between disk and described lead terminal climb electric groove profile creep age distance L1 (as Fig. 2
In the length climbing power path represented by black line) 7.8mm can be more than or equal to.Due to climbing electricity
The calculation of distance is relevant with the shape and size of groove and internal deposition conditions, above-mentioned pass
It is not restricted in the concrete example climbing electric groove, those skilled in the art can be according to reality
Border application selects suitably to climb the shape and size of electric groove, as long as disclosure satisfy that required climbing
Electrical distance.
Fig. 4 illustrates that the semiconductor chip package according to one embodiment of the invention is encapsulating
Sectional view before.Fig. 5 illustrates the semiconductor chip envelope according to one embodiment of the invention
Piece installing axonometric chart before encapsulation.
In a preferred embodiment, described semiconductor chip package further includes one
Heating column 70, this heating column 70 is disposed on described chip attachment disk neighbouring described quasiconductor
Chip, and the top surface of this heating column 70 can expose from the top of semiconductor chip package
Go out (as shown in Figure 2).As clearly visible in Fig. 4, the side of this heating column is provided with edge
The recess of its length direction extension, to form the cross sectional shape of basic " work " shape.So exist
In molding process, this heating column can be better locked onto in molding material.Preferably, should
Heating column can be made up of Heat Conduction Material known in the art (for example, the metal material such as copper),
Preferably it is transmitted to the outside of semiconductor chip package with the heat energy producing semiconductor chip.
Fig. 6 illustrates the top view of the lead frame according to one embodiment of the invention.Fig. 7
The side view of the lead frame of Fig. 6 is shown.Fig. 8 illustrates the axonometric chart of the lead frame of Fig. 6.
Fig. 6-8 shows that three of initial acquisition connect the lead frame of arrangement side by side.As Fig. 6
Shown in, a lead frame includes a chip attachment disk 50 and two lead wire, and described two
Individual lead wire includes being stepped the outer leg terminal 301 of arrangement and 302 and inside end
303 and 304.The lead frame of the present invention can form thicker lead by being stamped and formed out
Framework, thus reaching more preferable radiating effect, and can installed by surface mount mode
During to circuit substrate, obtain the more stable surface mount device (SMD) of performance.In addition, this
The lead plate shape of the lead frame of invention can form compact Layout with climbing electric groove so that
While increasing creep age distance, also will not expand the size of semiconductor chip package, thus more
Meet related request well.
Fig. 9 is shown in showing of the semiconductor chip package completing on the lead frame of Fig. 6
It is intended to.Figure 10 illustrates the axonometric chart of the semiconductor chip package of Fig. 9.
Three semiconductor die package being arranged in juxtaposition having completed are shown in Fig. 9 and 10
Part, after they being cut apart and pass through other subsequent process steps such as example polish,
An independent semiconductor chip package 100 as shown in Figures 2 and 3 can be obtained.
Figure 11 illustrates the inclusion semiconductor chip package according to one embodiment of the invention
A system axonometric chart.Figure 12 illustrates the sectional view of the system of Figure 11.
The semiconductor chip package 100 having completed can be pacified by surface-pasted mode
It is filled to a circuit substrate 80, thus forming the electricity of an inclusion semiconductor chip package 100
Gas system.As shown in FIG. 11 and 12, this system can further include a top heat sink 90,
This top heat sink 90 is installed in the top surface of semiconductor chip package 100, and and cloth
The heating column 70 put on chip attachment disk directly or indirectly contacts.So, semiconductor core
Heat within chip package can not only be conducted by the circuit substrate 80 of bottom, and can lead to
Cross heating column 70 and be conducted to top heat sink 90, thus reach two-sided cooling (that is, top and
Bottom cools down simultaneously) effect.
In addition, can arrange an opening 801 in described circuit substrate, this opening 801 is located at
The described lower section climbing electric groove 60 and extending, to increase source along the length direction climbing electric groove
The air gap between pole and drain electrode is climbed it is ensured that can calculate along the recessed profile climbing electric groove
Electrical distance.Preferably, in the case that described system includes top heat sink 90, this system is also
May further include an insulating trip (not shown), this insulating trip is disposed in top heat sink
And the top surface of semiconductor chip package between.
Figure 13 illustrates the inclusion semiconductor die package according to another embodiment of the invention
The axonometric chart of another system of part.Figure 14 illustrates the sectional view of the system of Figure 13.
To include a top heat sink different from the system in Figure 11 and 12, in Figure 13 and 14
The system illustrating includes a bottom heat spreader 90 ', and this bottom heat spreader 90 ' is installed in half
The basal surface of conductor chip packaging part, and directly or indirectly connect with the basal surface of chip attachment disk
Touch, but described in not covering, climb electric groove 60.The top surface of described semiconductor chip package can
Be mounted to a circuit substrate 80 ', described circuit substrate 80 ' be arranged in chip attachment disk
On a heating column 70 directly or indirectly contact.In addition, quasiconductor as shown in Figure 14
The stairstepping of the lead wire in chip package and the semiconductor die package shown in Figure 12
The stairstepping of the lead wire in part is on the contrary so that the outer leg terminal of lead wire can be upwards
Extend to be attached to the circuit substrate 80 ' of top.
Similarly, the system shown in Figure 13 and 14 also can reach two-sided cooling (that is, top
Cool down with bottom simultaneously) effect, and due to bottom heat spreader 90 ' with drain electrode output area straight
Contact is such that it is able to realize more preferable radiating effect.In addition, this system can also include one
Individual insulating trip (not shown), this insulating trip can be disposed in bottom heat spreader 90 ' and quasiconductor
Between the basal surface of chip package.
Yet another aspect, although not shown, the present invention also provides one kind to be used for manufacturing quasiconductor
The method of chip package, the method comprises the following steps：
A () obtains a lead frame, this lead frame includes a chip attachment disk and at least
One lead wire, at least one semiconductor chip is bonded to the chip attachment disk of lead frame；
B () covers chip attachment disk and at least one lead of described lead frame with molding material
Around at least a portion of piece, to form semiconductor chip package；And
C () forms electric recessed for increasing climbing of creep age distance in the bottom of semiconductor chip package
Groove, this climbs the mould that electric groove is located between described chip attachment disk and at least one lead wire described
In prepared material.
Preferably, said method also includes a step (d)：One heating column is arranged on institute
State neighbouring described semiconductor chip on chip attachment disk.This step (d) can in step (b) or
Execute before (c).
Preferably, can perform a step (e) after step (c)：By a radiator
It is attached to top surface or the basal surface of semiconductor chip package.This radiator can be that top dissipates
Hot device 90 or bottom heat spreader 90 '.
Above-mentioned manufacture method may be adapted to manufacture SiC device.
It should be understood that present disclosure is not limited to specific embodiments described above.
In the case of without departing from spirit and scope of the appended claims, present disclosure can be entered
The multiple modification of row and replacement, for example, can carry out selecting combination to above-mentioned technical characteristic, described many
Plant modification and replacement should be understood as being within the scope of the present invention.
Claims (10)
1. a kind of semiconductor chip package is it is characterised in that include：
Lead frame, described lead frame includes a chip attachment disk and to be arranged in this chip attached
At least one lead wire of disk side；
At least one semiconductor chip, at least one semiconductor chip described be disposed in described in draw
On the described chip attachment disk of wire frame；
Molding material, for covering at least a portion of described chip attachment disk and described lead wire,
To form semiconductor chip package；
Wherein the bottom in semiconductor chip package is provided with and climbs electricity for increase creep age distance
Groove, this climbs the molding material that electric groove is located between described chip attachment disk and described lead wire
In.
2. semiconductor chip package according to claim 1, wherein said at least one
Lead wire has the lead terminal being exposed to outside semiconductor chip package and is located at semiconductor core
Inside end inside chip package, the lead terminal of at least one lead wire described and inside end
End is ladder-like arranged.
3. semiconductor chip package according to claim 2, further includes at least one
Individual connection intermediate plate, described at least one connect intermediate plate be respectively electrically connected to described at least one half
Between the inside end of conductor chip and corresponding lead wire.
4. semiconductor chip package according to claim 3, wherein said climbs electric groove
Below the described connecting portion connecting between intermediate plate and the inside end of described lead wire.
5. semiconductor chip package according to claim 1, further includes that one is led
Plume, this heating column is disposed on described chip attachment disk neighbouring described semiconductor chip, and
And the top surface of heating column exposes from the top of semiconductor chip package.
6. a kind of system is it is characterised in that include：
One semiconductor chip package, this semiconductor chip package includes：
Lead frame, described lead frame includes a chip attachment disk and is arranged in this core
At least one lead wire of piece attachment disk side；
At least one semiconductor chip, at least one semiconductor chip described is disposed in institute
State on the described chip attachment disk of lead frame；
Molding material, for covering at least the one of described chip attachment disk and described lead wire
Part, to form semiconductor chip package；
Wherein it is provided with for increasing creep age distance in the bottom of semiconductor chip package
Climb electric groove, this is climbed electric groove and is located between described chip attachment disk and described lead wire
In molding material；And
One circuit substrate, semiconductor chip package is mounted to by surface-pasted mode
This circuit substrate.
7. system according to claim 6, further includes a top heat sink, should
Top heat sink is installed in the top surface of semiconductor chip package, and be arranged in chip
A heating column on attachment disk directly or indirectly contacts, and described circuit substrate is attached to partly leads
The basal surface of body chip package.
8. system according to claim 7, is wherein provided with one in described circuit substrate
Individual opening, this opening climbs the lower section of electric groove and along the length side climbing electric groove positioned at described
To extension.
9. system according to claim 6, further includes a bottom heat spreader, should
Bottom heat spreader is installed in the basal surface of semiconductor chip package, and with chip attachment disk
Basal surface directly or indirectly contact, but described in not covering, climb electric groove.
10. a kind of manufacture method is it is characterised in that comprise the following steps：
A () obtains a lead frame, this lead frame includes a chip attachment disk and at least one
Individual lead wire, at least one semiconductor chip is bonded to the chip attachment disk of lead frame；
B () covers chip attachment disk and at least one lead of described lead frame with molding material
Around at least a portion of piece, to form semiconductor chip package；And
C () forms electric recessed for increasing climbing of creep age distance in the bottom of semiconductor chip package
Groove, this climbs the mould that electric groove is located between described chip attachment disk and at least one lead wire described
In prepared material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510514194.1A CN106469704A (en) | 2015-08-20 | 2015-08-20 | Semiconductor chip package, system and manufacture method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510514194.1A CN106469704A (en) | 2015-08-20 | 2015-08-20 | Semiconductor chip package, system and manufacture method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473410A (en) * | 2017-09-08 | 2019-03-15 | 英飞凌科技奥地利有限公司 | SMD encapsulation with top side cooling end |
| CN110518814A (en) * | 2019-09-19 | 2019-11-29 | 江西精骏电控技术有限公司 | A kind of two-sided cooling structure for vehicle-mounted inverter |
| CN118299356A (en) * | 2024-05-14 | 2024-07-05 | 日月新半导体(威海)有限公司 | Front side heat dissipation structure of semiconductor chip and packaging method thereof |
-
2015
- 2015-08-20 CN CN201510514194.1A patent/CN106469704A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473410A (en) * | 2017-09-08 | 2019-03-15 | 英飞凌科技奥地利有限公司 | SMD encapsulation with top side cooling end |
| CN109473410B (en) * | 2017-09-08 | 2023-11-28 | 英飞凌科技奥地利有限公司 | SMD package with topside cooling |
| CN110518814A (en) * | 2019-09-19 | 2019-11-29 | 江西精骏电控技术有限公司 | A kind of two-sided cooling structure for vehicle-mounted inverter |
| CN118299356A (en) * | 2024-05-14 | 2024-07-05 | 日月新半导体(威海)有限公司 | Front side heat dissipation structure of semiconductor chip and packaging method thereof |
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