CN106463242A - 制造用于高频开关模式电源的微细加工的晶片级集成电感器或变压器的方法 - Google Patents
制造用于高频开关模式电源的微细加工的晶片级集成电感器或变压器的方法 Download PDFInfo
- Publication number
- CN106463242A CN106463242A CN201580026307.1A CN201580026307A CN106463242A CN 106463242 A CN106463242 A CN 106463242A CN 201580026307 A CN201580026307 A CN 201580026307A CN 106463242 A CN106463242 A CN 106463242A
- Authority
- CN
- China
- Prior art keywords
- layer
- polymer layer
- polymer
- top surface
- conducting material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 5
- 229920000642 polymer Polymers 0.000 claims abstract description 157
- 238000000034 method Methods 0.000 claims abstract description 42
- 230000008569 process Effects 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 336
- 239000004020 conductor Substances 0.000 claims description 61
- 229920002120 photoresistant polymer Polymers 0.000 claims description 41
- 239000013047 polymeric layer Substances 0.000 claims description 41
- 239000013078 crystal Substances 0.000 claims description 33
- 230000004888 barrier function Effects 0.000 claims description 20
- 239000011810 insulating material Substances 0.000 claims description 20
- 239000000696 magnetic material Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 239000010936 titanium Substances 0.000 claims description 18
- 238000003475 lamination Methods 0.000 claims description 15
- 238000000206 photolithography Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 238000004528 spin coating Methods 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 239000003292 glue Substances 0.000 claims description 7
- 238000007711 solidification Methods 0.000 claims description 7
- 230000008023 solidification Effects 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 238000010561 standard procedure Methods 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 238000009987 spinning Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- 238000006116 polymerization reaction Methods 0.000 description 4
- 238000005829 trimerization reaction Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
- H01F2027/2809—Printed windings on stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
- H01L2224/305—Material
- H01L2224/30505—Layer connectors having different materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
- H01L2224/80031—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by chemical means, e.g. etching, anodisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/8085—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/80855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/80862—Heat curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/36—Material effects
- H01L2924/364—Polymers
Abstract
在所描述的晶片级工艺上的电感器(100)的示例中,高导电层(107、114)、聚合物层(105、109、112、116)和磁芯(111)允许高频操作、低RDSON值和高效率。
Description
技术领域
本申请一般涉及集成电感器,并且更具体地涉及将电感器集成到晶片级集成电路工艺中。
背景技术
电感器和变压器可以被用于很多不同类型的电路中。例如,电感器和变压器可以被用于射频(RF)电路和高频功率分布或转换系统,诸如DC-DC电压(或功率)转换器。当前,因各种理由,电压转换器可能不完全集成在芯片上。例如,所期望的操作频率可能需要基于电感器受约束的物理尺寸不能获得的电感值。另外,特别地,基于涡流效应,片上电感器可不具有用于RF或高频电压转换应用的足够高的操作频率。
通过集成电力系统,优势包括处于与由此供电的(一个或多个)电路相同的管芯上的DC-DC电压转换器。例如,当处理器技术缩小到更小的尺寸时,到处理器内的电路的电源电压也可以缩小到更小的值。然而,随着尺寸减小,处理器的功率消耗可能增加。通过使用管芯外电压转换器以大的功率消耗将小的电源电压提供到处理器,大的总电流被供应到处理器。因为每个管脚具有最大电流处理能力,所以这可能增加每个管脚的电流,或增加向处理器供电所需的管脚的总数量。而且,电源电流的增加能够导致各种管芯外和管芯上互连件两端的电阻和电感电压降的增加,并且导致去耦电容器的较高的成本,通过将电压转换器集成到管芯上,可以减轻这些问题和其它问题。
常规的电压调节器被构建有离散电感器。这些调节器的频率一直在增加。通过增加频率,允许所需要的电感减小。如果切换频率是20MHz,则所需要的电感器是~100nH。
发明内容
在所描述的晶片级工艺上的电感器的示例中,高导电层、聚合物层和磁芯允许高频操作、低RDSON值和高效率。
附图说明
图1、图2和图3是根据示例实施例的电感器的制造步骤的说明。
图3AA是图3的截面A-A的横截面视图。
图3BB是图3的截面B-B的横截面视图。
具体实施方式
在附图中,相同的附图标记有时被用于指定相同的元件。图中的描述是示意性的且未按比例。示例实施例包含使用晶片级工艺制造片上电感器的技术,以及允许高频操作、低RDSON值和高效率的电感器设计。本文中描述了用于集成电路中的电感器的层压磁性材料(laminated magnetic material)及其制造的方法的实施例。
在至少一个实施例中,电感器可以包括层压材料结构,以减小其中的涡流,在高频下,涡流可以限制电感器的操作。电感器可以包括基本上或完全围绕磁性材料的金属线。电感器还可以包括一个层压磁层或多个层压磁层,一个层压磁层或多个层压磁层可以进一步包括更高的电阻或绝缘体层。层压磁层的增加的电阻可以减小电感器内的涡流,并且随后提高电感器在较高频率下的性能。实施例可以采用电镀、无电镀(electro less plating)或溅射技术,以形成一个或多个磁性材料层,以及具体地那些层邻近绝缘体层。
图3AA和图3BB分别是图3的截面A-A和截面B-B的横截面视图。在示例实施例100中,图3AA具有硅晶片基板101。有源区102包括通过导电互连层103耦合的晶体管、二极管、电容器和电阻器以形成有源电路。有源区102接触硅晶片基板的顶部表面,并且包括第一多个接合触点(bond contact)104。导电互连层103能够包括其间具有绝缘层的多个导电材料层。多个导电材料层能够经由刺穿它们的相关联的绝缘层的多个通孔耦合在一起。导电互连层103的顶部是绝缘层,具有开口,以暴露第一多个接合触点104。并且,导电互连层的顶部上的绝缘层能够被氮化硅层106覆盖,氮化硅层106具有开口,以暴露第一多个接合触点104。
第一聚合物层105能够沉积在氮化硅层的顶部上,并且还包括从第一聚合物层的顶部向下延伸到第一多个接合触点104的第一多个开口。第一聚合物层105能够充当电感器和硅晶片之间的应力缓解层(relief layer)。第一聚合物层105的厚度能够是在5μm-15μm之间。这还能够用于减少在铜绕组和硅晶片基板101之间的耦合。能够从聚合物SU8或PI-2622的组中选取第一聚合物层。
第一高电导材料层107(图1)能够沉积在第一聚合物层105的顶部表面上,填充第一聚合物层中的开口,从而将第一高电导材料层107耦合到第一多个接合触点104。第一高电导材料层107还能够被配置为形成多个下部线圈构件,并且还包括第二多个接合触点108。第一高电导材料层107能够包括具有20μm的厚度的铜。
第二聚合物层109接触第一聚合物层105和第一高电导材料层107。第二聚合物层的顶部表面是平坦的。第二聚合物层109能够包括从第二聚合物层109的顶部表面向下延伸到第二多个触点108的开口。能够用第一多个通孔110填充第二聚合物层中的开口。第一多个通孔110能够是铜。能够从聚合物SU8 3000或PI-2622的组中选取第二聚合物层109。
交替的磁性材料和绝缘材料的多个层111(图2)能够被沉积和限定在第二聚合物层109的顶部表面上。如所限定的,交替的磁性材料和绝缘材料的多个层111不接触暴露在第二聚合物层109的顶部表面上的第一多个通孔110。
每个磁膜层能够具有从0.1μm到3μm的范围的厚度,每个磁膜层之间具有10nm AIN电介质。能够从Ni80Fe20、Co90Ta5Zr5或FeAIN的组中选择磁层。层压磁芯总厚度能够是在5μm-15μm之间。
接下来,第三聚合物层112能够被沉积,接触第二聚合物层109和交替的磁性材料和绝缘材料的多个层111的顶部。第三聚合物层能够包括从第三聚合物层112的顶部表面向下延伸到第一多个通孔110的顶部表面的开口。
第二高电导材料层114(图3)能够被沉积在第三聚合物层112的顶部表面上。第二高电导材料层114填充第三聚合物层112中的开口,从而将第二高电导材料层114耦合到第一多个接合触点104。第三高电导材料层114还能够被配置为形成多个上部线圈构件,并且还包括第三多个接合触点115。第二高电导材料层114能够包括具有20μm的厚度的铜。
接下来,第四聚合物层116能够被沉积,接触第三聚合物层112和第二高电导材料层114的顶部。第四聚合物层能够包括从第四聚合物层112的顶部表面向下延伸到第二高电导材料层114的开口。能够用焊锡球116填充第四聚合物层中的开口。焊锡球提供到外部电路系统的连接。
根据另一个实施例,通过提供常规形成的集成电路晶片101、集成电路晶片102和集成电路晶片103,制造晶片级集成电感器。通过导电互连层103的顶部处的绝缘层中的开口暴露集成电路中的每个集成电路的接合触点104。
在晶片上方沉积氮化硅层,氮化硅层接触导电互连层103的顶部处的绝缘层和通过导电互连层103的顶部处的绝缘层中的开口暴露的接合焊盘104。使用图案化和刻蚀工艺,通过氮化硅层中的开口暴露接合触点104。
从聚合物SU8或PI-2622的组中选取的第一聚合物层105被旋涂到晶片上。
如果旋涂到晶片上的第一聚合物层105是PI-2622,则然后烘烤(bake)第一聚合物层105,以使其固化。将图案化的硬掩膜沉积在晶片上,接触第一聚合物105的顶部表面。将开口刻蚀到第一聚合物层105中,开口从第一聚合物层105的顶部表面向下延伸到多个接合触点104。第一聚合物层被配置为充当电感器和硅晶片之间的应力缓解层。第一聚合物层的厚度是在5μm-15μm之间。然后,移除硬掩膜。
如果旋涂到晶片上的第一聚合物层105是SU8,则然后软烘烤第一聚合物层105。沉积和图案化光刻胶层,其中由光源发生曝光。在曝光之后,执行后曝光烘烤。然后显影光刻胶和未曝光的SU8。在显影之后,然后硬烘烤SU8。在显影工艺之后,曝光于光源的SU8将保留在晶片上。
将Ti/Cu的第一籽晶层溅射到第一聚合物层105的顶部表面上。
使用标准光刻工艺,将光刻胶层旋涂到晶片上且将光刻胶层图案化。
然后,将第一高电导材料层107电镀到光刻胶的表面上,并且进入到由光刻胶限定的开口区域中,接触第一聚合物层105上的第一籽晶层以及限定包括第二多个触点108的多个下部线圈构件107并填充在第一聚合物层105中的开口,从而将第一高电导材料层耦合到第一多个接合触点104。第一高电导材料层能够由20μm的铜组成。使用标准光剥离(photostripping)方法,剥离光刻胶层。在光刻胶剥离之后,干法刻蚀所暴露的第一籽晶层。
将第二聚合物层109旋涂到晶片上,并且烘烤第二聚合物层109,以固化聚合物层。将图案化的硬掩膜沉积在晶片上,接触第二聚合物109的顶部表面。将开口刻蚀到第二聚合物层109中,开口从第二聚合物层109的顶部表面向下延伸到多个接合触点108。然后,移除硬掩膜。
能够从聚合物SU8 3000或PI-2622的组中选取第二聚合物层109。如果使用PI-2622,则CMP工艺能够被用于使表面平坦化。如果使用SU8 3000替代PI-2622用于第二聚合物层109,则因为SU8 3000大部分自平坦化到所需的容差,所以不需要CMP。
将Ti/Cu的第二籽晶层溅射到第二聚合物层109的顶部表面上,接触第二聚合物层109和第二多个触点108的顶部。
使用标准光刻工艺,将光刻胶层旋涂到晶片上且将光刻胶层图案化。
然后,将高电导材料层电镀到由光刻胶限定的开口区域中,接触第二聚合物层109上的第二籽晶层,填充第二聚合物层109中的开口,限定第一多个通孔110,从而将多个通孔耦合到第一多个接合触点104。第二高电导材料层能够由20μm的铜组成。使用标准光剥离方法剥离光刻胶层。在光刻胶剥离之后,干法刻蚀所暴露的第一籽晶层。
将钛层溅射到第二聚合物层的顶部表面上,接触第二聚合物层和第一多个通孔110的顶部。
在磁场中,能够使用Veeco Nexus PVDi工具,将包括交替的磁性材料和绝缘材料的多个层(图2)的层压磁芯111沉积在钛层的顶部表面上。交替的磁性材料和绝缘材料的多个层111被限定为不接触在第二聚合物层109的顶部表面上暴露的第一多个通孔110。
每个磁膜层能够被溅射具有从0.1μm到3μm的范围的厚度,每个磁膜层之间具有10nm AIN电介质。能够在磁场存在的情况下进行溅射,以确定磁性材料的易轴(easyaxis)。取向使得在交替的磁性材料和绝缘材料的多个层111中的B场在难轴(hard axis)的方向。磁层能够从Ni80Fe20、Co90Ta5Zr5或FeAIN的组中选择。在溅射之后,在磁场的存在的情况下,磁层能够经受退火(300-500C)。这用于进一步限定易轴/难轴。层压磁芯111总厚度能够在5μm-15μm之间。
能够使用标准光刻胶工艺,图案化和刻蚀层压磁芯111。然后,能够刻蚀交替的磁性材料和绝缘材料的多个层和Ti粘合层。然后使用标准技术剥离光刻胶。
将第三聚合物层112旋涂到晶片上,并且烘烤第三聚合物层112,以使聚合物层固化。将图案化的硬掩膜沉积在晶片上,接触第三聚合物层112的顶部表面。将开口刻蚀到第三聚合物层112中,开口从第三聚合物层112的顶部表面向下延伸到第一多个通孔110。然后移除硬掩膜。
将Ti/Cu的第三籽晶层溅射到第三聚合物层112的顶部表面上,接触第三聚合物层112和第一多个通孔110的顶部。
使用标准光刻工艺,将光刻胶层旋涂到晶片上且将光刻胶层图案化。
然后,将第二高电导材料层114电镀到光刻胶的表面上,并且进入由光刻胶限定的开口区域中,接触第三聚合物层112上的第三籽晶层,以及限定包括第二多个触点115的多个上部线圈构件114,并填充第三聚合物层112中的开口,从而将第二高电导材料层耦合到第一多个接合触点104。第二高电导材料层能够由20μm的铜组成。使用标准光剥离方法剥离光刻胶层。在光刻胶剥离之后,干法刻蚀所暴露的第一籽晶层。
将第四聚合物层116旋涂到晶片上,并且烘烤第四聚合物层116,以使聚合物层固化。将图案化的硬掩膜沉积在晶片上,接触第四聚合物层116的顶部表面。将开口刻蚀到第三聚合物层116中,开口从第四聚合物层116的顶部表面向下延伸到第二多个触点115。然后移除硬掩膜。
在磁场(0.1-1T)存在的情况下,磁层能够经受第二退火(300-500C)。这用于进一步限定易轴/难轴。
最终,在形成于第四聚合物层116中的开口中形成焊接凸块,接触第三高电导材料层114,从而耦合到第一多个接合触点104。
相应地,在所描述的示例中,集成磁性设备包括硅晶片基板。有源区在其上包括由导电互连层耦合的晶体管、二极管、电容器和电阻器以形成有源电路。有源区接触硅晶片基板的顶部表面,并且包括第一多个接合触点。导电互连层包括其间具有绝缘层的多个导电材料层,多个导电材料层通过刺穿它们的相关联的绝缘层的第一多个通孔耦合在一起。导电互连层的顶部是绝缘层,具有开口,以暴露第一多个接合触点。进一步地,集成磁性设备包括氮化硅层,该氮化硅层覆盖并接触绝缘层,也具有开口,以暴露第一多个接合触点。第一聚合物层沉积在氮化硅层的顶部上,包括从第一聚合物层的顶部向下延伸到第一多个接合触点的第一多个开口。第一高电导材料层沉积在第一聚合物层的顶部表面上,填充第一聚合物层中的第一多个开口,形成第二多个通孔,从而将第一高电导材料层耦合到第一多个接合触点。第一高电导材料层被配置为形成多个下部线圈构件,并且还包括第二多个接合触点。第二聚合物层接触第一聚合物层和第一高电导材料层。第二聚合物层的顶部表面是平坦的。第二聚合物层包括从第二聚合物层的顶部表面向下延伸到第二多个接合触点的第二多个开口。用第三多个通孔填充第二聚合物层中的第二多个开口。交替的磁膜材料和绝缘材料的多个层被沉积和限定在第二聚合物层的顶部表面上。如所限定的,交替的磁膜材料和绝缘材料的多个层不接触暴露在第二聚合物层的顶部表面上的第三多个通孔。第三聚合物层被沉积接触第二聚合物层和交替的磁性材料和绝缘材料的多个层的顶部。第三聚合物层包括从第三聚合物层的顶部表面向下延伸到第三多个通孔的顶部表面的第三多个开口。第二高电导材料层被沉积在第三聚合物层的顶部表面上。第二高电导材料层填充第三聚合物层中的第三多个开口,形成第四多个通孔,从而将第二高电导材料层耦合到第一多个接合触点。第三高电导材料层被配置为形成多个上部线圈构件,并且还包括第三多个接合触点。第四聚合物层被沉积接触第三聚合物层和第二高电导材料层的顶部。第四聚合物层包括从第四聚合物层的顶部表面向下延伸到第二高电导材料层的开口。用焊锡球填充第四聚合物层中的开口,这提供到外部电路系统的连接。
在其它所描述的示例中,形成集成磁性设备的方法包含提供常规形成的集成电路晶片。通过导电互连层的顶部处的绝缘层中的开口暴露集成电路中的每个集成电路的接合触点。该方法包含在晶片上沉积和限定氮化硅层,其中氮化硅层接触导电互连层的顶部处的绝缘层,并且暴露通过导电互连层的顶部处的绝缘层中的开口暴露的接合焊盘。通过使用图案化和刻蚀工艺,通过氮化硅层中的开口暴露接合触点。并且,该方法包含将第一聚合物层旋涂和图案化到晶片上,该第一聚合物层从聚合物SU8或PI-2622的组中选取;将Ti/Cu的第一籽晶层溅射到第一聚合物层的顶部表面上;以及使用标准光刻工艺,将光刻胶层旋涂和图案化到第一籽晶层上。进一步地,该方法包含将第一高电导材料层电镀到光刻胶的表面上,并且进入到由光刻胶限定的开口区域中,接触第一籽晶层,并且限定包括第二多个触点的多个下部线圈构件,以及填充第一聚合物层中的第一多个开口,从而将第一高电导材料层耦合到第一多个接合触点。而且,该方法包含使用标准光刻胶剥离方法剥离光刻胶层,并且干法刻蚀所暴露的第一籽晶层;将第二聚合物层旋涂到晶片上,并且烘烤第二聚合物层,以使聚合物层固化;以及将图案化的硬掩膜沉积在晶片上,接触第二聚合物的顶部表面。将第二多个开口刻蚀到第二聚合物层中,第二多个开口从第二聚合物层的顶部表面向下延伸到第二多个触点。并且,该方法包含移除硬掩膜;将Ti/Cu的第二籽晶层溅射到第一聚合物层的顶部表面上;使用标准光刻工艺,将光刻胶层旋涂和图案化到第二籽晶层上;将高电导材料层电镀到由光刻胶限定的开口区域中,接触第二籽晶层,并且限定第一多个通孔,从而将第一多个通孔耦合到第一多个接合触点。进一步地,该方法包含使用标准光刻胶剥离方法剥离光刻胶层,并且干法刻蚀所暴露的第二籽晶层;将钛层溅射到第二聚合物层的顶部表面上,接触第二聚合物层和第一多个通孔的顶部;以及在磁场中,使用VeecoNexus PVDi工具,将层压磁芯沉积在钛层的顶部表面上,该层压磁芯包括交替的磁膜材料和绝缘材料的多个层。交替的磁性材料和绝缘材料的多个层被限定为不接触在第二聚合物层的顶部表面上暴露的第一多个通孔。而且,该方法包含使用标准光刻胶工艺,图案化和刻蚀交替的磁性材料和绝缘材料的多个层和钛层。然后使用标准技术剥离光刻胶。并且,该方法包含将第三聚合物层旋涂到晶片上,并且烘烤第三聚合物层,以使聚合物层固化;将图案化的硬掩膜沉积在晶片上,接触第三聚合物的顶部表面,其中将第三多个开口刻蚀到第三聚合物层中,第三多个开口从第三聚合物层的顶部表面向下延伸到第一多个通孔;移除硬掩膜;将Ti/Cu的第三籽晶层溅射到第三聚合物层的顶部表面上;使用标准光刻工艺,将光刻胶层旋涂和图案化到第三籽晶层上;以及将第二高电导材料层电镀到光刻胶的表面上,并且进入到由光刻胶限定的开口区域中,接触第三籽晶层,并且限定包括第二多个触点的多个上部线圈构件,以及填充第三聚合物层中的第三多个开口,从而将第二高电导材料层耦合到第一多个接合触点。进一步地,该方法包含使用标准光刻胶剥离方法剥离光刻胶层,并且干法刻蚀所暴露的第一籽晶层;沉积第四聚合物层,接触第三聚合物层和第二高电导材料层,其中第四聚合物层包括从第四聚合物层的顶部表面向下延伸穿过第四聚合物层到第二高电导材料层的开口;在磁场(0.1-1T)存在的情况下,磁层经受第二退火(300-500C),其中第二退火进一步限定易轴/难轴;以及在形成于第四聚合物层中的开口中形成焊接凸块,接触第二高电导材料层。
在所描述的实施例中,修改是可能的,并且在要求保护的范围内其他实施例是可能的。
Claims (15)
1.一种集成磁性设备,包括:
硅晶片基板,有源区,所述有源区在其上包括通过导电互连层耦合的晶体管、二极管、电容器和电阻器以形成有源电路,其中所述有源区接触所述硅晶片基板的顶部表面,并且包括第一多个接合触点,其中所述导电互连层包括其间具有绝缘层的多个导电材料层,所述多个导电材料层通过刺穿它们的相关联的绝缘层的第一多个通孔耦合在一起,其中所述导电互连层的顶部是绝缘层,具有开口以暴露第一多个接合触点;
氮化硅层,所述氮化硅层覆盖并接触所述绝缘层,也具有开口,以暴露所述第一多个接合触点;
第一聚合物层,所述第一聚合物层沉积在所述氮化硅层的顶部上,包括从所述第一聚合物层的顶部向下延伸到所述第一多个接合触点的第一多个开口;
第一高电导材料层,所述第一高电导材料层沉积在所述第一聚合物层的顶部表面上,填充所述第一聚合物层中的所述第一多个开口,形成第二多个通孔,从而将所述第一高电导材料层耦合到所述第一多个接合触点,其中所述第一高电导材料层被配置为形成多个下部线圈构件,并且还包括第二多个接合触点;
第二聚合物层,所述第二聚合物层接触所述第一聚合物层和所述第一高电导材料层,其中所述第二聚合物层的顶部表面是平坦的,所述第二聚合物层包括从所述第二聚合物层的所述顶部表面向下延伸到所述第二多个接合触点的第二多个开口,其中用第三多个通孔填充所述第二聚合物层中的所述第二多个开口;
交替的磁膜材料和绝缘材料的多个层,所述交替的磁膜材料和绝缘材料的多个层被沉积和限定在第二聚合物层的所述顶部表面上,其中如所限定的,所述交替的磁膜材料和绝缘材料的多个层不接触暴露在所述第二聚合物层的所述顶部表面上的所述第三多个通孔;
第三聚合物层,所述第三聚合物层被沉积接触所述第二聚合物层和交替的磁性材料和绝缘材料的多个层的顶部,所述第三聚合物层包括从所述第三聚合物层的顶部表面向下延伸到所述第三多个通孔的顶部表面的第三多个开口;
第二高电导材料层,所述第二高电导材料层被沉积在所述第三聚合物层的所述顶部表面上,其中所述第二高电导材料层填充所述第三聚合物层中的所述第三多个开口,形成第四多个通孔,从而将所述第二高电导材料层耦合到所述第一多个接合触点,所述第三高电导材料层被配置为形成多个上部线圈构件,并且还包括第三多个接合触点;以及
第四聚合物层,所述第四聚合物层被沉积接触所述第三聚合物层和所述第二高电导材料层的顶部,其中所述第四聚合物层包括从所述第四聚合物层的顶部表面向下延伸到所述第二高电导材料层的开口,用焊锡球填充所述第四聚合物层中的所述开口,其中所述焊锡球提供到外部电路系统的连接。
2.根据权利要求1所述的集成磁性设备,其中所述第一聚合物层被配置为充当电感器和硅晶片之间的应力缓解层,其中所述第一聚合物层的厚度是在5μm-15μm之间,并且所述第一聚合物层从聚合物SU8或PI-2622的组中选取。
3.根据权利要求1所述的集成磁性设备,其中所述第二聚合物层从聚合物SU8 3000或PI-2622的组中选取。
4.根据权利要求1所述的集成磁性设备,其中每个磁膜层具有从0.1μm到3μm的范围的厚度,所述每个磁膜层之间具有10nmAIN电介质,并且所述磁膜层的构成从Ni80Fe20、Co90Ta5Zr5或FeAIN的组中选择。
5.根据权利要求1所述的集成磁性设备,其中所述层压磁芯总厚度是在5μm-15μm之间。
6.根据权利要求1所述的集成磁性设备,其中所述第一高电导材料层和所述第二高电导材料层包括具有20μm的厚度的铜。
7.一种形成集成磁性设备的方法,包括:
提供常规形成的集成电路晶片,其中通过在导电互连层的顶部处的绝缘层中的开口暴露集成电路中的每个集成电路的接合触点;
在晶片上沉积和限定氮化硅层,其中所述氮化硅层接触所述导电互连层的所述顶部处的所述绝缘层,并且暴露通过在所述导电互连层的所述顶部处的所述绝缘层中的所述开口暴露的所述接合焊盘;以及通过使用图案化和刻蚀工艺,通过所述氮化硅层中的开口暴露所述接合触点;
将第一聚合物层旋涂和图案化到所述晶片上,所述第一聚合物层从聚合物SU8或PI-2622的组中选取;
将Ti/Cu的第一籽晶层溅射到所述第一聚合物层的顶部表面上;
使用标准光刻工艺,将光刻胶层旋涂和图案化到所述第一籽晶层上;
将第一高电导材料层电镀到光刻胶的表面上,并且进入由所述光刻胶限定的开口区域中,接触所述第一籽晶层,并且限定包括第二多个触点的多个下部线圈构件,填充在所述第一聚合物层中的第一多个开口,从而将所述第一高电导材料层耦合到第一多个接合触点;
使用标准光刻胶剥离方法剥离所述光刻胶层,并且干法刻蚀所暴露的第一籽晶层;
将第二聚合物层旋涂到所述晶片上,并且烘烤所述第二聚合物层,以使所述聚合物层固化;
将图案化的硬掩膜沉积在所述晶片上,接触所述第二聚合物的顶部表面,其中将第二多个开口刻蚀到所述第二聚合物层中,所述第二多个开口从所述第二聚合物层的所述顶部表面向下延伸到第二多个触点;
移除所述硬掩膜;
将Ti/Cu的第二籽晶层溅射到所述第一聚合物层的所述顶部表面上;
使用标准光刻工艺,将光刻胶层旋涂和图案化到所述第二籽晶层上;
将高电导材料层电镀到由所述光刻胶限定的所述开口区域中,接触所述第二籽晶层,并且限定第一多个通孔,从而将所述第一多个通孔耦合到所述第一多个接合触点;
使用标准光刻胶剥离方法剥离所述光刻胶层,并且干法刻蚀所暴露的第二籽晶层;
将钛层溅射到所述第二聚合物层的所述顶部表面上,接触所述第二聚合物层和所述第一多个通孔的顶部;
在磁场中,使用Veeco Nexus PVDi工具,将层压磁芯沉积在所述钛层的顶部表面上,所述层压磁芯包括交替的磁膜材料和绝缘材料的多个层,其中交替的磁性材料和绝缘材料的多个层被限定为不接触暴露在所述第二聚合物层的所述顶部表面上的所述第一多个通孔;
使用标准光刻胶工艺,图案化和刻蚀所述交替的磁性材料和绝缘材料的多个层和所述钛层,其中然后使用标准技术剥离所述光刻胶;
将第三聚合物层旋涂到所述晶片上,并且烘烤所述第三聚合物层,以使所述聚合物层固化;
将图案化的硬掩膜沉积在所述晶片上,接触所述第三聚合物层的顶部表面,其中将第三多个开口刻蚀到所述第三聚合物层中,所述第三多个开口从所述第三聚合物层的所述顶部表面向下延伸到所述第一多个通孔;
移除所述硬掩膜;
将Ti/Cu的第三籽晶层溅射到所述第三聚合物层的所述顶部表面上;
使用标准光刻工艺,将光刻胶层旋涂和图案化到所述第三籽晶层上;
将第二高电导材料层电镀到所述光刻胶的所述表面上,并且进入由所述光刻胶限定的所述开口区域中,接触所述第三籽晶层,并且限定包括第二多个触点的多个上部线圈构件,以及填充所述第三聚合物层中的所述第三多个开口,从而将所述第二高电导材料层耦合到所述第一多个接合触点;
使用标准光刻胶剥离方法剥离所述光刻胶层,并且干法刻蚀所暴露的第一籽晶层;
沉积第四聚合物层,接触所述第三聚合物层和所述第二高电导材料层,其中所述第四聚合物层包括从所述第四聚合物层的顶部表面向下延伸穿过所述第四聚合物层到所述第二高电导材料层的开口;
在磁场存在的情况下,其中磁场为0.1-1T,磁层经受300-500C的第二退火,其中所述第二退火进一步限定易轴/难轴;以及
在形成于所述第四聚合物层中的所述开口中形成焊接凸块,接触所述第二高电导材料层。
8.根据权利要求7所述的形成集成磁性设备的方法,其中所述第二聚合物层从聚合物SU8 3000或PI-2622的组中选取,其中如果选取PI-2622,则使用CMP工艺以使表面平坦化,并且其中如果使用SU8 3000替代PI-2622用于所述第二聚合物层,因为SU8 3000大部分自平坦化到所需的容差,所以不需要CMP。
9.根据权利要求7所述的形成集成磁性设备的方法,其中每个磁膜层被溅射具有从0.1μm到3μm的范围的厚度,所述每个磁膜层之间具有10nm AIN电介质,其中总的层压磁芯厚度是在5μm-15μm之间,在磁场存在的情况下完成所述溅射,以确定磁性材料的所述易轴,并且其中取向使得所述交替的磁性材料和绝缘材料的多个层中的B场在所述难轴的方向上。
10.根据权利要求7所述的形成集成磁性设备的方法,其中所述磁膜层能够从Ni80Fe20、Co90Ta5Zr5或FeAIN的组中选择。
11.根据权利要求7所述的形成集成磁性设备的方法,其中在溅射之后,在磁场的存在的情况下,所述磁膜层接收300-500℃的退火,进一步限定所述易轴/难轴。
12.根据权利要求7所述的形成集成磁性设备的方法,其中所述第一高电导材料层和所述第二高电导材料层包括具有20μm的厚度的铜。
13.根据权利要求7所述的形成集成磁性设备的方法,其中所述第一聚合物层被配置为充当电感器和硅晶片之间的应力缓解层,其中所述第一聚合物层的厚度是在5μm-15μm之间,并且所述第一聚合物层从聚合物SU8或PI-2622的组中选取。
14.根据权利要求7所述的形成集成磁性设备的方法,其中所述第一聚合物层是PI-2622,并且在旋涂之后,接着烘烤所述第一聚合物层,以使所述聚合物层固化,将图案化的硬掩膜沉积在所述晶片上,接触所述第一聚合物层的所述顶部表面,其中将第一多个开口刻蚀到所述第一聚合物层中,所述第一多个开口从所述第一聚合物层的所述顶部表面向下延伸到多个接合触点,移除所述硬掩膜。
15.根据权利要求7所述的形成集成磁性设备的方法,其中所述第一聚合物层是SU8,在旋涂之后,接着软烘烤所述第一聚合物层,将光刻胶层沉积和图案化到所述晶片上,接触所述第一聚合物层的所述顶部表面,其中由光源发生曝光,在所述曝光之后,执行后曝光烘烤,其中然后显影所述光刻胶和未曝光的SU8,其中在显影之后,然后硬烘烤所述SU8,并且在所述显影工艺之后,曝光于所述光源的所述SU8将保留在所述晶片上。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/286,562 | 2014-05-23 | ||
US14/286,562 US20150340422A1 (en) | 2014-05-23 | 2014-05-23 | Method of manufacturing a micro-fabricated wafer level integrated inductor or transformer for high frequency switch mode power supplies |
PCT/US2015/032437 WO2015179863A1 (en) | 2014-05-23 | 2015-05-26 | Method of manufacturing a micro-fabricated wafer level integrated inductor or transformer for high frequency switch mode power supplies |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106463242A true CN106463242A (zh) | 2017-02-22 |
Family
ID=54554893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201580026307.1A Pending CN106463242A (zh) | 2014-05-23 | 2015-05-26 | 制造用于高频开关模式电源的微细加工的晶片级集成电感器或变压器的方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20150340422A1 (zh) |
EP (1) | EP3146538B1 (zh) |
CN (1) | CN106463242A (zh) |
WO (1) | WO2015179863A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109935451A (zh) * | 2017-12-19 | 2019-06-25 | 三菱电机株式会社 | 变压器、变压器的制造方法以及半导体装置 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9893141B2 (en) * | 2015-02-26 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Magnetic core, inductor, and method for fabricating the magnetic core |
US10269701B2 (en) * | 2015-10-02 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure with ultra thick metal and manufacturing method thereof |
WO2017177387A1 (zh) * | 2016-04-13 | 2017-10-19 | 深圳线易科技有限责任公司 | 可重构磁感应连接衬底和可重构磁性器件 |
EP3665767A1 (en) | 2017-08-07 | 2020-06-17 | Raytheon Company | Hereterogenously integrated power converter assembly |
US10340812B2 (en) | 2017-09-13 | 2019-07-02 | Raytheon Company | Flexible power converter architecture based on interposer and modular electronic units |
US10164001B1 (en) * | 2017-09-18 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure having integrated inductor therein |
KR102492733B1 (ko) | 2017-09-29 | 2023-01-27 | 삼성디스플레이 주식회사 | 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법 |
TWI643216B (zh) * | 2017-11-10 | 2018-12-01 | 瑞昱半導體股份有限公司 | 積體電感 |
US10741477B2 (en) * | 2018-03-23 | 2020-08-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods of forming the same |
US10748810B2 (en) * | 2018-05-29 | 2020-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing an integrated inductor with protections caps on conductive lines |
KR102615701B1 (ko) | 2018-06-14 | 2023-12-21 | 삼성전자주식회사 | 관통 비아를 포함하는 반도체 장치, 반도체 패키지 및 이의 제조 방법 |
US11538617B2 (en) * | 2018-06-29 | 2022-12-27 | Intel Corporation | Integrated magnetic core inductors on glass core substrates |
US20220216295A1 (en) * | 2021-01-07 | 2022-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inductor, semiconductor device including the same, and manufacturing method thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1081012A (zh) * | 1992-03-04 | 1994-01-19 | 安佩克斯系统公司 | 一种叠层高频磁性换能器及其制造方法 |
TW200427057A (en) * | 2003-05-27 | 2004-12-01 | Megic Corp | High performance system-on-chip inductor using post passivation process |
US20090068347A1 (en) * | 2007-09-10 | 2009-03-12 | Lotfi Ashraf W | Method of Forming a Micromagnetic Device |
US20110279214A1 (en) * | 2010-05-11 | 2011-11-17 | Dok Won Lee | High Frequency Semiconductor Transformer |
CN103579766A (zh) * | 2012-08-09 | 2014-02-12 | 株式会社村田制作所 | 天线装置、无线通信装置及天线装置的制造方法 |
US20140068932A1 (en) * | 2012-09-11 | 2014-03-13 | Ferric Semiconductor, Inc. | Magnetic Core Inductor Integrated with Multilevel Wiring Network |
CN103681633A (zh) * | 2012-09-04 | 2014-03-26 | 亚德诺半导体技术公司 | 磁芯及其形成方法,以及包括该磁芯的集成电路、衬底、变压器和电感器 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8178435B2 (en) * | 1998-12-21 | 2012-05-15 | Megica Corporation | High performance system-on-chip inductor using post passivation process |
US6255714B1 (en) * | 1999-06-22 | 2001-07-03 | Agere Systems Guardian Corporation | Integrated circuit having a micromagnetic device including a ferromagnetic core and method of manufacture therefor |
US6856228B2 (en) * | 1999-11-23 | 2005-02-15 | Intel Corporation | Integrated inductor |
US7943510B2 (en) * | 2007-09-10 | 2011-05-17 | Enpirion, Inc. | Methods of processing a substrate and forming a micromagnetic device |
US8169050B2 (en) * | 2008-06-26 | 2012-05-01 | International Business Machines Corporation | BEOL wiring structures that include an on-chip inductor and an on-chip capacitor, and design structures for a radiofrequency integrated circuit |
US8378766B2 (en) * | 2011-02-03 | 2013-02-19 | National Semiconductor Corporation | MEMS relay and method of forming the MEMS relay |
US9121106B2 (en) * | 2012-02-28 | 2015-09-01 | Texas Instruments Incorporated | Method of forming a laminated magnetic core with sputter deposited and electroplated layers |
CN204335178U (zh) * | 2012-08-09 | 2015-05-13 | 株式会社村田制作所 | 天线装置及无线通信装置 |
-
2014
- 2014-05-23 US US14/286,562 patent/US20150340422A1/en not_active Abandoned
-
2015
- 2015-05-26 EP EP15795680.6A patent/EP3146538B1/en active Active
- 2015-05-26 WO PCT/US2015/032437 patent/WO2015179863A1/en active Application Filing
- 2015-05-26 CN CN201580026307.1A patent/CN106463242A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1081012A (zh) * | 1992-03-04 | 1994-01-19 | 安佩克斯系统公司 | 一种叠层高频磁性换能器及其制造方法 |
TW200427057A (en) * | 2003-05-27 | 2004-12-01 | Megic Corp | High performance system-on-chip inductor using post passivation process |
US20090068347A1 (en) * | 2007-09-10 | 2009-03-12 | Lotfi Ashraf W | Method of Forming a Micromagnetic Device |
US20110279214A1 (en) * | 2010-05-11 | 2011-11-17 | Dok Won Lee | High Frequency Semiconductor Transformer |
CN103579766A (zh) * | 2012-08-09 | 2014-02-12 | 株式会社村田制作所 | 天线装置、无线通信装置及天线装置的制造方法 |
CN103681633A (zh) * | 2012-09-04 | 2014-03-26 | 亚德诺半导体技术公司 | 磁芯及其形成方法,以及包括该磁芯的集成电路、衬底、变压器和电感器 |
US20140068932A1 (en) * | 2012-09-11 | 2014-03-13 | Ferric Semiconductor, Inc. | Magnetic Core Inductor Integrated with Multilevel Wiring Network |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109935451A (zh) * | 2017-12-19 | 2019-06-25 | 三菱电机株式会社 | 变压器、变压器的制造方法以及半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
EP3146538A4 (en) | 2018-02-28 |
US20150340422A1 (en) | 2015-11-26 |
WO2015179863A1 (en) | 2015-11-26 |
EP3146538B1 (en) | 2020-07-08 |
EP3146538A1 (en) | 2017-03-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106463242A (zh) | 制造用于高频开关模式电源的微细加工的晶片级集成电感器或变压器的方法 | |
US9027229B2 (en) | Coil assembly comprising planar coil | |
JP6051359B2 (ja) | コア付きインダクタ素子およびその製造方法 | |
US8907447B2 (en) | Power inductors in silicon | |
US7666688B2 (en) | Method of manufacturing a coil inductor | |
JP4191506B2 (ja) | 高密度インダクタおよびその製造方法 | |
US8344478B2 (en) | Inductors having inductor axis parallel to substrate surface | |
US11393787B2 (en) | Conductor design for integrated magnetic devices | |
US20110310579A1 (en) | Inductive Structure and Method of Forming the Inductive Structure with an Attached Core Structure | |
EP1901353A2 (en) | Integrated passive devices with high Q inductors | |
US20080157273A1 (en) | Integrated electronic circuit chip comprising an inductor | |
US7897472B2 (en) | Apparatus and method for wafer level fabrication of high value inductors on semiconductor integrated circuits | |
KR100766213B1 (ko) | 전자 부품 | |
CN109524388B (zh) | 具有集成电感器的半导体结构 | |
JP2008171965A (ja) | 超小型電力変換装置 | |
US8907227B2 (en) | Multiple surface integrated devices on low resistivity substrates | |
TW201714383A (zh) | 無線充電裝置 | |
US20060017133A1 (en) | Electronic part-containing elements, electronic devices and production methods | |
JP2012129269A (ja) | コア付きインダクタ素子およびその製造方法 | |
JP5709434B2 (ja) | 電子装置とその製造方法 | |
WO2010147120A1 (ja) | コア付きインダクタ素子およびその製造方法 | |
JP2005044952A (ja) | コモンモードチョークコイル及びその製造方法並びにコモンモードチョークコイルアレイ | |
US20090243088A1 (en) | Multiple Layer Metal Integrated Circuits and Method for Fabricating Same | |
CN113016043B (zh) | 薄膜电感及其制作方法、集成电路、终端设备 | |
RU2474004C1 (ru) | Способ изготовления многоуровневых тонкопленочных микросхем |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170222 |