CN106462534B

CN106462534B - Link layer is to physical layer (PHY) serial line interface

Info

Publication number: CN106462534B
Application number: CN201580031992.7A
Authority: CN
Inventors: T·B·兰博尔; N·V·丹恩; S·沙赫鲁尼亚
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2014-06-16
Filing date: 2015-06-16
Publication date: 2019-07-16
Anticipated expiration: 2035-06-16

Abstract

A kind of link layer is disclosed to physical layer (PHY) serial line interface.On the one hand, system on chip (SoC) integrated circuit (IC) includes link layer circuit, and remote I C includes universal serial bus (USB) PHY circuit.Bus with four or less conducting wires connects the two IC.Chain road and bridge communicate with link layer circuit and are serialized as USB transceiver macro cells interface (UMTI) signaling received from the link layer circuit to be used for transmission high speed (HS) USB message of remote I C.The chain road and bridge also receive HS message from the USBPHY circuit on remote I C.The chain road and bridge de-serialize HS message to extract UTMI signaling and extracted UTMI signaling is passed to the link layer circuit.

Description

Link layer is to physical layer (PHY) serial line interface

Priority claim

This application claims submission on June 16th, 2014 and entitled " USB LINK TO PHY SERIAL INTERFACE The U.S. Provisional Patent Application S/N.62/012 of (USB link to PHY serial line interface) ", 888 priority, content is by drawing With by all is included in this.

This application claims entitled " the LINK LAYER TO PHYSICAL LAYER (PHY) submitted on June 15th, 2015 The U.S. Patent application S/N.14/739,439's of SERIAL INTERFACE (link layer to physical layer (PHY) serial line interface) " Priority, all is included in this by quoting for this application.

Background

I., field is disclosed

The technology of the disclosure relates generally to the communication between link layer and physical layer.

II. background technique

It calculates equipment and has become very universal in contemporary society.These calculate equipment dependence microprocessor and other are integrated Circuit (IC).In mobile computing device (as smart phone) and static calculation equipment (such as desktop computer) the two, exist Reduce the general trend of the size of such IC.As equipment size reduces, the voltage carried on builtin voltage rail also reduces.

Although the voltage in IC in Voltage rails generally reduces, some IC include the physical layer for requiring higher signaling voltage (sometimes referred to as PHY).For example, system on chip (SoC) may have features designed to remote peripheral device (for example, memory, mouse Mark, keyboard or similar devices) communication universal serial bus (USB) physical layer.USB requires 3.6 volts generally to be used for signaling.If Voltage rails carry 1.8 volts, then then requiring have voltage multiplie in the case where the physical layer is still in IC.If Voltage rails carry 1.2 volts, then then requiring have voltage tripler in the case where the physical layer is still in IC.Such voltage multiplication structure is not It must be reliable.

One solution of the voltage problem is the individual IC that moves to physical layer except SoC IC (for example, power Manage integrated circuit (PMIC)) and between the two IC there is link layer to bridge to physical layer.However, many link layers arrive Physical layer protocol requires multiple channels or channel.For example, USB transceiver macro cells interface (UTMI) has 32 (32) A channel, and UTMI+ can have the channel that up to 56 (56) are a.Under normal circumstances, the dedicated electrical connection (example of channel requirements Such as, conducting wire), and USB physical layer thus may require that in SOC IC and PHY IC the two there is 32 from link layer removal Pin.So many pin can not be exclusively used in relatively secondary interface (such as, USB) by common SoC IC.

Various solutions have been proposed to solve the problems, such as this, including the low pin interface of UTMI+ (ULPI), serial chain Road phy interface (SLPI) and Embedded USB 2 (eUSB).ULPI still require that eight or 12 pins and have been found for It is commercially unpractical for IC to IC communication.SLPI requires nothing more than two pins, is used with difference modes.However, SLPI define for register access four kinds of signaling methods and for data transmitting two kinds of signaling methods, this by Confirmation is unmanageable.Similarly, eUSB is used in single-ended mode using two pins for a type of signaling The two pins, and it is directed to another type of signaling, the two pins are used in difference modes.State machine tracking activity with Determine which kind of mode just used.It is final as a result, eUSB has a kind of signaling method for register access, for data There are two types of signaling methods for transmitting tool, and there are two types of signaling methods for the tool of the transmitting for controlling information.A variety of signalings in eUSB Method is heavy.Further, SLPI and eUSB defines the electrical interface for requiring the analog circuitry system in SoC IC, the simulation Circuit system is for functions such as differential driver, differential receivers, differential termination and squelch detections.PHY is moved into SIC An advantage of IC is to reduce the amount of Analog Circuit Design required on SoC IC.By keeping the simulation function on SoC IC Can, the advantages of PHY is moved to SoC IC, does not fully achieve.Correspondingly, however it remains for low pin count, simple signaling side Case, with the demand for allowing the link between multiple IC to communicate to PHY.

It is open to summarize

Aspects disclosed in detailed description includes link layer to physical layer (PHY) serial line interface.In illustrative aspect, System on chip (SoC) integrated circuit (IC) includes link layer circuit, and remote I C includes universal serial bus (USB) PHY electrical Road.Bus with four or less conducting wires connects the two IC.Chain road and bridge communicate with link layer circuit and will be received from these USB transceiver macro cells interface (UMTI) signaling of link layer circuit is serialized as being used for transmission the high speed of remote I C (HS) message.The chain road and bridge also receive HS message from the USB PHY circuit on remote I C.The chain road and bridge de-serialize HS message To extract UTMI signaling and extracted UTMI signaling passed to the link layer circuit.By the way that UTMI is believed in this way Order is serialized into HS message, and the number of the conducting wire between two IC is minimized and the number can be down to single conducting wire.It is logical The electrical interface that definition requires nothing more than numeral input/output (I/O) pad is crossed, the analog circuitry system for being used for USB is required in SoC IC Quantity be significantly reduced.Further, control information and data is come by using HS message, neither requires USB PH circuit The knowledge of state does not require complicated synchronization scheme yet.Further, allow the relatively quick turnaround time using HS message, This can satisfy relatively stringent latency requirement.

In this regard, on the one hand, a kind of IC is provided.The IC includes link layer circuit.The IC further includes operatively coupling Close the chain road and bridge of the link layer circuit.The chain road and bridge include serialiser.The IC further includes being operatively coupled to chain road and bridge Bus interface.The bus interface is configured to couple to there are four tools or the bus in less channel.The serialiser configures bunchiness The UTMI signaling that rowization receives at the chain road and bridge from the link layer circuit.The chain road and bridge are configured to transmit to the bus interface Serialized UTMI signaling is for using HS message by the bus transfer to long-range PHY chip.The UTMI signaling is selected from packet Include the group of UTMI control, low speed (LS) data and full speed (FS) data.

On the other hand, a kind of IC is provided.The IC includes PHY circuit.The IC further includes being operatively coupled to the PHY electrical The PHY bridge on road.The PHY bridge includes serialiser.The IC further includes the USB interface for being configured to couple to usb bus.The IC is also wrapped Include the bus interface for being operatively coupled to the PHY bridge.The bus interface is configured to couple to the total of there are four tools or less channel Line.The serialiser is configured to serialize the UTMI signaling received at the PHY bridge from the PHY circuit.The PHY bridge is configured to Serialized UTMI signaling is transmitted to the bus interface for using HS message to pass through the bus transfer to remote link layer core Piece.The UTMI signaling is selected from the group including UTMI control, LS data and FS data.

On the other hand, a kind of method for being communicated between PHY circuit and link layer is provided.This method packet It includes, at the first IC, serializes the UTMI signaling generated by link layer circuit.This method further includes across four or less conducting wires Bus is using serialized UTMI signaling as HS messaging to long-range PHY IC.It includes that UTMI is controlled that the UTMI signaling, which is selected from, System, the group of LS data and FS data.

Brief description

Fig. 1 is the exemplary conventional system on chip (SoC) wherein with both link layer circuit and physical layer (PHY) circuit The block diagram of integrated circuit (IC)；

Fig. 2 is according to the exemplary two-way single-ended single conductor link layer of the illustrative aspect of the disclosure to PHY serial line interface The block diagram of system；

Fig. 3 is according to the unidirectional single-ended links layer of exemplary two-conductor line of the illustrative aspect of the disclosure to PHY serial line interface The block diagram of system；

Fig. 4 is according to the exemplary two-conductor line two -way difference end link layer of the illustrative aspect of the disclosure to PHY serial interface The block diagram of port system；

Fig. 5 is serial to PHY according to the unidirectional Double deference end link layer of exemplary four conducting wire of the illustrative aspect of the disclosure The block diagram of interface system；

Fig. 6 is the diagram for explaining the signal relative time that grouping how is transmitted between the link layer and PHY in SoC IC；

Fig. 7 is the diagram for explaining the signal relative time how grouping is transmitted to link layer from PHY；

Fig. 8 is to explain the diagram for abiding by the signal relative time that (FS) signaling turnaround time requires at full speed；

Fig. 9 illustrates the structure of register packet command signal with tabular form；

Figure 10 illustrates the structure of control packet command signal with tabular form；And

Figure 11 illustrates the letter for being used to convey different the control groupings and symbol of UTMI signaling during USB reset operation The diagram of number relative time.

Detailed description

Referring now to attached drawing, several illustrative aspects of the disclosure are described.Wording " exemplary " is used for table herein Show " being used as example, example or explanation ".It is not necessarily to be construed as advantageous over or surpasses here depicted as any aspect of " exemplary " Other aspects.

Before being related to the illustrative aspect of the disclosure, the general view of conventional link layer to phy interface is provided referring to Fig.1. The discussion of the illustrative aspect of the disclosure starts referring to Fig. 2.

In this regard, Fig. 1 is the exemplary routine SoC IC wherein with 14 the two of link layer circuit 12 and PHY circuit 10 block diagram.SoC IC 10 further includes control system 16, can be microprocessor or similar.Link layer circuit 12 passes through total Line 18 is communicated with PHY circuit 14, which has conducting wire 20 (1) -20 (32) to carry UTMI signaling therebetween.It should lead Meeting, if UTMI+ is used to be communicated between link layer circuit 12 and PHY circuit 14, then bus 18 can have 50 Six (56) conducting wire (not shown).PHY circuit 14 communicated with the USB interface 22 for being coupled to USB connector 24 with remote peripheral Equipment (being not shown, such as memory component, keyboard, mouse or similar devices) communication.USB interface 22 may include that plug 26 is inserted into In socket therein, what this was well understood.Plug 26 may include four be bundled in cable 28 or five conductors.That is, big There are four most USB connector tools conductor (Vbus, D+, D-, ground connection), but mini USB (mini USB) and micro USB (micro USB) connector has the ID connector for indicating that it is type A or type B connector.USB 3.0 can have two A additional twisted pair (SSTx+, SST, SSRx+, SSRx-), what this was well understood.

With continued reference to Fig. 1, the presence of conducting wire 20 (1) -20 (32) allows UTMI signaling in link layer circuit 12 and PHY circuit It is effectively conveyed between 14.When link layer circuit 12 and PHY circuit 14 are on identical chips, such conducting wire 20 (1)-is used 20 (32) are optimal.However, the voltage that the transistor in SoC IC 10 is resistant to subtracts as equipment size continues to reduce It is small to 1.8 volts, or even 1.2 volts.As a comparison, the voltage of PHY circuit 14 is disposed and retained in 3.6 volts by USB standard. Designer is by the pressure for removing PHY circuit 14 from SoC IC 10 as a result,.However, the PHY circuit IC in removal (does not show It is unpractical for having 32 conducting wires between SoC IC 10 out), because can not bear will be as by general SoC IC Pin more than this is exclusively used in relatively secondary function, such as USB PHY to LI(link interface).Even if the low pin interface of UTMI (ULPI) Relatively low pin count it is too high for general SoC IC.

The illustrative aspect of the disclosure allows to remove PHY circuit from SoC IC, while making conducting wire in bus therebetween Number is minimized to the number that can be born by SoC IC.Additional aspect allows different voltage to be supplied to different IC, This provides better low-power and realizes.The further aspect of the disclosure allows the simplification between link layer circuit and PHY circuit Signaling, so that the mode of USB connector (for example, USB connector 24) is unimportant.The signaling of the simplification is still largely On remain explicit UTMI signaling between link and PHY.When retaining the help of UTMI signaling reduces required by circuit research and development Between and production debugging number because UTMI is well established in the industry.Numeral input/defeated is required nothing more than by definition The quantity of the electrical interface of (I/O) pad out, the analog circuitry system required in SoC IC is lowered.As final advantage, originally Disclosed illustrative aspect allows to abide by USB 2.0 completely, and specifically abides by the turnaround time required by USB 2.0 It realizes.The signaling interface of the simplification is sometimes referred to as UTMI serial line interface (USI) in the following figures.

In this regard, Fig. 2 is according to the exemplary two-way single-ended single conductor link layer of the illustrative aspect of the disclosure to PHY The block diagram of serial interface system 30.System 30 includes the SoC IC 32 and PHY IC 34 coupled by two-way single conductor bus 36. SoC IC 32, PHY IC 34 and two-way single conductor bus 36 can be placed on printed circuit board (PCB) 38, this is fine Understand.SoC IC 32 includes control system 40, which can be microprocessor or similar, and including control With status register (CSR), interrupt control unit (interruption) and phaselocked loop (PLL).SoC IC 32 further includes link layer circuit 42, And the chain road and bridge 44 of the link layer 42 are operatively coupled to by connection 46.In illustrative aspect, connection 46 includes 32 (32) conducting wire and thereon carrying UTMI signaling.In the illustrative aspect of replacement, connection 46 includes 56 (56) bar conducting wire And UTMI+ signaling is carried thereon.There are also the illustrative aspect of another replacement, connection 46 includes eight (8) items or 12 (12) conducting wire and thereon carrying ULPI signaling.Clock signal can be passed to chain road and bridge 44 by control system 40, and be posted Storage calling-on signal and/or interruption can also transmit between chain road and bridge 44 and control system 40.SoC IC 32 further includes operation It is coupled to chain road and bridge 44 and is configured to couple to the bus interface 48 of two-way single conductor bus 36 in ground.Bus interface 48, which can be, draws Foot.

With continued reference to Fig. 2, PHY IC 34 includes the bus interface 50 for being configured to couple to two-way single conductor bus 36.Always Line interface 50 can be pin.PHY bridge 52 is operatively coupled to bus interface 50.PHY IC 34 further includes by 56 behaviour of connection Make the PHY circuit 54 that ground is coupled to PHY bridge 52.In illustrative aspect, connection 56 includes 32 (32) bar conducting wire and thereon Carry UTMI signaling.In the illustrative aspect of replacement, connection 56 includes 56 (56) bar conducting wire and carrying UTMI+ believes thereon It enables.There are also another illustrative aspect, connection 56 includes eight (8) items or 12 (12) bar conducting wire and carrying ULPI believes thereon It enables.PHY circuit 54 is communicated with USB interface 58, the USB interface 58 can be similar to Fig. 1 USB interface 22 or with the USB of Fig. 1 The identical conventional USB interface of interface 22.

With continued reference to Fig. 2, chain road and bridge 44 receive UTMI signaling (as used herein, term from link layer circuit 42 UTMI includes UTMI 1.0, UTMI 1.05, UTMI+ and ULPI).UTMI signaling is serialized into HS message by serialiser 60, and And chain road and bridge 44 are configured to HS message transmission to bus interface 48 for being transferred to long-range PHY in two-way single conductor bus 36 IC 34.Deserializer 62 in chain road and bridge 44 is used passes through bus interface 48 from long-range PHY IC in two-way single conductor bus 36 The 34 HS message received, and the HS message received is de-serialized into the UTMI signaling for passing to link layer circuit 42. Similarly, PHY bridge 52 receives UTMI signaling from PHY circuit 54.UTMI signaling is serialized into HS message by serialiser 64, and PHY bridge 52 is configured to HS message transmission to bus interface 50 for being transferred to SoC IC 32 in two-way single conductor bus 36. Deserializer 66 in PHY bridge 52 is used passes through what bus interface 50 was received from SoC IC 32 in two-way single conductor bus 36 HS message, and the HS message received is de-serialized into the UTMI signaling for passing to PHY circuit 54.It will be appreciated that HS disappears Breath can be eight (8) bit symbols, command grouping or data grouping.

With continued reference to Fig. 2, two-way single conductor bus 36 allows the single-ended signaling between SoC IC 32 and PHY IC 34.Its His illustrative aspect allows different signals, and explains in figs. 3-5.However, most of elements be still it is identical and No longer describe.

In this regard, Fig. 3 is according to the unidirectional single-ended links layer of exemplary two-conductor line of the illustrative aspect of the disclosure to PHY The block diagram of serial interface system 70.Instead of the two-way single conductor bus 36 of system 30, system 70 includes two conductor bus 72, wherein Conducting wire 72A is the unidirectional single-ended connection for going to the transmission of PHY IC 34, and conducting wire 72B is for going to SoC IC 32 The unidirectional single-ended connection of transmission.In system 70, bus interface 48 and bus interface 50 can respectively include two pins.

Fig. 4 is according to the exemplary two-conductor line two -way difference end link layer of the illustrative aspect of the disclosure to PHY serial interface The block diagram of port system 80.Instead of two-way single conductor bus 36 or two conductor bus 72, system 80 includes two conductor bus 82, wherein The two conductor bus is the connection of two -way difference end.In system 80, bus interface 48 and bus interface 50 can respectively include two A pin.

Fig. 5 is serial to PHY according to the unidirectional Double deference end link layer of exemplary four conducting wire of the illustrative aspect of the disclosure The block diagram of interface system 90.Instead of two-way single conductor bus 36, two conductor bus 72 or two conductor bus 82, system 90 includes four Conductor bus 92, four conductor bus 92 include that the first unidirectional two-conductor line differential ends connection 94 goes to PHY IC's 34 with carrying HS message, and including the second unidirectional two-conductor line differential ends connection 96 to carry the HS message for going to SoC IC 32.In system 90 In, bus interface 48 and bus interface 50 can respectively include four pins.

Turning now to the HS message provided in bus 36,72,82 and 92, referring to table 1, the two of HS message is shown in table 1 Ary codes.

Table 1

Symbol/synchronization code word	Binary code (HS bit)
		j_smbl	1111 0000
k_smbl	1111 0100
		se0_smbl	1111 0101
dis_smbl	1111 1111
		cmd_sync	1010 1010 1001
dat_sync	1010 1010 1000

It as described in table 1, (is J, K, single-ended zero and disabling or j_smbl, k_smbl, se0_ respectively there are four symbols Smbl and dis_smbl), for command grouping command synchronization word (cmd_sync) and be used for HS data packets data synchronization character (dat_sync).The combination of the symbol and order allows UTMI signaling between SoC IC 32 and PHY IC 34 with acceptable Waiting time level is transmitted.Conducting wire and pin the permission cost of low number are controlled and circuit design keeps simple.It is below More specifically for the discussion of signaling.

Note that cmd_sync is 12 (12) bits.12 bit sync words allow receiving element to make its clock sum number It is locked according to recovery (CDR) circuit time.As a comparison, symbol is only eight (8) bits, this help meets full speed (FS) signaling Timing constraint and FS are grouped the turnaround time.It is transmitted between SoC IC 32 and PHY IC 34 using these symbols low speed (LS) With FS data grouping.J_smbl indicates J state, and k_smbl indicates K state, and se0_smbl indicates SE0 state, and dis_smbl refers to Show that PHY IC 34 should disable its output driver.Shorter symbol allows them to be decoded with the smallest waiting time.It is similar Ground, these symbols can be used to during USB operates (such as resetting, chirp, hang-up, recovery and Remote Wake Up) in SoC IC Transfer line status information between 32 and PHY IC 34.Using command grouping between SoC IC 32 and PHY IC 34 explicitly Transmit UTMI control signaling.Between each message, bus 36,72,82 or 92 is maintained in idle state and consumes most Small power.

In order to facilitate a better understanding of, Fig. 6, which explains how FS to be grouped from SoC IC 32, is transmitted to PHY IC 34 The diagram 100 of signal relative time.When link layer circuit 42 asserts link_txvalid UTMI signal 102, chain road and bridge 44 to PHY IC 34 sends a series of symbols (j_smbl and k_smbl) 104 for starting from the first j_smbl 106.First j_smbl 106 So that PHY IC 34 enables its output driver for marking usually at 108, (phy_ser_txen or PHY, which are serially transferred, to be made Can), and (will be marked usually at 110) on the D+/D- line of J state-driven to USB interface 58.By the connecing of sending of chain road and bridge 44 Seven symbols got off are output to the USB interface 58 of PHY IC 34 on D+/D- line USB FS synchronization character, wherein USB FS synchronization character includes KJKJKJKK (marking usually at 112).Chain road and bridge 44 are then in a series of symbols (j_smbl and k_ Smbl FS), which is sent, to PHY IC 34 in 116 is grouped payload 114.When link deasserts link_txvalid 118, Chain road and bridge 44 send the end of the series of packets of symbol 120 to PHY IC 34.First code element in these symbols is se0_smbl 122, make PHY IC 34 will be in the driving to D+/D- line of SE0 state 124.Second code element is j_smbl 126, and third yard Member is dis_smbl 128, the D+/D- for making PHY IC 34 stop driving USB interface 58 by disabling phy_ser_txen Line (marks) usually at 130.

Fig. 7 is to explain the signal relative time how LS and FS grouping is transmitted to link layer circuit 42 from PHY IC 34 Diagram 140.If PHY IC 34 not in the D+/D- line (that is, phy_ser_txen and not enabled) of driving USB interface 58, that When each PHY circuit 54 detects the transformation on the D+/D- line (usually marking at 142) of USB interface 58, PHY bridge 52 is just Corresponding symbol is sent to chain road and bridge 44.As a result, as commentary, when D+/D- line be converted to K state (usually at 144 mark Note) when, PHY bridge 52 to chain road and bridge 44 send k_smbl 146.Chain road and bridge 44 are then in UTMI signal (referred to as link_ Linestate [1:0]) on to link send K state.Subsequent transformation 148 and 150 generates j_smbl 152 and k_ respectively Smbl 154, and so on.When D+/D- line receives SE0 156, PHY bridge 52 sends se0_smbl 158.

Under usb protocol, when equipment, which receives FS from usb host, to be grouped, which is required be less than 6.5FS bit The grouping is responded in the turnaround time of time.The timing demands are illustrated in Fig. 8, Fig. 8 is the diagram 170 of signal relative time. The diagram 170 of signal relative time shows the end 172 of the SE0 on D+/D- line and opening for next K state on D+/D- line Time between beginning 174 is less than 6.5FS bit-time.As shown in table 2 below, the turn around latency packet of the 6.5FS bit-time It includes through PHY, PHY bridge, chain road and bridge, link, the delay of chain road and bridge, PHY bridge and PHY.Specifically, table 2 outlines hypothesis The source of delay in 60MHz period (herein be sometimes referred to as prds) and compare budget and this public affairs that UTMI 1.05 is distributed The budget (column of the maximum value of entitled recommendation) for the illustrative aspect opened.Fig. 8 is returned to, in order to reach the week of 6.5FS bit-time Turn the time, chain road and bridge 44 receive j_smbl 176 and export the time between J state 178 to link layer circuit 42 and are necessarily less than Two periods of 60MHz, or it is less than 16HS bit-time.Similarly, PHY bridge 52 receives k_smbl 180 and to PHY circuit 54 Time between output K state 182 is necessarily less than two periods of 60MHz, or is less than 16HS bit-time.If being used for j_smbl Have with the symbol of k_smbl and needs by the decoded synchronization character of ce circuit and payload, it may not be possible to meeting 16HS ratio The decoding time of special time.

Table 2

In order to avoid delay associated with ce circuit, the symbol in table 1 is defined such that they are short (only 8HS bit-time is long), and allow to minimum latency and decode them.A kind of method for decoding these symbols is to make With the circuit of property with the following functions.First functionality is on the rising and falling edges of 480MHz clock (can be generated by PLL) Bus 36,72,82 or 92 is sampled.If the functionality detect idle state followed by least three be 1 HS bit, So incoming message just not instead of command grouping or data grouping, are possibly used for the symbol or long pulse that reset or interrupt.The Two circuit functionalities 10HS bit-time after idle state terminates samples bus 36,72,82 or 92.If in 10HS The state of bus 36,72,82 or 92 is zero after bit-time, then incoming message is symbol and non-pulse.Tertiary circuit function Energy property has counted the number of the rising edge of the bus 36,72,82 or 92 since idle state.If there are two rising edge, that Symbol is k_smbl.If there are three rising edge, then symbol is se0_smbl.If there is a rising edge, then symbol is j_ Smbl or dis_smbl.If the first functionality sampled on the rising edge of 480MHz clock to bus 36,72,82 or 92 Detect that there are five the HS bit-times for being above 1 after idle state, then symbol is dis_smbl.Otherwise symbol is j_smbl.Such circuit has minimum latency and thus, it is possible to decode all codes in the time for being less than 16HS bit-time Member.

When one or more UTMI controls signal change at link, chain road and bridge 44 send command grouping to PHY bridge 52. PHY bridge 52 is responded with acknowledgement grouping.There are two kinds of command groupings, that is, register grouping and control grouping.In Fig. 9 Illustrate the format of register grouping.Similarly, the format of control grouping is illustrated in Figure 10.The grouping of both types all makes Start to be grouped with the cmd_sync of identical table 1.Similarly, the two groupings are 29 (29) bit longs.Register Grouping is used to from link layer circuit 42 from being read out in the register in PHY circuit 54 or to posting into PHY circuit 54 Storage is written.PHY IC 34 is grouped to respond back link layer circuit 42. with identical register write.If link layer circuit 42 are not received by having of returning from PHY IC 34 and transmitted identical value contracture group really, then link layer circuit 42 It is retried.If the event that must be communicated to link layer circuit 42 has occurred in PHY IC 34, then PHY IC 34 can be with Interruption pulse is sent to link layer circuit 42.Link layer circuit 42 by read PHY IC 34 in interrupt status register come It is responded.

As explained in Figure 10, control grouping convey from link layer circuit 42 several UTMI control signal (for example, Opmode, xcrsel, termsel, suspendm, txvalid and tdat), and the control letter of several UTMI from PHY circuit 54 Number (for example, linestate, hostdisc, iddig and bvalid).When the UTMI control signal from link layer circuit 42 changes When change, chain road and bridge 44 send control grouping to PHY bridge 52.Control grouping includes that the UTMI at link layer circuit 42 controls signal Latest value.When PHY bridge 52 receives control grouping, PHY bridge 52 applies newest UTMI output signal simultaneously to PHY circuit 54 And a bit of time is waited to change to wait the UTMI from PHY circuit 54 to control signal.After such time, PHY bridge 54, which send back control grouping to chain road and bridge 44, is used as acknowledgement.Original control grouping from chain road and bridge 44 has ack_req bit Group, the bit group indicate that chain road and bridge 44 it is expected acknowledgement grouping to PHY IC 34.When PHY bridge 52 sends back acknowledgement to chain road and bridge 44 When grouping, PHY bridge 52 does not need that ack_req bit is arranged in the control grouping for going to chain road and bridge 44.If chain road and bridge 44 do not have Acknowledgement grouping is received from PHY IC 34, is grouped then chain road and bridge 44 will retry its initial control.

If PHY bridge 52 is in control grouping from symbol is sent out while transmission chain road and bridge 44 to convey linear state (linestate) change, then PHY bridge 52 will not receive control grouping, acknowledgement, and 44 meeting of chain road and bridge will not be sent Retransmit its control grouping.When PHY bridge 52, which was received from chain road and bridge 44, retries control grouping, PHY bridge with acknowledgement grouping come Response.Because acknowledgement grouping includes updated value threadiness state, even if in the event of conflict, also in 34 He of PHY IC All UTMI control information are reliably exchanged between link layer circuit 42.

Further, it in the case where the definition of proposed control grouping, calls out in resetting, chirp, hang-up, recovery and remotely What the UTMI control event occurred during awake USB operation can be grouped between chain road and bridge 44 and PHY bridge 52 with two controls It exchanges and is steadily conveyed.As a comparison, if being grouped using register, then identical information require six grouping with And interruption pulse.This arrangement reduces the waiting time relative to some possible replacements as a result,.

Figure 11 is the signal phase for being used to convey different the control groupings and symbol of UTMI signaling during USB reset operation To the diagram 200 of time.Six lines 202 at top show the control signal of the UTMI at link.Next line 204 shows chain The message that road and bridge 44 send.Next line 206 shows the message of the transmission of PHY bridge 52.Then six lines 208 show PHY UTMI at IC 34 controls signal.Last line 210 shows the D+/D- line of USB interface 58.Control and acknowledgement grouping by with To convey the mode of UTMI signaling that can find out by examining typical transaction.Xcvrsel, opmode at chain road and bridge 44, The change 212 of txvalid and txdat causes chain road and bridge 44 to send single control grouping 214 to PHY bridge 52.PHY bridge 52 is subsequent more Newly go to the UTMI control signal 214 of chain road and bridge 44.The update is so that the value on D+/D- line changes 216, and then causes The change 218 of PHY threadiness state.PHY bridge 52 allows the time of this change before acknowledgement grouping 220 is sent back chain road and bridge 44 It completes.Acknowledgement grouping includes the latest value of the linear state from PHY bridge 52, thus chain road and bridge 44 can by K state this is newest Value 222 drives back chain road and bridge 44.

It can be provided in any processor-based equipment according to link layer disclosed herein to PHY serial line interface Or it is integrated into any processor-based equipment.Example not as restriction includes: that set-top box, amusement unit, navigation are set Standby, communication equipment, mobile position data unit, mobile phone, cellular phone, smart phone, is put down at fixed position data cell Plate, computer, portable computer, desktop computer, personal digital assistant (PDA), monitor, computer monitor, TV Machine, tuner, radio, satelline radio, music player, digital music player, portable music player, number view Frequency player, video player, digital video dish (DVD) player, portable digital video player and automobile.

Those skilled in the art will further appreciate that, in conjunction with the various illustrative logics of aspects disclosed herein description Block, module, circuit and algorithm can be implemented as electronic hardware, storage in memory or in another computer-readable medium and by The instruction or combination of the two that processor or other processing equipments execute.As an example, equipment described herein can be used in In any circuit, hardware component, IC or IC chip.Memory disclosed herein can be the storage of any type and size Device, and can be configured to store required any kind of information.This interchangeability for a clear explanation, it is above with its function The form of energy property generally describes various illustrative components, frame, module, circuit and step.How such functionality is implemented Depending on concrete application, design alternative, and/or the design constraint being added on total system.Technical staff can be directed to every kind of spy Described function is realized in fixed application in different method, but such realization decision is not to be read as causing a departure from the disclosure Range.

Various illustrative logical blocks, module and the circuit described in conjunction with aspects disclosed herein is available to be designed to The processor of execution functions described in this article, digital signal processor (DSP), specific integrated circuit (ASIC), scene can compile Journey gate array (FPGA) or other programmable logic device, discrete door or transistor logic, discrete hardware component or its What combination is to realize or execute.Processor can be microprocessor, but in alternative solution, and processor can be at any routine Manage device, controller, microcontroller or state machine.Processor is also implemented as calculating combination (such as the DSP and Wei Chu of equipment Manage combination, multi-microprocessor, the one or more microprocessors to cooperate with DSP core or any other such configuration of device).

Various aspects disclosed herein can be embodied as the instruction of hardware and storage within hardware, and can reside in for example Random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electric erazable programmable ROM (EEPROM), register, hard disk, removable disk, CD-ROM or any other form known in the art is computer-readable In medium.Exemplary storage medium is coupled to processor, so that processor can be believed from/to the storage medium read/write Breath.In alternative, storage medium can be integrated into processor.Pocessor and storage media can reside in ASIC. ASIC can reside in distant station.In alternative, pocessor and storage media can be used as discrete assembly reside in distant station, In base station or server.

It is also noted that operating procedure described in any illustrative aspect is to provide for example and discusses and retouched herein It states.Described operation can be executed by numerous different orders other than the sequence explained.In addition, in single operation Operating described in step can actually execute in multiple and different steps.In addition, one or more discussed in illustrative aspect A operating procedure can be combined.It should be understood that as apparent to those skilled in the art, the operating procedure explained in diagram It can carry out numerous different modifications.It will further be appreciated by those of ordinary skill in the art that any one of various different technologies can be used Indicate information and signal.For example, through the data that may be addressed always, instruction, order, information, signal, position is described above (bit), symbol and chip can be by voltage, electric current, electromagnetic wave, magnetic field or magnetic particle, light field or light particle or its any groups It closes to indicate.

Offer is to make any person skilled in the art all and can make or use this public affairs to the previous description of the disclosure It opens.The various modifications of the disclosure will be easy to those skilled in the art to be it will be apparent that and defined herein Generic principles can be applied to other modifications without departing from the spirit or scope of the disclosure.The disclosure is not intended to as a result, It is defined to example and design described herein, but should be awarded and principle disclosed herein and novel feature one The broadest range caused.

Claims

1. a kind of Integrated circuit IC, comprising:

Link layer circuit；

The chain road and bridge of the link layer circuit are operatively coupled to, the chain road and bridge include serialiser；And

Bus interface, be operatively coupled to the chain road and bridge and be configured to couple to tool there are four or less channel bus； And

Wherein the serialiser is configured to serialize the general string received at the chain road and bridge from the link layer circuit Row bus USB transceiver macro cells interface UTMI signaling, and the chain road and bridge are configured to transmit to the bus interface Serialized UTMI signaling for using high speed HS message by the bus transfer to remote physical layer PHY chip, wherein The UTMI signaling selection includes the group of UTMI control, low speed LS data and full speed FS data certainly.

2. Integrated circuit IC as described in claim 1, which is characterized in that the bus interface includes being used for two-way single-ended conducting wire Single pin.

3. Integrated circuit IC as described in claim 1, which is characterized in that the bus interface includes being used for two -way difference conducting wire Pair two pins.

4. Integrated circuit IC as described in claim 1, which is characterized in that the bus interface includes unidirectional single-ended for two Two pins of conducting wire.

5. Integrated circuit IC as described in claim 1, which is characterized in that the bus interface includes being used for two unidirectional difference Four pins of conducting wire pair.

6. Integrated circuit IC as described in claim 1, which is characterized in that the serialiser, which is configured to control UTMI, to be believed Breath, UTMI LS data and UTMI FS serial mode are melted into HS message.

7. Integrated circuit IC as described in claim 1, which is characterized in that the chain road and bridge include that be configured to will be received from described The deserializer of the HS message de-serialization of bus.

8. Integrated circuit IC as described in claim 1, which is characterized in that the UTMI signaling is UTMI+ signaling.

9. Integrated circuit IC as described in claim 1, which is characterized in that the chain road and bridge are configured to compile FS line status information For code at the HS message for the FS turnaround time for meeting USB 2.0, the FS threadiness state information includes J state, K state, SE0 and taboo With.

10. Integrated circuit IC as described in claim 1, which is characterized in that the chain road and bridge be configured to by measurement pulsewidth and Message is decoded to edge counting to meet the FS turnaround time of the USB 2.0.

11. a kind of Integrated circuit IC, comprising:

Physical layer PHY circuit；

It is operatively coupled to the PHY bridge of the PHY circuit, the PHY bridge includes serialiser；

General-purpose serial bus USB interface, the usb bus being configured to couple to；

Bus interface, be operatively coupled to the PHY bridge and be configured to couple to tool there are four or less channel bus；With And

Wherein the serialiser is configured to serialize the USB transceiver received at the PHY bridge from the PHY circuit macro Cellular cell interface UTMI signaling, and the PHY bridge is configured to transmit serialized UTMI signaling to the bus interface For using high speed HS message by the bus transfer to remote link layer chip, wherein UTMI signaling selection includes certainly UTMI control, low speed LS data and full speed FS data group.

12. a kind of method for being communicated between physical layer PHY circuit and link layer circuit, which comprises

At the first Integrated circuit IC, serialization is small by the general-purpose serial bus USB transceiver macrocellular that link layer circuit generates Area's interface UTMI signaling；And

Serialized UTMI signaling is given long-range PHY IC by bus across four or less conducting wires, Wherein the UTMI signaling selection includes the group of UTMI control, low speed LS data and full speed FS data certainly.

13. method as claimed in claim 12, which is characterized in that transmission includes being passed across the two-way single-ended bus of single conductor It send.

14. method as claimed in claim 12, which is characterized in that transmission includes that one across the unidirectional single-ended bus of two-conductor line leads Line is transmitted.

15. method as claimed in claim 12, which is characterized in that transmission includes across two -way difference conducting wire to being transmitted.

16. method as claimed in claim 12, which is characterized in that transmission includes across unidirectional differential conductor to being transmitted.

17. method as claimed in claim 12, which is characterized in that further compile J state, K state, SE0 and disabling signal Code at the FS turnaround time that can satisfy USB 2.0 state HS message.

18. method as claimed in claim 17, which is characterized in that further comprise by measurement pulsewidth and to edge counting come Decode the state HS message.

19. method as claimed in claim 12, which is characterized in that the transmission serialized UTMI signaling includes by UTMI + control event is transmitted as HS message.

20. method as claimed in claim 19, which is characterized in that further comprise as single HS message sink for described The response of UTMI+ control event.

21. method as claimed in claim 12, which is characterized in that further comprise, by FS threadiness state information coding at being short to Meet the HS message of the FS turnaround time of USB 2.0 enough, the FS threadiness state information includes J state, K state, SE0 and taboo With.

22. method as claimed in claim 12, which is characterized in that further comprise by the FS turnover to meet USB 2.0 The method measurement pulsewidth of time and message is decoded to edge counting.

23. method as claimed in claim 12, which is characterized in that further comprise:

At chain road and bridge, UTMI is conveyed to control event using single HS message；And

It is finally responded from the long-range PHY IC as single HS message sink, thus extensive in message or message collision from having abandoned It is multiple.