CN106449765A - Floating gate type flash memory structure and manufacture method thereof - Google Patents
Floating gate type flash memory structure and manufacture method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention discloses a floating gate type flash memory structure and a manufacture method thereof. A channel layer is formed on a substrate, and an ion injection region is respectively formed in the substrate and the channel layer; a grid electrode structure is arranged in a groove which runs through the channel layer and extends into the substrate, and comprises a control grid, an inter-grid medium layer and at least two floating gates; and a vertical channel is formed in the channel layer. Therefore, the floating gate type flash memory structure can be used for storing a plurality of bits in a single groove, and the control grid is shared, so that on the premise of not influencing device performance, the device size can be further reduced, the storage density of the device can be improved, the cost can be reduced, and the competitiveness can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a floating gate type flash memory structure and a manufacturing method thereof.
Background
Flash memory has become a hot point of research in non-volatile memories due to its advantages of convenience, high storage density, good reliability and the like. Since the first flash memory product appeared in the eighties of the twentieth century, with the development of technology and the demand of various electronic products for storage, flash memory is widely used in mobile and communication devices such as mobile phones, notebooks, palm computers, U disks and the like, the flash memory is a non-volatile memory, the operation principle of which is to control the on-off of a gate channel by changing the threshold voltage of a transistor or a memory cell so as to achieve the purpose of storing data, so that the data stored in the memory cannot disappear due to power interruption, and the flash memory is a special structure of an electrically erasable and programmable read-only memory. Flash memory now occupies a large portion of the market share of non-volatile semiconductor memory, becoming the fastest growing non-volatile semiconductor memory.
Fig. 1 is a schematic diagram of a conventional floating gate flash memory structure, which includes a tunnel oxide layer 11 deposited on a substrate 10, a floating gate 12 located right above the tunnel oxide layer 11, a control gate 14 stacked on the floating gate 12, an ONO (oxide-nitride-oxide) layer 13 disposed between the control gate 14 and the floating gate 12, and a source region a and a drain region B disposed on the substrate 10. Conventional floating gate type flash memory structures are lateral channel devices (i.e., drain/floating gate/source), and devices of such structures require additional area for the drain/source regions, thereby affecting the storage density of the devices. To increase the storage density of such devices, it is usually necessary to reduce the channel length and the drain/source width, but such improvements have the undesirable effects of short channel effect and low drain-source breakdown voltage, which are undesirable to those skilled in the art.
Disclosure of Invention
The invention aims to provide a floating gate type flash memory structure and a manufacturing method thereof, which can improve the storage density of a device, reduce the cost and improve the competitiveness on the premise of not influencing the performance of the device.
To solve the above technical problem, the present invention provides a floating gate flash memory structure, including:
the ion implantation device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein two ion implantation regions are arranged in the substrate;
the channel layer is positioned on the substrate and comprises at least one epitaxial layer, two epitaxial ion implantation regions are arranged in each epitaxial layer, and the two epitaxial ion implantation regions in the epitaxial layers are respectively positioned right above the two ion implantation regions in the substrate;
a groove, wherein the groove penetrates through the channel layer and extends into the substrate, and the groove is positioned between two ion implantation regions in the substrate;
the grid structure is arranged in the groove, one end of the grid structure extends into the substrate, and the other end of the grid structure is close to the upper surface of the channel layer; wherein,
the grid structure comprises a control grid, an inter-grid dielectric layer and at least two floating grids, the floating grids are arranged on two sides of the control grid, each floating grid is arranged on the side wall close to the groove, the control grid vertically penetrates through the channel layer, and the inter-grid dielectric layer isolates the control grid from each floating grid.
Preferably, in the floating gate type flash memory structure, each epitaxial layer corresponds to two floating gates, and the floating gates are respectively located at two sides of the control gate.
Optionally, in the floating gate flash memory structure, the channel layer includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located on the substrate, and the second epitaxial layer is located on the first epitaxial layer.
Furthermore, in the floating gate type flash memory structure, 4 floating gates are arranged in the gate structure, and every two floating gates are distributed up and down in parallel.
Further, in the floating gate type flash memory structure, the floating gate type flash memory structure further includes an insulating layer between the upper and lower adjacent floating gates.
Further, in the floating gate type flash memory structure, the floating gate type flash memory structure further includes a first oxide layer covering the bottom of the groove, a tunneling oxide layer on the sidewall of the groove, and a protection layer covering the gate structure.
Further, in the floating gate type flash memory structure, the substrate is a P-type silicon substrate.
Furthermore, in the floating gate type flash memory structure, the ion implantation region and the epitaxial ion implantation region are both N-type ion implantation regions.
According to another aspect of the present invention, the present invention further provides a method for manufacturing a floating gate type flash memory structure, including:
providing a substrate, carrying out ion implantation on the substrate, and forming two ion implantation areas on the substrate;
forming a channel layer, wherein the channel layer is positioned on the substrate and comprises at least one epitaxial layer;
forming a groove, wherein the groove penetrates through the channel layer and extends into the substrate, and the groove is positioned between the two ion implantation regions;
forming a floating gate layer in the groove, wherein the upper surface of the floating gate layer is lower than that of the channel layer, and the floating gate layer comprises at least one floating gate polycrystalline silicon layer;
etching the floating gate layer to form at least two floating gates;
forming an inter-gate dielectric layer and a control gate between the at least two floating gates, wherein the control gate vertically penetrates through the channel layer, and the inter-gate dielectric layer isolates the control gate from each floating gate to form a gate structure;
and carrying out ion implantation on the channel layer to form two epitaxial ion implantation areas in the channel layer, wherein the two epitaxial ion implantation areas are respectively positioned right above the two ion implantation areas so as to form the floating gate type flash memory structure.
Preferably, in the manufacturing method, the number of layers of the epitaxial layer is matched with the number of layers of the floating gate polysilicon layer, each layer of the epitaxial layer corresponds to two floating gates, and the floating gates are respectively positioned on two sides of the control gate.
Optionally, in the step of forming a channel layer, the channel layer includes a first epitaxial layer and a second epitaxial layer; forming the first epitaxial layer over the substrate; performing ion implantation on the first epitaxial layer, and forming two first epitaxial ion implantation regions in the first epitaxial layer, wherein the two first epitaxial ion implantation regions are respectively positioned right above the two ion implantation regions in the substrate; the second epitaxial layer is formed over the first epitaxial layer.
Optionally, in the manufacturing method, the first epitaxial ion implantation region is located on an upper surface of the first epitaxial layer.
Optionally, in the step of forming a floating gate layer in the groove, and an upper surface of the floating gate layer is lower than an upper surface of the channel layer, the floating gate layer includes a first floating gate polysilicon layer and a second floating gate polysilicon layer; forming a first floating gate polycrystalline silicon layer in the groove, wherein the upper surface of the first floating gate polycrystalline silicon layer is lower than the upper surface of the first epitaxial layer; forming an insulating layer on the first floating gate polycrystalline silicon layer, wherein the upper surface of the insulating layer is lower than the lower surface of the second epitaxial layer; and depositing a second floating gate polysilicon layer on the insulating layer, wherein the upper surface of the second floating gate polysilicon layer is lower than the upper surface of the second epitaxial layer.
Furthermore, in the manufacturing method, the thickness ranges of the first floating gate polysilicon layer and the second floating gate polysilicon layer are both 300 angstroms to 800 angstroms.
Optionally, in the manufacturing method, the width of the control gate is between 50 nm and 200 nm.
Optionally, before forming the floating gate layer in the groove, the method further includes: depositing a first oxide layer on the bottom of the recess, and growing a tunnel oxide layer on the sidewalls of the recess, the floating gate layer being deposited over the first oxide layer.
Optionally, before etching the floating gate layer, the method further includes: and forming side wall structures respectively covering two sides of the upper surface of the floating gate layer, covering the exposed side walls of the groove, and etching the floating gate layer by taking the side wall structures as masks.
Optionally, in the manufacturing method, a protective layer is further covered on the surface of the floating gate type flash memory structure.
Preferably, in the manufacturing method, the channel layer is formed on the substrate by a silicon-based epitaxy method.
Further, in the manufacturing method, the base is a P-type silicon substrate.
Further, in the manufacturing method, N-type ion implantation is performed in the substrate and in the channel layer.
Compared with the prior art, the invention has the following beneficial effects:
the invention increases the contact area of the control gate and the floating gate by improving the wrapping mode of the control gate and the floating gate, forms a channel layer on the substrate, forms ion injection regions in the substrate and the channel layer respectively, arranges a grid structure in a groove which penetrates through the channel layer and extends into the substrate so as to form a vertical channel in the channel layer, the grid structure comprises a control gate, an inter-gate dielectric layer and at least two floating gates, the floating gates are arranged at two sides of the control gate, each floating gate is arranged at the side wall close to the groove, the control gate vertically penetrates through the channel layer, and the inter-gate dielectric layer separates the control gate from each floating gate so as to enable the control gate and each floating gate to form a storage unit. In the floating gate type flash memory structure, when a high voltage is applied to a drain end, a hot carrier is generated at the drain end, and then the hot carrier is pulled into the floating gate by utilizing the positive voltage of the control gate, so that the writing of a device is realized; when the control gate is applied with higher negative voltage, electrons in the floating gate are pushed out, so that the erasing function of the device is realized. Therefore, the floating gate type flash memory structure can simultaneously realize the storage of a plurality of bits in a single groove, and the control gate is shared, so that the size of the device is further reduced, the storage density of the device is improved, the cost is reduced, and the competitiveness is improved on the premise of not influencing the performance of the device.
Drawings
FIG. 1 is a diagram illustrating a floating gate type flash memory structure according to the prior art;
FIG. 2 is a schematic structural diagram of a floating gate flash memory structure according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a floating gate type flash memory structure according to an embodiment of the present invention;
fig. 4 to fig. 11 are schematic structural diagrams corresponding to steps in a method for manufacturing a floating gate type flash memory structure according to a first embodiment of the present invention;
FIG. 12 is a schematic structural diagram of a floating gate type flash memory structure according to a second embodiment of the present invention;
fig. 13 to fig. 15 are schematic structural diagrams corresponding to relevant steps in a method for manufacturing a floating gate type flash memory structure according to a second embodiment of the present invention.
Detailed Description
A floating gate type flash memory structure and method of fabricating the same of the present invention will now be described in more detail, with reference to the flow charts and schematic diagrams, wherein preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The core idea of the present invention is that the present invention provides a floating gate type flash memory structure, comprising:
the ion implantation device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein two ion implantation regions are arranged in the substrate;
the channel layer is positioned on the substrate and comprises at least one epitaxial layer, two epitaxial ion implantation regions are arranged in each epitaxial layer, and the two epitaxial ion implantation regions in the epitaxial layers are respectively positioned right above the two ion implantation regions in the substrate;
a groove, wherein the groove penetrates through the channel layer and extends into the substrate, and the groove is positioned between two ion implantation regions in the substrate;
the grid structure is arranged in the groove, one end of the grid structure extends into the substrate, and the other end of the grid structure is close to the upper surface of the channel layer; wherein,
the grid structure comprises a control grid, an inter-grid dielectric layer and at least two floating grids, the floating grids are arranged on two sides of the control grid, each floating grid is arranged on the side wall close to the groove, the control grid vertically penetrates through the channel layer, and the inter-grid dielectric layer isolates the control grid from each floating grid.
Correspondingly, according to another aspect of the present invention, the present invention further provides a method for manufacturing a floating gate type flash memory structure, where the method includes the following steps:
s1, providing a substrate, and performing ion implantation on the substrate to form two ion implantation areas on the substrate;
s2, forming a channel layer, wherein the channel layer is positioned on the substrate and comprises at least one epitaxial layer;
s3, forming a groove, wherein the groove penetrates through the channel layer and extends into the substrate, and the groove is positioned between the two ion implantation regions;
s4, forming a floating gate layer in the groove, wherein the upper surface of the floating gate layer is lower than that of the channel layer, and the floating gate layer comprises at least one floating gate polysilicon layer;
s5, etching the floating gate layer to form at least two floating gates;
s6, forming an inter-gate dielectric layer and a control gate between the at least two floating gates, wherein the control gate vertically penetrates through the channel layer, and the inter-gate dielectric layer separates the control gate from each floating gate to form a gate structure;
s7, performing ion implantation on the channel layer, and forming two epitaxial ion implantation areas in the channel layer, wherein the two epitaxial ion implantation areas are respectively located right above the two ion implantation areas in the substrate, so as to form the floating gate type flash memory structure.
The invention increases the contact area of the control gate and the floating gate by improving the wrapping mode of the control gate and the floating gate, forms a channel layer on the substrate, forms ion injection regions in the substrate and the channel layer respectively, arranges a grid structure in a groove which penetrates through the channel layer and extends into the substrate so as to form a vertical channel in the channel layer, the grid structure comprises a control gate, an inter-gate dielectric layer and at least two floating gates, the floating gates are arranged at two sides of the control gate, each floating gate is arranged at the side wall close to the groove, the control gate vertically penetrates through the channel layer, and the inter-gate dielectric layer separates the control gate from each floating gate so as to enable the control gate and each floating gate to form a storage unit. In the floating gate type flash memory structure, when a high voltage is applied to a drain end, a hot carrier is generated at the drain end, and then the hot carrier is pulled into the floating gate by utilizing the positive voltage of the control gate, so that the writing of a device is realized; when the control gate is applied with higher negative voltage, electrons in the floating gate are pushed out, so that the erasing function of the device is realized. Therefore, the floating gate type flash memory structure can simultaneously realize the storage of a plurality of bits in a single groove, and the control gate is shared, so that the size of the device is further reduced, the storage density of the device is improved, the cost is reduced, and the competitiveness is improved on the premise of not influencing the performance of the device.
The following embodiments of a floating gate type flash memory structure and a method for fabricating the same are illustrated to describe the contents of a floating gate type flash memory structure and a method for fabricating the same in detail, it should be understood that the contents of the present invention are not limited to the following embodiments, and other modifications by conventional technical means of those skilled in the art are within the scope of the idea of the present invention.
Example 1:
referring to fig. 2, fig. 2 is a schematic diagram of the floating gate type flash memory structure in the present embodiment, the floating gate type flash memory structure includes a base 20, the base 20 is a P-type silicon substrate, and the base 20 has two N-type ion implantation regions a1 and a 2; a channel layer 21, in this embodiment, the channel layer 21 has only one epitaxial layer 21, and there are two N-type ion implantation regions B1 and B2 in the epitaxial layer 21, where the ion implantation regions B1 and B2 are located directly above the ion implantation regions a1 and a2, respectively; a groove extending through the channel layer 21 into the substrate 20 and located between two ion implantation regions a1 and a2 of the substrate 20; the floating gate type flash memory structure further includes a gate structure disposed in the groove, one end of the gate structure extends into the substrate 20, and the other end of the gate structure is adjacent to the upper surface of the epitaxial layer 21, so as to form a vertical channel in the channel layer (epitaxial layer) 21.
Specifically, in this embodiment, the gate structure includes two floating gates 25 ', an inter-gate dielectric layer (such as an ONO layer) 27 and a control gate 28, the floating gates 25' are located at two sides of the control gate 28, each floating gate 25 'is disposed adjacent to a sidewall of the recess, the control gate 28 vertically penetrates through the channel layer (epitaxial layer) 21, the control gate 28 is flush with an upper surface of the floating gate 25', and the inter-gate dielectric layer 27 isolates the control gate 28 from each floating gate 25 ', so that the control gate 28 and each floating gate 25' form a memory cell, that is, 2 memory cells share one control gate 28, thereby further reducing the size of the device, improving the memory density of the device, reducing the cost, and improving the competitiveness.
In addition, the floating gate flash memory structure further includes a first oxide layer covering the bottom of the trench, a tunnel oxide layer on the sidewall of the trench, and a protection layer 29 covering the gate structure, and preferably, the first oxide layer and the tunnel oxide layer are both silicon dioxide layers 24.
Next, please refer to fig. 3 to 11, wherein fig. 3 is a flowchart illustrating the manufacturing method of the present embodiment, and fig. 4 to 11 are schematic structural diagrams corresponding to the steps of the manufacturing method, and the specific manufacturing steps include:
in step S1, a substrate 20 is provided, and ion implantation is performed on the substrate 20 to form two ion implantation regions a1 and a2 in the substrate 20. Preferably, in this embodiment, the base 20 is a P-type silicon substrate, and N-type ion implantation is performed on the P-type silicon substrate 20, that is, both the ion implantation regions a1 and a2 are N-type ion implantation regions, as shown in fig. 4. Of course, in other embodiments, the substrate 20 may also be a Ge substrate, a SiGe substrate, a SiC substrate, an SOI (silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like, may also be a substrate including other element semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., a gallium nitride substrate, a gallium arsenide substrate, or the like), may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as an SGOI (silicon Germanium On Insulator) or the like. The conductivity type of the ion implantation area is opposite to that of the substrate.
In step S2, a channel layer 21 is formed, wherein the channel layer 21 is located on the substrate 20. Preferably, the channel layer 21 is obtained on the P-type silicon substrate 20 by a silicon-based epitaxial growth method, in this embodiment, the channel layer 21 has only one epitaxial layer 21 (the epitaxial layer 21 is a P-type epitaxial layer), as shown in fig. 5.
Step S3, forming a recess extending through the channel layer 21 and into the substrate 20, the recess being located between the two ion implantations a1 and a 2. Specifically, the manufacturing process of the groove comprises the following steps: an oxide layer 22 and a silicon nitride layer 23 are sequentially deposited on the epitaxial layer 21 as the mask layer, and the recess is formed by using photolithography and dry etching processes, as shown in fig. 6 (the structure shown by the arrow in the figure is the recess). The photolithography and dry etching processes in this step are well known to those skilled in the art and will not be described herein.
Step S4 is to form a floating gate layer 25 in the recess, and the upper surface of the floating gate layer 25 is lower than the upper surface of the channel layer 21. Preferably, before forming the floating gate layer 25, a first oxide layer 240 is deposited on the bottom of the recess, and a tunnel oxide layer 241 is grown on the sidewalls of the recess. In detail, an oxide is deposited on the semiconductor structure formed in the step S3, a planarization process is performed on the oxide by using a chemical mechanical polishing process and stops on the silicon nitride layer 23, and then an oxide etch-back process is performed to leave an oxide layer with a certain thickness at the bottom of the trench to form the first oxide layer 240, in this embodiment, the upper surface of the first oxide layer 240 is lower than the upper surface of the substrate 20; the process of growing tunnel oxide 241 on the sidewalls of the recess may be a process known to those skilled in the art, and will not be described herein, resulting in the structure shown in fig. 7. Typically, the materials of the first oxide layer 240 and the tunnel oxide layer 241 are silicon dioxide;
next, a floating gate layer 25 is formed on the first oxide layer 240, and the floating gate layer 25 includes only a floating gate polysilicon layer 25. Specifically, after a layer of polysilicon is deposited on the semiconductor structure and a chemical mechanical polishing process is performed to polish the layer of polysilicon to the plane of the silicon nitride layer 23, the polysilicon is etched back to form a floating gate polysilicon layer 25 covering the upper surface of the first oxide layer 240, and the upper surface of the floating gate polysilicon layer 25 is lower than the upper surface of the channel layer 21 (the specific value of the thickness may be set by a person skilled in the art according to actual requirements, for example, the thickness of the floating gate polysilicon layer 25 may be in the range of 300 angstroms to 800 angstroms), as shown in fig. 8.
Step S5, the floating gate layer 25 is etched to form two floating gates 25 'respectively located at two sides of the groove (i.e. the floating gates 25' are both close to the side wall of the groove). Preferably, before the floating gate layer 25 is etched, a sidewall structure 26 is further formed to cover both sides of the upper surface of the floating gate layer 25, respectively, so as to cover the exposed sidewall of the groove. Preferably, in this embodiment, the sidewall structure 26 is made of silicon oxide (in other embodiments, the sidewall structure 26 may also be made of a silicon nitride layer), specifically, silicon oxide is deposited above the floating gate layer 25 and fills the groove, and then partial etching is performed on the silicon oxide to obtain the sidewall structure 26, as shown in fig. 9. Then, the floating gate layer 25 is etched by using the sidewall structures 26 as masks, so as to form the structure shown in fig. 10.
In step S6, an intergate dielectric layer 27 and a control gate 28 are formed between the two floating gates 25'. Specifically, the inter-gate dielectric layer 27 covers the exposed sidewalls of the two floating gates 25', the exposed sidewalls of the sidewall structures 26, and the upper surface of the first oxide layer 240, and the process of the inter-gate dielectric layer (oxide layer-nitride layer-oxide layer) 27 is not a key point of the improvement of the present invention, and is also a well-known process by those skilled in the art, and is not described herein again; then, a control polysilicon layer is deposited in the recess (i.e. the middle region of the recess) of the above structure until the recess is filled, and a dry etching process is used to etch back the control polysilicon layer to a position flush with the upper surfaces of the two floating gates 25 ', so as to form the control gate 28, i.e. the control gate 28 vertically penetrates through the channel layer 21, and the floating gates 25' are arranged at two sides of the control gate 28, preferably, the width of the control gate 28 is between 50 nm and 200 nm, the upper surfaces of the control gate 28 and the two floating gates 25 'are flush with each other and are lower than the upper surface of the channel layer 21, and the floating gate 25' and the control gate 28 are separated by the inter-gate dielectric layer 27, as shown in fig. 11.
Step S7, performing ion implantation on the channel layer 21, and forming two epitaxial ion implantation regions B1 and B2 in the channel layer 21, where the two epitaxial ion implantation regions B1 and B2 of the channel layer 21 are respectively located right above the ion implantation regions a1 and a2, so as to form the floating gate flash memory structure. Of course, before the ion implantation into the channel layer 21, the mask layer (the silicon nitride layer 23 and the oxide layer 22) and the sidewall structures 26 are removed by a certain etching process, and meanwhile, the excess portions of the inter-gate dielectric layer 27 and the tunnel oxide layer 241 are also removed, which can be understood by those skilled in the art. Finally, a protective layer 29 is further covered on the floating gate type flash memory structure, and the material of the protective layer 29 is silicon dioxide in common use. Finally, the structure shown in fig. 2 is formed (note that, in this embodiment, the materials of the first oxide layer 240 and the tunnel oxide layer 241 are both silicon dioxide layers, so that, in fig. 2, the first oxide layer 240 and the tunnel oxide layer 241 are collectively referred to as a silicon dioxide layer 24).
In this embodiment, a vertical channel is formed in the channel layer 21 by forming a channel layer 21 on the substrate 20, providing two ion implantation regions in the substrate 20 and two epitaxial ion implantation regions in the channel layer 21, and providing a gate structure in a recess extending through the channel layer 21 into the substrate 20, the gate structure including a control gate 28, an intergate dielectric layer 27 and two floating gates 25'. Therefore, the floating gate type flash memory structure can simultaneously realize the storage of 2 bits in a single groove, and 2 memory cells share one control gate, so that the size of the device is further reduced, the storage density of the device is improved, the cost is reduced, and the competitiveness is improved.
Example 2:
referring to fig. 12 to 15, fig. 12 is a schematic diagram of a floating gate type flash memory structure in a second embodiment, and fig. 13 to 15 are structural diagrams corresponding to relevant steps of a manufacturing method of the floating gate type flash memory structure in the present embodiment. In fig. 12 to 15, reference numerals denote structures that are the same as those in fig. 2 and 4 to 11 and that are the same as those in the first embodiment, and a floating gate type flash memory structure in the second embodiment is substantially the same as that in the first embodiment, except that: in the second embodiment, the channel layer 21 includes a first epitaxial layer 210 and a second epitaxial layer 211, and two first epitaxial ion implantation regions C1 and C2 are provided in the first epitaxial layer 210, two epitaxial ion implantation regions B1 and B2 are provided in the second epitaxial layer 211, and the first epitaxial ion implantation regions (C1 and C2) and the epitaxial ion implantation regions (B1 and B2) are both N-type ion implantation regions; the floating gate structure is provided with 4 floating gates 25 ', the 4 floating gates 25' are arranged side by side up and down in pairs, and the upper floating gate 25 'and the lower floating gate 25' are separated by an insulating layer (silicon dioxide).
Accordingly, the manufacturing method of the floating gate type flash memory structure in the second embodiment is also substantially the same as that in the first embodiment, wherein the manufacturing methods of steps S1, S3, S5-S7 are completely the same, and the difference is that:
in step S2, the channel layer 21 includes a first epitaxial layer 210 and a second epitaxial layer 211; specifically, the first epitaxial layer 210 is formed on the substrate 20; performing ion implantation on the first epitaxial layer 210 to form two first epitaxial ion implantation regions C1 and C2 in the first epitaxial layer 210, wherein the two first epitaxial ion implantation regions C1 and C2 of the first epitaxial layer 210 are located directly above the two ion implantation regions a1 and a2 in the substrate 20, and preferably, the two first epitaxial ion implantation regions C1 and C2 are located on the upper surface of the first epitaxial layer 210; then, the second epitaxial layer 211 is formed on the first epitaxial layer 210, and preferably, the first epitaxial layer 210 and the second epitaxial layer 211 are both obtained by a silicon-based epitaxial growth method, as shown in the structure shown in fig. 13.
In step S4 (i.e., in the step of forming the floating gate layer 25 in the recess with the upper surface of the floating gate layer 25 lower than the upper surface of the channel layer 21), the floating gate layer 25 includes a first floating gate polysilicon layer 250 and a second floating gate polysilicon layer 251;
specifically, a first oxide layer 240 is deposited on the bottom of the recess, and a tunnel oxide layer 241 is grown on the sidewalls of the recess; then, a first floating gate polysilicon layer 250 is formed on the first oxide layer 240, the upper surface of the first floating gate polysilicon layer 250 is lower than the upper surface of the first epitaxial layer 210, and the method for depositing the first floating gate polysilicon layer 250 refers to the process for forming the floating gate layer 25 in the first embodiment (i.e., deposition, chemical mechanical polishing process, and etch-back process); forming an insulating layer 242 on the first floating gate polysilicon layer 250, wherein the upper surface of the insulating layer 242 is lower than the lower surface of the second epitaxial layer 211, and depositing the insulating layer 242 refers to the forming process of the first oxide layer 240 in the first embodiment, and simultaneously, during the forming process of the insulating layer 242, a portion of the tunnel oxide layer 241 on the insulating layer 242 is etched away, which can be known by those skilled in the art. Usually, the material of the insulating layer 242 is silicon dioxide, such as the structure shown in fig. 14;
next, a second floating gate polysilicon layer 251 is deposited on the insulating layer 242, wherein the upper surface of the second floating gate polysilicon layer 251 is lower than the upper surface of the second epitaxial layer 211. Of course, a tunnel oxide layer 243 (different numbers are used for tunnel oxide layers only to show the specific steps for tunnel oxide layer formation) is formed on the exposed sidewalls of the trench before the second floating gate polysilicon layer 251 is deposited. The method for forming the second floating gate polysilicon layer 251 is the same as the method for forming the first floating gate polysilicon layer 250, and preferably, the thicknesses of the first floating gate polysilicon layer 250 and the second floating gate polysilicon layer 251 can be in the range of 300 angstroms to 800 angstroms, as shown in the structure of fig. 15. (note that the materials of the first oxide layer 240, the first tunnel oxide layer 241, the insulating layer 242, and the second tunnel oxide layer 243 in fig. 15 are all silicon dioxide layers, and thus, the above structures are collectively identified as silicon dioxide layers 24 in fig. 12.)
Referring to steps S5 to S7 in the first embodiment, the floating gate flash memory structure shown in fig. 12 is finally formed.
In the second embodiment, a vertical channel is formed in the channel layer 21 by forming a channel layer 21 including two epitaxial layers on the substrate 20, providing two ion implantation regions on the substrate 20, providing two first epitaxial ion implantation regions in the first epitaxial layer 210, and providing two epitaxial ion implantation regions in the second epitaxial layer 211, and providing a gate structure in a recess extending through the channel layer 21 into the substrate 20, the gate structure including a control gate 28, an intergate dielectric layer 27, and 4 floating gates 25 '(the floating gate layer 25 includes two floating gate polysilicon layers, and 4 floating gates 25' are obtained by etching and dividing). Therefore, in the floating gate type flash memory structure, 4 bits of storage can be simultaneously realized in a single groove, and 4 storage units share one control gate 28, so that the storage density of the device is further improved, the cost is reduced, and the competitiveness is improved.
Obviously, in other embodiments, the channel layer 21 may also be a plurality of epitaxial layers according to actual requirements, and the floating gate layer 25 may also be a plurality of floating gate polysilicon layers, as long as the number of the epitaxial layers 21 is matched with the number of the floating gate layer 25, and each layer of the epitaxial layers corresponds to two floating gates 25', so that the purpose of improving the storage density of the device can be achieved, and the performance of the device is not affected.
In summary, the present invention increases the contact area between the control gate and the floating gate by improving the wrapping manner between the control gate and the floating gate, forms a channel layer on the substrate, and forms ion implantation regions in the substrate and the channel layer, respectively, and arranges a gate structure in a groove extending through the channel layer to the substrate to form a vertical channel in the channel layer, where the gate structure includes a control gate, an inter-gate dielectric layer and at least two floating gates, the floating gates are arranged on two sides of the control gate, each floating gate is arranged on a sidewall near the groove, the control gate vertically penetrates through the channel layer, and the inter-gate dielectric layer separates the control gate from each floating gate, so that the control gate and each floating gate form a memory cell. In the floating gate type flash memory structure, when a high voltage is applied to a drain end, a hot carrier is generated at the drain end, and then the hot carrier is pulled into the floating gate by utilizing the positive voltage of the control gate, so that the writing of a device is realized; when the control gate is applied with higher negative voltage, electrons in the floating gate are pushed out, so that the erasing function of the device is realized. Therefore, the floating gate type flash memory structure can simultaneously realize the storage of a plurality of bits in a single groove, and the control gate is shared, so that the size of the device is further reduced, the storage density of the device is improved, the cost is reduced, and the competitiveness is improved on the premise of not influencing the performance of the device.
In addition, it should be noted that the terms "first" and "second" and the like in the description are used for distinguishing each component, element, step and the like in the description, and are not used for representing a logical relationship or a sequential relationship between each component, element, step and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (21)
1. A floating gate type flash memory structure, comprising:
the ion implantation device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein two ion implantation regions are arranged in the substrate;
the channel layer is positioned on the substrate and comprises at least one epitaxial layer, two epitaxial ion implantation regions are arranged in each epitaxial layer, and the two epitaxial ion implantation regions in the epitaxial layers are respectively positioned right above the two ion implantation regions in the substrate;
a groove, wherein the groove penetrates through the channel layer and extends into the substrate, and the groove is positioned between two ion implantation regions in the substrate;
the grid structure is arranged in the groove, one end of the grid structure extends into the substrate, and the other end of the grid structure is close to the upper surface of the channel layer; wherein,
the grid structure comprises a control grid, an inter-grid dielectric layer and at least two floating grids, the floating grids are arranged on two sides of the control grid, each floating grid is arranged on the side wall close to the groove, the control grid vertically penetrates through the channel layer, and the inter-grid dielectric layer isolates the control grid from each floating grid.
2. The floating gate type flash memory structure of claim 1 wherein each of said epitaxial layers corresponds to two of said floating gates, said floating gates being located on either side of said control gate.
3. The floating gate type flash memory structure of claim 1, wherein the channel layer comprises a first epitaxial layer and a second epitaxial layer, the first epitaxial layer being located over the substrate, the second epitaxial layer being located over the first epitaxial layer.
4. The floating gate type flash memory structure of claim 3 wherein there are 4 floating gates in said gate structure, said floating gates being arranged side-by-side up and down two by two.
5. The floating gate type flash memory structure of claim 4, further comprising an insulating layer between said floating gates that are adjacent above and below.
6. The floating gate flash memory structure of any one of claims 1-5 further comprising a first oxide layer covering the bottom of the trench, a tunnel oxide layer on the sidewalls of the trench, and a passivation layer covering the gate structure.
7. The floating gate type flash memory structure of claim 6 wherein said base is a P-type silicon substrate.
8. The floating gate type flash memory structure of claim 7 wherein said ion implanted region and epitaxial ion implanted region are both N-type ion implanted regions.
9. A method for manufacturing a floating gate type flash memory structure is characterized by comprising the following steps:
providing a substrate, carrying out ion implantation on the substrate, and forming two ion implantation areas on the substrate;
forming a channel layer, wherein the channel layer is positioned on the substrate and comprises at least one epitaxial layer;
forming a groove, wherein the groove penetrates through the channel layer and extends into the substrate, and the groove is positioned between the two ion implantation regions;
forming a floating gate layer in the groove, wherein the upper surface of the floating gate layer is lower than that of the channel layer, and the floating gate layer comprises at least one floating gate polycrystalline silicon layer;
etching the floating gate layer to form at least two floating gates;
forming an inter-gate dielectric layer and a control gate between the at least two floating gates, wherein the control gate vertically penetrates through the channel layer, and the inter-gate dielectric layer isolates the control gate from each floating gate to form a gate structure;
and carrying out ion implantation on the channel layer to form two epitaxial ion implantation areas in the channel layer, wherein the two epitaxial ion implantation areas are respectively positioned right above the two ion implantation areas so as to form the floating gate type flash memory structure.
10. The method of claim 9, wherein the number of epitaxial layers is matched to the number of floating gate polysilicon layers, each epitaxial layer corresponds to two floating gates, and the floating gates are respectively located on two sides of the control gate.
11. The method of fabricating a floating gate type flash memory structure according to claim 10, wherein in the step of forming a channel layer, the channel layer comprises a first epitaxial layer and a second epitaxial layer;
forming the first epitaxial layer over the substrate;
performing ion implantation on the first epitaxial layer, and forming two first epitaxial ion implantation regions in the first epitaxial layer, wherein the two first epitaxial ion implantation regions are respectively positioned right above the two ion implantation regions in the substrate;
the second epitaxial layer is formed over the first epitaxial layer.
12. The method of claim 11, wherein the first epi-ion implantation region is located on an upper surface of the first epi-layer.
13. The method of claim 11, wherein in the step of forming a floating gate layer in the recess and having an upper surface lower than an upper surface of the channel layer, the floating gate layer comprises a first floating gate polysilicon layer and a second floating gate polysilicon layer;
forming a first floating gate polycrystalline silicon layer in the groove, wherein the upper surface of the first floating gate polycrystalline silicon layer is lower than the upper surface of the first epitaxial layer;
forming an insulating layer on the first floating gate polycrystalline silicon layer, wherein the upper surface of the insulating layer is lower than the lower surface of the second epitaxial layer;
and depositing a second floating gate polysilicon layer on the insulating layer, wherein the upper surface of the second floating gate polysilicon layer is lower than the upper surface of the second epitaxial layer.
14. The method of claim 13, wherein the first floating gate polysilicon layer and the second floating gate polysilicon layer each have a thickness in the range of 300 angstroms to 800 angstroms.
15. The method of any of claims 9 to 14, wherein the control gate has a width of between 50 nm and 200 nm.
16. The method of any of claims 9 to 14, further comprising, before forming the floating gate layer in the recess: depositing a first oxide layer on the bottom of the recess, and growing a tunnel oxide layer on the sidewalls of the recess, the floating gate layer being deposited over the first oxide layer.
17. The method of any of claims 9 to 14, further comprising, before etching the floating gate layer: and forming side wall structures respectively covering two sides of the upper surface of the floating gate layer, covering the exposed side walls of the groove, and etching the floating gate layer by taking the side wall structures as masks.
18. The method as claimed in any one of claims 9 to 14, wherein a protective layer is further covered on the surface of the floating gate type flash memory structure.
19. The method of fabricating a floating gate type flash memory structure according to any one of claims 9 to 14, wherein the channel layer is formed on the substrate by silicon-based epitaxy.
20. The method of any of claims 9 to 14, wherein the substrate is a P-type silicon substrate.
21. The method of claim 20, wherein N-type ion implantation is performed in the substrate and in the channel layer.
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