CN106449414B - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN106449414B CN106449414B CN201610984921.5A CN201610984921A CN106449414B CN 106449414 B CN106449414 B CN 106449414B CN 201610984921 A CN201610984921 A CN 201610984921A CN 106449414 B CN106449414 B CN 106449414B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000002360 preparation method Methods 0.000 title claims abstract description 35
- 230000012010 growth Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 14
- 239000013078 crystal Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 14
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 229910021332 silicide Inorganic materials 0.000 abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 229910005883 NiSi Inorganic materials 0.000 description 6
- 230000009647 facial growth Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of PMOS semiconductor devices and preparation method thereof.Semiconductor devices preparation method of the invention includes: first step: providing semiconductor substrate, and pattern etched semiconductor substrate is to form recess；Second step: the epitaxial growth sige material in semiconductor substrate is recessed；Third step: the first cap is epitaxially-formed in sige material；Four steps: the second cap of epitaxial growth in the first cap.Using can significantly improve cap pattern after the double-canopy cap technique of semiconductor devices preparation method of the invention, be conducive to the formation of subsequent metal silicide.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of semiconductor devices and its preparation
Method, especially PMOS semiconductor devices and preparation method thereof.
Background technique
With the development of integrated circuit, field-effect size is smaller and smaller, and stress technique is introduced in semiconductors manufacture to change
Become the lattice structure in channel, to improve the mobility of the carrier in channel；It is applied on channel from the point of view of existing research
Add tensile stress that can improve the mobility of electronics, and the mobility in hole can be improved by applying compression then.Embedded SiGe technology quilt
Be widely applied to improve the performance of PMOS, embedded SiGe technology by being embedded in sige material in source region and drain region in PMOS,
Compression can be applied to channel region, so that the performance of PMOS is obviously improved.
In embedded germanium silicon technology, SiGe is improved by improving the content of Ge in SiGe layer to the stress of channel, from
And reach the promotion of device performance.However since epitaxial growth has crystal orientation selectivity, (in<100>, epitaxial growth is most fast,<110>
Secondly,<111>extremely difficult growth), easily formed when the region SRAM SiGe epitaxial layer is higher than base plane in the two sides of epitaxial layer<
111 > crystal face.And<111>crystal face is unfavorable for the growth of subsequent cap, so that the uniformity of the region SRAM SiGe cap is very poor
(the cap thickness low LCL of<111>crystal face growth, hardly grow).And the SiGe epitaxial layer of high Ge content, it can not be with metal
Nickel reactant is formed metal silicide (NiSi or NiGeSi), to cause the contact between subsequent CT and SiGe layer bad, is caused
Electric leakage, resistance increase, the problems such as resistance is uncontrollable.And the cap of Distributed Control System (DCS) growth is used then to be easy to appear
The technological problems of PPU short circuit.
For this reason, it may be necessary to which a kind of new technical solution, improves cap pattern, is conducive to subsequent metal silicide (NiSi)
It is formed.
Summary of the invention
The technical problem to be solved by the present invention is to for drawbacks described above exists in the prior art, providing one kind can improve
Cap pattern method in embedded SiGe technique, is conducive to the formation of subsequent metal silicide (NiSi), while can keep away
Exempt from the PPU short circuit in the region SRAM.
In order to achieve the above technical purposes, according to the present invention, a kind of semiconductor devices preparation method is provided, comprising:
First step: semiconductor substrate is provided, and pattern etched semiconductor substrate is to form recess；
Second step: the epitaxial growth sige material in semiconductor substrate is recessed；
Third step: the first cap is epitaxially-formed in sige material；
Four steps: the second cap of epitaxial growth in the first cap.
Preferably, in the semiconductor devices preparation method, the semiconductor devices preparation method is for manufacturing
PMOS semiconductor devices.
Preferably, in the semiconductor devices preparation method, the first cap is on<111>face and<100>face face
Growth rate ratio be 1~50%.
Preferably, in the semiconductor devices preparation method, the second cap is on<111>face and<100>face face
Growth rate ratio be 50~100%.
Preferably, in the semiconductor devices preparation method, the thickness of the first cap and the second cap is than being situated between
Between 0.5 to 2.
Preferably, in the semiconductor devices preparation method, the semiconductor substrate is made of monocrystalline silicon.
Preferably, in the semiconductor devices preparation method, the semiconductor substrate is by soi semiconductor material structure
At.
In order to achieve the above technical purposes, according to the present invention, it provides a kind of using above-mentioned semiconductor device preparation method
Manufactured semiconductor devices.
Using can significantly improve cap pattern after the double-canopy cap technique of semiconductor devices preparation method of the invention, have
Conducive to the formation of subsequent metal silicide (NiSi).
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantage and feature is more easily to understand, in which:
The first step that Fig. 1 schematically shows semiconductor devices preparation method according to the preferred embodiment of the invention obtains
The the first section semiconductor structure diagram arrived.
Fig. 2 schematically shows the first steps of semiconductor devices preparation method according to the preferred embodiment of the invention to obtain
The the second section semiconductor structure diagram arrived.
The second step that Fig. 3 schematically shows semiconductor devices preparation method according to the preferred embodiment of the invention obtains
The the first section semiconductor structure diagram arrived.
Fig. 4 schematically shows the second steps of semiconductor devices preparation method according to the preferred embodiment of the invention to obtain
The the second section semiconductor structure diagram arrived.
The third step that Fig. 5 schematically shows semiconductor devices preparation method according to the preferred embodiment of the invention obtains
The the first section semiconductor structure diagram arrived.
The third step that Fig. 6 schematically shows semiconductor devices preparation method according to the preferred embodiment of the invention obtains
The the second section semiconductor structure diagram arrived.
The four steps that Fig. 7 schematically shows semiconductor devices preparation method according to the preferred embodiment of the invention obtains
The the first section semiconductor structure diagram arrived.
The four steps that Fig. 8 schematically shows semiconductor devices preparation method according to the preferred embodiment of the invention obtains
The the second section semiconductor structure diagram arrived.
It should be noted that attached drawing is not intended to limit the present invention for illustrating the present invention.Note that indicating that the attached drawing of structure can
It can be not necessarily drawn to scale.Also, in attached drawing, same or similar element indicates same or similar label.
Specific embodiment
In order to keep the contents of the present invention more clear and understandable, combined with specific embodiments below with attached drawing in of the invention
Appearance is described in detail.
The present invention relates in terms of semiconductor device processing technology, improve embedded SiGe epitaxial growth more particularly to a kind of
The method of cap pattern in technique, using this method using can significantly improve cap pattern after double-canopy cap technique, favorably
In the formation of subsequent metal silicide (NiSi), while it can be avoided the PPU short circuit in the region SRAM.
Fig. 1 to Fig. 8 schematically shows each of semiconductor devices preparation method according to the preferred embodiment of the invention
The section semiconductor structure diagram that step obtains.
Specifically, as shown in Figures 1 to 8, semiconductor devices preparation method according to the preferred embodiment of the invention includes:
First step: semiconductor substrate is provided, and pattern etched semiconductor substrate is to form recess 10；
Second step: the epitaxial growth sige material 20 in semiconductor substrate is recessed；
Third step: the first cap 30 is epitaxially-formed in sige material 20；
Four steps: the second cap of epitaxial growth 40 in the first cap 30.
For example, the semiconductor substrate is made of monocrystalline silicon.Alternatively, for example, the semiconductor substrate is by soi semiconductor material
Material is constituted.
Preferably, growth rate of first cap 30 on<111>face and<100>face face is than about 1~50% or so.
Preferably, growth rate of second cap 40 on<111>face and<100>face face is more left than about 50~100%
It is right.
It is further preferred that can according to need any thickness proportion for adjusting two layers of cap.For instance, it is preferred that first
The thickness ratio of cap 30 and the second cap 40 is between 0.5 to 2.
It should be noted that the first cap can be first grown when specific growth grows the second cap again, it can also be first
Long second cap grows the first cap again, and the growth sequencing of two layers of cap does not limit.
For example, the semiconductor devices preparation method is advantageously used for manufacture PMOS semiconductor devices.
Using can significantly improve cap pattern after the double-canopy cap technique of semiconductor devices preparation method of the invention, have
Conducive to the formation of subsequent metal silicide (NiSi).
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification, "
Two ", the descriptions such as " third " are used only for distinguishing various components, element, the step etc. in specification, each without being intended to indicate that
Component, element, the logical relation between step or ordinal relation etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any person skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications all are made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of variation.Therefore, anything that does not depart from the technical scheme of the invention are right according to the technical essence of the invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
And it should also be understood that the present invention is not limited thereto and locate the specific method described, compound, material, system
Technology, usage and application are made, they can change.It should also be understood that term described herein be used merely to describe it is specific
Embodiment, rather than be used to limit the scope of the invention.Must be noted that herein and appended claims used in
Singular "one", "an" and "the" include complex reference, unless context explicitly indicates that contrary.Therefore, example
Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
The citation of multiple steps or device, and may include secondary step and second unit.It should be managed with broadest meaning
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as the function of also quoting from the structure
Equivalent.It can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Moreover, the realization of the method and/or system of the embodiment of the present invention may include manual, automatic or selected by executing in combination
Task.Moreover, according to the method for the present invention and/or the real instrument and equipment of the embodiment of system, it is logical using operating system
It crosses hardware, software, or its combination and realizes several selected tasks.
Claims (5)
1. a kind of semiconductor devices preparation method, characterized by comprising:
First step: semiconductor substrate is provided, and pattern etched semiconductor substrate is to form recess；
Second step: the epitaxial growth sige material in semiconductor substrate is recessed；
Third step: the first cap is epitaxially-formed in sige material；
Four steps: the second cap of epitaxial growth in the first cap；
Wherein, growth rate ratio of first cap on<111>face and<100>face face is 1~50%, second lid
Growth rate ratio of the cap layers on<111>face and<100>face face is 50~100%, first cap and second lid
Cap layers are grown according to preset thickness proportion, to avoid the PPU short circuit in the region SRAM.
2. semiconductor devices preparation method according to claim 1, which is characterized in that the semiconductor devices preparation method
For manufacturing PMOS semiconductor devices.
3. semiconductor devices preparation method according to claim 1 or 2, which is characterized in that the first cap and the second lid
The thickness ratio of cap layers is between 0.5 to 2.
4. semiconductor devices preparation method according to claim 1 or 2, which is characterized in that the semiconductor substrate is by list
Crystal silicon is constituted.
5. semiconductor devices preparation method according to claim 1 or 2, which is characterized in that the semiconductor substrate is by SOI
Semiconductor material is constituted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610984921.5A CN106449414B (en) | 2016-11-09 | 2016-11-09 | Semiconductor devices and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610984921.5A CN106449414B (en) | 2016-11-09 | 2016-11-09 | Semiconductor devices and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106449414A CN106449414A (en) | 2017-02-22 |
| CN106449414B true CN106449414B (en) | 2019-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610984921.5A Active CN106449414B (en) | 2016-11-09 | 2016-11-09 | Semiconductor devices and preparation method thereof |
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Families Citing this family (1)
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| CN112201691A (en) * | 2020-09-28 | 2021-01-08 | 上海华力集成电路制造有限公司 | Germanium-silicon source drain structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244263A (en) * | 2015-10-21 | 2016-01-13 | 上海集成电路研发中心有限公司 | Manufacturing method for improving quality of SiGe source and drain area |
| CN105261567A (en) * | 2015-10-27 | 2016-01-20 | 上海华力微电子有限公司 | Method for preparing cap layer of embedded epitaxial silicon-germanium layer |
| CN105742284A (en) * | 2016-02-26 | 2016-07-06 | 上海华力微电子有限公司 | Fabrication method of semiconductor device and semiconductor device |
-
2016
- 2016-11-09 CN CN201610984921.5A patent/CN106449414B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105244263A (en) * | 2015-10-21 | 2016-01-13 | 上海集成电路研发中心有限公司 | Manufacturing method for improving quality of SiGe source and drain area |
| CN105261567A (en) * | 2015-10-27 | 2016-01-20 | 上海华力微电子有限公司 | Method for preparing cap layer of embedded epitaxial silicon-germanium layer |
| CN105742284A (en) * | 2016-02-26 | 2016-07-06 | 上海华力微电子有限公司 | Fabrication method of semiconductor device and semiconductor device |
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| CN106449414A (en) | 2017-02-22 |
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