CN105374665B - The production method of the cap layer of embedded epitaxial Germanium silicon layer - Google Patents
The production method of the cap layer of embedded epitaxial Germanium silicon layer Download PDFInfo
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- CN105374665B CN105374665B CN201510707870.7A CN201510707870A CN105374665B CN 105374665 B CN105374665 B CN 105374665B CN 201510707870 A CN201510707870 A CN 201510707870A CN 105374665 B CN105374665 B CN 105374665B
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- Prior art keywords
- layer
- cap layer
- epitaxial germanium
- germanium silicon
- production method
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- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 71
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 238000000137 annealing Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000002156 mixing Methods 0.000 claims abstract description 19
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims abstract description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000005253 cladding Methods 0.000 claims abstract description 6
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 5
- 206010010144 Completed suicide Diseases 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 18
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 9
- 229910000077 silane Inorganic materials 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000005224 laser annealing Methods 0.000 claims description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 5
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 1
- 238000005660 chlorination reaction Methods 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 229910021334 nickel silicide Inorganic materials 0.000 abstract description 6
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000011068 loading method Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005574 cross-species transmission Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- -1 silicon ion Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
The present invention provides a kind of production method of the cap layer of embedded epitaxial Germanium silicon layer, comprising: provides semiconductor substrate, is formed with embedded epitaxial Germanium silicon layer in the semiconductor substrate, there are fleet plough groove isolation structure in the embedded epitaxial Germanium silicon layer two sides；Cap layer is made using mixing silicon source, includes at least dichlorosilane and another silicon source in the mixing silicon source, and carry out in the cap layer manufacturing process using selective etching gas；Silicon injection technology is carried out to the cap layer；Annealing process is carried out to the cap layer after injection；Nickel suicide technique is carried out to the cap layer after annealing.The present invention solves the problems, such as that the prior art can not form the cap layer of cladding epitaxial Germanium silicon layer completely on embedded epitaxial Germanium silicon layer, prevents reacting for subsequent nickel silicide technique and the germanium silicon of epitaxial Germanium silicon layer, improves therefore bring stress problem.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of production side of the cap layer of embedded epitaxial Germanium silicon layer
Method.
Background technique
With the development of semiconductor technology, the characteristic size of silicon substrate semiconductor device constantly reduces.Various CMOS technologies
Development all under the premise of seeking not dramatically increase semiconductor device creepage, improves device ON state conducting electric current, improves device
The method of speed.Wherein, stress technique is to change silicon substrate semiconductor device channel stress, improve carrier in conducting channel
Mobility, to improve the effective ways of device performance.
The prior art forms epitaxial Germanium silicon layer using epitaxy technique, and the hole of PMOS device is promoted using epitaxial Germanium silicon layer
Channel mobility, and the content of the germanium in epitaxial Germanium silicon is higher, and the compression introduced in the devices is bigger.
Silicon cap layer (Si cap) can be covered, for PMOS device region, on epitaxial Germanium silicon layer to improve epitaxial Germanium silicon layer
Germanium silicon stability, and by formed silicide reduce metal and semiconductor contact resistance.Due to PMOS device region with
Figure difference at SRAM device region is so that the micro- loading effect (micro-loading effect) formed can be equally embodied in
In the growth of epitaxial Germanium silicon layer.
For the silicon cap layer on epitaxial Germanium silicon layer, the region SRAM is because of the hydrofluoric acid clean step before growth epitaxial Germanium silicon layer
It will cause SiO at fleet plough groove isolation structure2Loss, the especially SiO of fleet plough groove isolation structure vertex2It loses more, works as life
Long epitaxial Germanium silicon layer is to can be than PMOS area spill-over (overfill) very much, to<111>crystalline substance occur when being higher by STI vertex
Face, subsequent silicon cap layer can not be grown on this crystal face, but can be grown in<100>crystal face of epitaxial Germanium silicon layer.Such as Fig. 1 institute
The formation for the prior art shown has the schematic diagram of the section structure of the semiconductor structure of epitaxial Germanium silicon layer.Epitaxial Germanium silicon layer 12 is formed in
In semiconductor substrate 10,12 two sides of epitaxial Germanium silicon layer are fleet plough groove isolation structure 11, to put it more simply, by semiconductor devices in figure
Other structures are omitted.The top of epitaxial Germanium silicon layer 12 is formed with cap layer 13 in figure, and the side of epitaxial Germanium silicon layer 12 is close to shallow
The position at 11 top of groove isolation construction does not have cap layer 13.
After subsequent nickel silicide technique carries out, in<111>crystal face of epitaxial Germanium silicon layer 12 because no silicon cap layer will cause
The epitaxial Germanium silicon layer 12 of high germanium component is directly reacted with nickel, this reaction can bring and connect because the precipitation of germanium component forms high resistant phase
The drawbacks of electric shock resistance increases, while because of<111>crystal face (i.e. the side of the close fleet plough groove isolation structure of epitaxial Germanium silicon layer 12) nothing
Silicon cap layer is likely to result in the stress release of the epitaxial Germanium silicon layer of high germanium component.
Summary of the invention
The technical problem to be solved by the present invention is to provide the production method of the cap layer of embedded epitaxial Germanium silicon layer, solve existing
There is technology that can not prevent subsequent the problem of forming the cap layer of cladding epitaxial Germanium silicon layer completely on embedded epitaxial Germanium silicon layer
Nickel silicide technique is reacted with the germanium silicon of epitaxial Germanium silicon layer, improves therefore bring stress problem.
To solve the above-mentioned problems, the present invention provides a kind of production method of the cap layer of embedded epitaxial Germanium silicon layer, packet
It includes:
Semiconductor substrate is provided, is formed with embedded epitaxial Germanium silicon layer, the embedded extension in the semiconductor substrate
There are fleet plough groove isolation structure in germanium silicon layer two sides；
Cap layer is made using mixing silicon source, includes at least dichlorosilane and another silicon in the mixing silicon source
Source, and carried out in the cap layer manufacturing process using selective etching gas；
Silicon injection technology is carried out to the cap layer；
Annealing process is carried out to the cap layer after injection；
Nickel suicide technique is carried out to the cap layer after annealing.
Optionally, the mixing silicon source includes dichlorosilane and silane.
Optionally, the mixing silicon source is the mixing of dichlorosilane and silane, wherein the stream of dichlorosilane and silane
Amount ratio is 2:1-5:1.
Optionally, the selective etching gas is hydrogen chloride gas.
Optionally, the range of flow of the hydrogen chloride gas is 70-200sccm.
Optionally, the Production Time range of the cap layer is 200-1000 seconds, and reaction temperature is 600-660 degrees Celsius.
Optionally, the energy range of the silicon injection is 1-10KeV, and implantation dosage range is 1.00E14-9.99E15.
Optionally, described to be annealed into spike annealing, laser annealing or flash anneal.
Optionally, the temperature range of the spike annealing is 800-1200 degrees Celsius, and time range is 1-5 seconds；It is described to swash
The temperature range of photo-annealing is 800-1300 degrees Celsius, and time range is 1-60 milliseconds；The temperature range of the flash anneal is
(800-1300 degrees Celsius, time range is 1-60 milliseconds.
Optionally, the thickness range of the cap layer is 50-400 angstroms.
Compared with prior art, mixing silicon source and selective etching gas is utilized in the production of cap layer by the present invention,
The mixed gas uses dichlorosilane and another silicon source, while under the collective effect of selective etching gas,
It is capable of forming the cap layer of uniformly cladding epitaxial Germanium silicon layer, and silicon injection technology has been carried out to cap layer, is increased for cap layer
Silicon source by annealing steps improves the silicon stability of epitaxial Germanium silicon, so that it is not easy stress release occur, while in shape
Make germanium silicon be not involved in reaction when at nickel silicide, reduces contact resistance.
Detailed description of the invention
Fig. 1 is the schematic diagram of the section structure that the formation of the prior art has the semiconductor structure of epitaxial Germanium silicon layer；
Fig. 2 is the schematic diagram of the section structure of the semiconductor structure of the epitaxial Germanium silicon layer formed using method of the invention.
Specific embodiment
The technology prior art that the present invention solves can not form cladding epitaxial Germanium silicon completely on embedded epitaxial Germanium silicon layer
The problem of cap layer of layer, prevents reacting for subsequent nickel silicide technique and the germanium silicon of epitaxial Germanium silicon layer, improves therefore brings
Stress problem.
To solve the above-mentioned problems, the present invention provides a kind of production method of the cap layer of embedded epitaxial Germanium silicon layer, packet
It includes:
Semiconductor substrate is provided, is formed with embedded epitaxial Germanium silicon layer, the embedded extension in the semiconductor substrate
There are fleet plough groove isolation structure in germanium silicon layer two sides；
Cap layer is made using mixing silicon source, includes at least dichlorosilane and another silicon in the mixing silicon source
Source, and carried out in the cap layer manufacturing process using selective etching gas；
Silicon injection technology is carried out to the cap layer；
Annealing process is carried out to the cap layer after injection；
Nickel suicide technique is carried out to the cap layer after annealing.
The cross-section structure signal of the semiconductor structure for the epitaxial Germanium silicon layer that method of the invention as shown in connection with fig. 2 is formed
Figure.Firstly, being formed with fleet plough groove isolation structure 101 in semiconductor substrate 100, epitaxial Germanium silicon layer 102 is located at shallow trench isolation knot
Between structure 101, for the present invention using mixing silicon source and selective etching gas, external in epitaxial Germanium silicon layer 102 forms one layer
Coat the cap layer 103 of epitaxial Germanium silicon layer 102.As one embodiment, the mixing silicon source includes dichlorosilane and silane.
More preferred, the mixing silicon source is the mixing of dichlorosilane and silane, wherein the flow-rate ratio of dichlorosilane and silane
Example is 2:1-5:1.
Selective etching gas of the present invention is hydrogen chloride gas, and the range of flow of the hydrogen chloride gas is 70-
200sccm。
The Production Time range of the cap layer 103 is 200-1000 seconds, and reaction temperature is 600-660 degrees Celsius, is formed
The cap layer 103 thickness range be 50-400 angstroms.
Cap layer 103 formation after, in order to increase the silicone content of cap layer 103, need to cap layer 103 carry out silicon from
Son injection.As preferred embodiment, the energy range of the silicon injection is 1-10KeV, and implantation dosage range is 1.00E14-
9.99E15。
It after silicon injection, anneals to cap layer 103, to activate silicon ion, the silicon for improving epitaxial Germanium silicon layer is stablized
Property.Annealing of the present invention can be spike annealing, laser annealing or flash anneal.
Described to be annealed into spike annealing as one embodiment, the temperature range of the spike annealing is taken the photograph for 800-1200
Family name's degree, time range are 1-5 seconds；It is described to be annealed into laser annealing as another embodiment of the present invention, the laser annealing
Temperature range is 800-1300 degrees Celsius, and time range is 1-60 milliseconds；It is described to be annealed into flash of light and move back as one embodiment
Fire, the temperature range of the flash anneal are 800-1300 degrees Celsius, and time range is 1-60 milliseconds.
To sum up, mixing silicon source and selective etching gas, the mixed gas is utilized in the production of cap layer by the present invention
Using dichlorosilane and another silicon source, while under the collective effect of selective etching gas, it is capable of forming
The cap layer of even cladding epitaxial Germanium silicon layer, and silicon injection technology has been carried out to cap layer, silicon source is increased for cap layer, is passed through
Annealing steps improve the silicon stability of epitaxial Germanium silicon, it is made to be not easy stress release occur, while when forming nickel silicide
So that germanium silicon is not involved in reaction, contact resistance is reduced.
Therefore, the technical concepts and features of above-mentioned preferred embodiment only to illustrate the invention, its object is to allow be familiar with this
The personage of item technology cans understand the content of the present invention and implement it accordingly, and it is not intended to limit the scope of the present invention.It is all
Equivalent change or modification made by Spirit Essence according to the present invention, should be covered by the protection scope of the present invention.
Claims (10)
1. a kind of production method of the cap layer of embedded epitaxial Germanium silicon layer characterized by comprising
Semiconductor substrate is provided, is formed with embedded epitaxial Germanium silicon layer, the embedded epitaxial Germanium silicon in the semiconductor substrate
There are fleet plough groove isolation structure in layer two sides；
It is described mixed in the external cap layer for making one layer of cladding epitaxial germanium layer using mixing silicon source of the epitaxial Germanium silicon layer
It closes and includes at least dichlorosilane and another silicon source in silicon source, and carved in the cap layer manufacturing process using selectivity
Gas is lost to carry out；
Silicon injection technology is carried out to the cap layer；
Annealing process is carried out to the cap layer after injection；
Nickel suicide technique is carried out to the cap layer after annealing.
2. the production method of the cap layer of embedded epitaxial Germanium silicon layer as described in claim 1, which is characterized in that the mixing
Silicon source includes dichlorosilane and silane.
3. the production method of the cap layer of embedded epitaxial Germanium silicon layer as claimed in claim 2, which is characterized in that the mixing
Silicon source is the mixing of dichlorosilane and silane, and wherein the flow proportional of dichlorosilane and silane is 2:1-5:1.
4. the production method of the cap layer of embedded epitaxial Germanium silicon layer as claimed in claim 2, which is characterized in that the selection
Property etching gas be hydrogen chloride gas.
5. the production method of the cap layer of embedded epitaxial Germanium silicon layer as claimed in claim 4, which is characterized in that the chlorination
The range of flow of hydrogen is 70-200sccm.
6. the production method of the cap layer of embedded epitaxial Germanium silicon layer as claimed in claim 2, which is characterized in that the nut cap
The Production Time range of layer is 200-1000 seconds, and reaction temperature is 600-660 degrees Celsius.
7. the production method of the cap layer of embedded epitaxial Germanium silicon layer as described in claim 1, which is characterized in that the silicon note
The energy range entered is 1-10KeV, and implantation dosage range is 1.00E14-9.99E15.
8. the production method of the cap layer of embedded epitaxial Germanium silicon layer as described in claim 1, which is characterized in that the annealing
For spike annealing, laser annealing or flash anneal.
9. the production method of the cap layer of embedded epitaxial Germanium silicon layer as claimed in claim 8, which is characterized in that the spike
The temperature range of annealing is 800-1200 degrees Celsius, and time range is 1-5 seconds；The temperature range of the laser annealing is 800-
1300 degrees Celsius, time range is 1-60 milliseconds；The temperature range of the flash anneal is 800-1300 degrees Celsius, time range
It is 1-60 milliseconds.
10. the production method of the cap layer of embedded epitaxial Germanium silicon layer as described in claim 1, which is characterized in that the lid
The thickness range of cap layers is 50-400 angstroms.
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| CN201510707870.7A CN105374665B (en) | 2015-10-27 | 2015-10-27 | The production method of the cap layer of embedded epitaxial Germanium silicon layer |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425534A (en) * | 2007-10-31 | 2009-05-06 | 周星工程股份有限公司 | Transistor and method of fabricating the same |
| CN102254866A (en) * | 2010-05-20 | 2011-11-23 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor structure |
| CN104752504A (en) * | 2013-12-27 | 2015-07-01 | 台湾积体电路制造股份有限公司 | Semiconductor Device Structure And Method For Manufacturing The Same |
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| CN101740380A (en) * | 2008-11-25 | 2010-06-16 | 上海华虹Nec电子有限公司 | Method for preparing Schottky diode |
| KR101776926B1 (en) * | 2010-09-07 | 2017-09-08 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
| US9064961B2 (en) * | 2013-09-18 | 2015-06-23 | Global Foundries Inc. | Integrated circuits including epitaxially grown strain-inducing fills doped with boron for improved robustness from delimination and methods for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425534A (en) * | 2007-10-31 | 2009-05-06 | 周星工程股份有限公司 | Transistor and method of fabricating the same |
| CN102254866A (en) * | 2010-05-20 | 2011-11-23 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor structure |
| CN104752504A (en) * | 2013-12-27 | 2015-07-01 | 台湾积体电路制造股份有限公司 | Semiconductor Device Structure And Method For Manufacturing The Same |
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